coreboot-gerrit February 2021

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Change in coreboot[master]: soc/intel/skylake/acpi/irqlinks.asl: Fix typo in comment
by Patrick Georgi (Code Review) 05 Feb '21

05 Feb '21

Attention is currently required from: Patrick Rudolph. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50269 ) Change subject: soc/intel/skylake/acpi/irqlinks.asl: Fix typo in comment ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50269 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbe012a9867a6814f64abcfe336e5edca19df879 Gerrit-Change-Number: 50269 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 05 Feb 2021 09:40:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: payloads/libpayload/arch/arm64/mmu.c: Fix typo in comment
by Patrick Georgi (Code Review) 05 Feb '21

05 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50268 ) Change subject: payloads/libpayload/arch/arm64/mmu.c: Fix typo in comment ...................................................................... payloads/libpayload/arch/arm64/mmu.c: Fix typo in comment Change-Id: Ieb10a881ef1d983f11318f0f6934491fd19fd0bf Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50268 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M payloads/libpayload/arch/arm64/mmu.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/payloads/libpayload/arch/arm64/mmu.c b/payloads/libpayload/arch/arm64/mmu.c index bc4c233..4c8f8c1 100644 --- a/payloads/libpayload/arch/arm64/mmu.c +++ b/payloads/libpayload/arch/arm64/mmu.c @@ -389,7 +389,7 @@ /* * Func: mmu_is_range_free - * Desc: We need to ensure that the new range being allocated doesnt overlap + * Desc: We need to ensure that the new range being allocated doesn't overlap * with any used memory range. Basically: * 1. Memory ranges used by the payload (usedmem_ranges) * 2. Any area that falls below _end symbol in linker script (Kernel needs to be -- To view, visit https://review.coreboot.org/c/coreboot/+/50268 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb10a881ef1d983f11318f0f6934491fd19fd0bf Gerrit-Change-Number: 50268 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: Add support for Hynix H9HCNNNBKMMLXR-NEE LP4x DRAM
by Patrick Georgi (Code Review) 05 Feb '21

05 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50271 ) Change subject: mb/google/brya: Add support for Hynix H9HCNNNBKMMLXR-NEE LP4x DRAM ...................................................................... mb/google/brya: Add support for Hynix H9HCNNNBKMMLXR-NEE LP4x DRAM BUG=b:178681161 TEST=abuild Change-Id: Icccfa3d1659e6c74c14a7372ea39c749a5921c64 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50271 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/brya/variants/brya0/memory/Makefile.inc M src/mainboard/google/brya/variants/brya0/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/brya0/memory/mem_list_variant.txt 3 files changed, 3 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/brya0/memory/Makefile.inc b/src/mainboard/google/brya/variants/brya0/memory/Makefile.inc index 03a38b2..b8229c4 100644 --- a/src/mainboard/google/brya/variants/brya0/memory/Makefile.inc +++ b/src/mainboard/google/brya/variants/brya0/memory/Makefile.inc @@ -2,4 +2,4 @@ ## This is an auto-generated file. Do not edit!! SPD_SOURCES = -SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:F +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:F, H9HCNNNBKMMLXR-NEE diff --git a/src/mainboard/google/brya/variants/brya0/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/brya0/memory/dram_id.generated.txt index 93934ae..45b69ae 100644 --- a/src/mainboard/google/brya/variants/brya0/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/brya0/memory/dram_id.generated.txt @@ -1,2 +1,3 @@ DRAM Part Name ID to assign MT53E512M32D2NP-046 WT:F 0 (0000) +H9HCNNNBKMMLXR-NEE 0 (0000) diff --git a/src/mainboard/google/brya/variants/brya0/memory/mem_list_variant.txt b/src/mainboard/google/brya/variants/brya0/memory/mem_list_variant.txt index fb014a3..5f83732 100644 --- a/src/mainboard/google/brya/variants/brya0/memory/mem_list_variant.txt +++ b/src/mainboard/google/brya/variants/brya0/memory/mem_list_variant.txt @@ -1 +1,2 @@ MT53E512M32D2NP-046 WT:F +H9HCNNNBKMMLXR-NEE -- To view, visit https://review.coreboot.org/c/coreboot/+/50271 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icccfa3d1659e6c74c14a7372ea39c749a5921c64 Gerrit-Change-Number: 50271 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: mb/apple/macbookair4_2: ACPI support for EC
by Evgeny Zinoviev (Code Review) 05 Feb '21

05 Feb '21

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33103 Change subject: mb/apple/macbookair4_2: ACPI support for EC ...................................................................... mb/apple/macbookair4_2: ACPI support for EC Added ACPI support for battery, AC and LID. I don't have MacBook Air 4,2 to test, but: - I tested it on 5,2; - I found decompiled DSDT for 4,2 and compared registers and bits, they are the same as on 5,2. So it should work. Change-Id: I592cb4501c878fe46684a524e729d32fb1d7920c Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M src/mainboard/apple/macbookair4_2/acpi/ec.asl 1 file changed, 5 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/33103/1 diff --git a/src/mainboard/apple/macbookair4_2/acpi/ec.asl b/src/mainboard/apple/macbookair4_2/acpi/ec.asl index f70cb3d..cd74865 100644 --- a/src/mainboard/apple/macbookair4_2/acpi/ec.asl +++ b/src/mainboard/apple/macbookair4_2/acpi/ec.asl @@ -1,6 +1,8 @@ /* * This file is part of the coreboot project. * + * Copyright (c) 2019 Evgeny Zinoviev <me(a)ch1p.io> + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -11,10 +13,6 @@ * GNU General Public License for more details. */ -Device(EC) -{ - Name (_HID, EISAID("PNP0C09")) - Name (_UID, 0) - Name (_GPE, 23) -/* FIXME: EC support */ -} +#include <ec/apple/acpi/ec.asl> +#include <ec/apple/acpi/ac_60.asl> +#include <ec/apple/acpi/lid_60.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/33103 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I592cb4501c878fe46684a524e729d32fb1d7920c Gerrit-Change-Number: 33103 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell/pch/lpc.c: Program GEN_PMCON_3 in one write
by Angel Pons (Code Review) 05 Feb '21

05 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47045 ) Change subject: soc/intel/broadwell/pch/lpc.c: Program GEN_PMCON_3 in one write ...................................................................... soc/intel/broadwell/pch/lpc.c: Program GEN_PMCON_3 in one write This is what Lynxpoint does. It is equivalent, but simpler. Change-Id: Ifdbb291a6cea0bb29b4e46c7a33c5abe61dbe86b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/pch/lpc.c 1 file changed, 9 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/47045/1 diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c index 550540d..d62a94c 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/soc/intel/broadwell/pch/lpc.c @@ -160,6 +160,15 @@ default: state = "undefined"; } + + reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */ + reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */ + + reg16 &= ~(1 << 10); + reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */ + + reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */ + pci_write_config16(dev, GEN_PMCON_3, reg16); printk(BIOS_INFO, "Set power %s after power failure.\n", state); @@ -178,21 +187,8 @@ static void pch_misc_init(struct device *dev) { u8 reg8; - u16 reg16; u32 reg32; - reg16 = pci_read_config16(dev, GEN_PMCON_3); - - reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */ - reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */ - - reg16 &= ~(1 << 10); - reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */ - - reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */ - - pci_write_config16(dev, GEN_PMCON_3, reg16); - /* Prepare sleep mode */ reg32 = inl(DEFAULT_PMBASE + PM1_CNT); reg32 &= ~SLP_TYP; -- To view, visit https://review.coreboot.org/c/coreboot/+/47045 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdbb291a6cea0bb29b4e46c7a33c5abe61dbe86b Gerrit-Change-Number: 47045 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: ec/apple: ACPI code for Apple MacBooks
by Evgeny Zinoviev (Code Review) 05 Feb '21

05 Feb '21

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33102 Change subject: ec/apple: ACPI code for Apple MacBooks ...................................................................... ec/apple: ACPI code for Apple MacBooks Move ACPI code for Apple MacBooks to a separate directory to avoid it's duplication in mainboards. AC and LID implementation files are named by EC register that's used in them. Older generations (macbook2,1) use 0x01 while newer generations like 2011-2012 Airs use 0x60. Battery registers seem to be the same. Tested on MacBook Air 5,2. Change-Id: I3d4585aac8e3ebbfed6ce4d4e39fbc33ac983069 Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- A src/ec/apple/acpi/ac_01.asl A src/ec/apple/acpi/ac_60.asl A src/ec/apple/acpi/battery.asl A src/ec/apple/acpi/ec.asl A src/ec/apple/acpi/lid_01.asl A src/ec/apple/acpi/lid_60.asl 6 files changed, 405 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/33102/1 diff --git a/src/ec/apple/acpi/ac_01.asl b/src/ec/apple/acpi/ac_01.asl new file mode 100644 index 0000000..86966ae8 --- /dev/null +++ b/src/ec/apple/acpi/ac_01.asl @@ -0,0 +1,42 @@ + + * This file is part of the coreboot project. + * + * Copyright (c) 2019 Evgeny Zinoviev <me(a)ch1p.io> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope(\_SB.PCI0.LPCB.EC) +{ + Field(ERAM, ByteAcc, NoLock, Preserve) + { + Offset(0x01), + 1, + HPAC, 1, /* AC status */ + } + + Device(AC) + { + Name(_HID, "ACPI0003") + Name(_UID, 0x00) + Name(_PCL, Package() { \_SB } ) + + Method(_PSR, 0, NotSerialized) + { + return(HPAC) + } + + Method(_STA, 0, NotSerialized) + { + Return(0x0f) + } + } +} diff --git a/src/ec/apple/acpi/ac_60.asl b/src/ec/apple/acpi/ac_60.asl new file mode 100644 index 0000000..76adea1 --- /dev/null +++ b/src/ec/apple/acpi/ac_60.asl @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2019 Evgeny Zinoviev <me(a)ch1p.io> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope(\_SB.PCI0.LPCB.EC) +{ + Field(ERAM, ByteAcc, NoLock, Preserve) + { + Offset(0x60), + , 1, + HPAC, 1, /* AC status */ + } + + Device(AC) + { + Name(_HID, "ACPI0003") + Name(_UID, 0x00) + Name(_PCL, Package() { \_SB } ) + + Method(_PSR, 0, NotSerialized) + { + return(HPAC) + } + + Method(_STA, 0, NotSerialized) + { + Return(0x0f) + } + } +} diff --git a/src/ec/apple/acpi/battery.asl b/src/ec/apple/acpi/battery.asl new file mode 100644 index 0000000..f1706be --- /dev/null +++ b/src/ec/apple/acpi/battery.asl @@ -0,0 +1,163 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Field(ERAM, ByteAcc, NoLock, Preserve) +{ + Offset(0x20), + SPTR, 8, + SSTS, 8, + SADR, 8, + SCMD, 8, + SBFR, 256, +} + +Field(ERAM, ByteAcc, Lock, Preserve) +{ + Offset(0x24), + SBDW, 16, +} + +Method(SBPC, 0, NotSerialized) +{ + Store(1000, Local0) + While(Local0) + { + If(LEqual(SPTR, 0x00)) + { + Return() + } + + Sleep(1) + Decrement(Local0) + } +} + +Method(SBRW, 2, NotSerialized) +{ + Acquire(ECLK, 0xFFFF) + Store(ShiftLeft(Arg0, 0x01), SADR) + Store(Arg1, SCMD) + Store(0x09, SPTR) + SBPC() + Store(SBDW, Local0) + Release(ECLK) + Return(Local0) +} + +Method(SBRB, 2, NotSerialized) +{ + Acquire(ECLK, 0xFFFF) + Store(ShiftLeft(Arg0, 0x01), SADR) + Store(Arg1, SCMD) + Store(0x0B, SPTR) + SBPC() + Store(SBFR, Local0) + Release(ECLK) + Return(Local0) +} + +Device(BAT0) +{ + Name(_HID, EisaId("PNP0C0A")) + Name(_UID, 0x00) + Name(_PCL, Package() { \_SB }) + + Name(BATS, Package() + { + 0x00, // 0: PowerUnit: Report in mWh + 0xFFFFFFFF, // 1: Design cap + 0xFFFFFFFF, // 2: Last full charge cap + 0x01, // 3: Battery Technology + 10800, // 4: Design Voltage(mV) + 0x00, // 5: Warning design capacity + 200, // 6: Low design capacity + 10, // 7: granularity1 + 10, // 8: granularity2 + "", // 9: Model number + "", // A: Serial number + "", // B: Battery Type + "" // C: OEM information + }) + + Name(BATI, Package() + { + 0, // Battery State + // Bit 0 - discharge + // Bit 1 - charge + // Bit 2 - critical state + 0, // Battery present Rate + 0, // Battery remaining capacity + 0 // Battery present voltage + }) + + Method(_BIF, 0, NotSerialized) + { + Multiply(^^SBRW(0x0B, 0x18), 10, Index(BATS, 0x01)) + Multiply(^^SBRW(0x0B, 0x10), 10, Index(BATS, 0x02)) + Store(^^SBRW(0x0B, 0x19), Index(BATS, 0x04)) + Store(^^SBRB(0x0B, 0x21), Index(BATS, 0x09)) + Store(^^SBRB(0x0B, 0x22), Index(BATS, 0x0B)) + Store(^^SBRB(0x0B, 0x20), Index(BATS, 0x0C)) + + Return(BATS) + } + + Method(_STA, 0, NotSerialized) + { + If(And(^^SBRW(0x0A, 0x01), 0x01)) { + Return(0x1f) + } else { + Return(0x0f) + } + } + + Method(_BST, 0, NotSerialized) + { + /* Check for battery presence. */ + If(LNot(And(^^SBRW(0x0A, 0x01), 0x01))) { + Return(Package(4) { + 0, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF + }) + } + Store(^^SBRW(0x0B, 0x09), Local1) + Store(Local1, Index(BATI, 0x03)) + Store(^^SBRW(0x0B, 0x0A), Local0) + /* Sign-extend Local0. */ + If(And(Local0, 0x8000)) + { + Not(Local0, Local0) + And(Increment(Local0), 0xFFFF, Local0) + } + + Multiply(Local0, Local1, Local0) + Divide(Local0, 1000, , Index(BATI, 1)) + Multiply(^^SBRW(0x0B, 0x0F), 10, Index(BATI, 2)) + If(HPAC) + { + If(LNot(And(^^SBRW(0x0B, 0x16), 0x40))) { + Store(2, Index(BATI, 0)) + } Else { + Store(0, Index(BATI, 0)) + } + } + Else + { + Store(0x01, Index(BATI, 0)) + } + + Return(BATI) + } +} diff --git a/src/ec/apple/acpi/ec.asl b/src/ec/apple/acpi/ec.asl new file mode 100644 index 0000000..982011c --- /dev/null +++ b/src/ec/apple/acpi/ec.asl @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device(EC) +{ + Name(_HID, EISAID("PNP0C09")) + Name(_UID, 0) + + Name(_GPE, 0x17) + Mutex(ECLK, 0) + + OperationRegion(ERAM, EmbeddedControl, 0x00, 0x100) + + /* LID status change. */ + Method(_Q20, 0, NotSerialized) + { + Notify(LID, 0x80) + } + + /* AC status change. */ + Method(_Q21, 0, NotSerialized) + { + Notify(AC, 0x80) + } + + Method(_CRS, 0) + { + Name(ECMD, ResourceTemplate() + { + IO(Decode16, 0x62, 0x62, 1, 1) + IO(Decode16, 0x66, 0x66, 1, 1) + }) + Return(ECMD) + } + + Method(_PRW, 0, NotSerialized) + { + return (Package () { 0x23, 0x04 }) + } + + Method(_INI, 0, NotSerialized) + { + } + +#include "battery.asl" +} diff --git a/src/ec/apple/acpi/lid_01.asl b/src/ec/apple/acpi/lid_01.asl new file mode 100644 index 0000000..88ad045 --- /dev/null +++ b/src/ec/apple/acpi/lid_01.asl @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2019 Evgeny Zinoviev <me(a)ch1p.io> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope(\_SB.PCI0.LPCB.EC) +{ + Field(ERAM, ByteAcc, NoLock, Preserve) + { + Offset(0x01), + LIDS, 1, /* Lid status */ + + Offset(0x02), + WKLD, 1, /* Lid wake */ + } + + Device(LID) + { + Name(_HID, "PNP0C0D") + + Method(_LID, 0, NotSerialized) + { + return(LIDS) + } + + Method(_PRW, 0, NotSerialized) + { + Return (Package() { 0x1d, 0x03 }) + } + + Method(_PSW, 1, NotSerialized) + { + if (Arg0) { + Store(1, WKLD) + } else { + Store(0, WKLD) + } + } + } +} diff --git a/src/ec/apple/acpi/lid_60.asl b/src/ec/apple/acpi/lid_60.asl new file mode 100644 index 0000000..e0836b6 --- /dev/null +++ b/src/ec/apple/acpi/lid_60.asl @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2019 Evgeny Zinoviev <me(a)ch1p.io> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope(\_SB.PCI0.LPCB.EC) +{ + Field(ERAM, ByteAcc, NoLock, Preserve) + { + Offset(0x60), + LIDS, 1, /* Lid status */ + + Offset(0x68), + WKLD, 1, /* Lid wake */ + } + + Device(LID) + { + Name(_HID, "PNP0C0D") + + Method(_LID, 0, NotSerialized) + { + return(LIDS) + } + + Method(_PRW, 0, NotSerialized) + { + Return (Package() { 0x23, 0x04 }) + } + + Method(_PSW, 1, NotSerialized) + { + if (Arg0) { + Store(1, WKLD) + } else { + Store(0, WKLD) + } + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/33102 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d4585aac8e3ebbfed6ce4d4e39fbc33ac983069 Gerrit-Change-Number: 33102 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: intel: Turn `DEFAULT_RCBA` into a Kconfig symbol
by Patrick Georgi (Code Review) 05 Feb '21

05 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50036 ) Change subject: intel: Turn `DEFAULT_RCBA` into a Kconfig symbol ...................................................................... intel: Turn `DEFAULT_RCBA` into a Kconfig symbol Create `FIXED_RCBA_MMIO_BASE` and use it everywhere, except in cases where a pointer cast would be necessary. Instances in Sandy Bridge MRC code were left as-is intentionally, so as not to collide with another cleanup patch train. Tested with BUILD_TIMELESS=1, these boards remain identical: - Asus P8Z77-V LX2 - Packard Bell MS2290 Change-Id: I642958fbd6f02dbf54812d6a75d6bc3087acc77a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50036 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/emulation/qemu-q35/bootblock.c M src/northbridge/intel/gm45/acpi/gm45.asl M src/northbridge/intel/gm45/pcie.c M src/northbridge/intel/haswell/acpi/hostbridge.asl M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/haswell/romstage.c M src/northbridge/intel/i945/acpi/i945.asl M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/ironlake/acpi/ironlake.asl M src/northbridge/intel/pineview/acpi/pineview.asl M src/northbridge/intel/sandybridge/acpi/sandybridge.asl M src/northbridge/intel/x4x/acpi/x4x.asl M src/southbridge/intel/bd82x6x/acpi/pch.asl M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/common/Kconfig M src/southbridge/intel/common/rcba.h M src/southbridge/intel/i82801gx/acpi/ich7.asl M src/southbridge/intel/i82801gx/early_init.c M src/southbridge/intel/i82801ix/acpi/ich9.asl M src/southbridge/intel/i82801ix/early_init.c M src/southbridge/intel/i82801jx/acpi/ich10.asl M src/southbridge/intel/i82801jx/early_init.c M src/southbridge/intel/ibexpeak/bootblock.c M src/southbridge/intel/ibexpeak/early_pch.c M src/southbridge/intel/lynxpoint/acpi/pch.asl M src/southbridge/intel/lynxpoint/bootblock.c M src/southbridge/intel/lynxpoint/early_pch.c M src/southbridge/intel/lynxpoint/lpc.c 29 files changed, 33 insertions(+), 44 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c index cdca27a..e17c8ee 100644 --- a/src/mainboard/emulation/qemu-q35/bootblock.c +++ b/src/mainboard/emulation/qemu-q35/bootblock.c @@ -36,7 +36,7 @@ /* Enable RCBA */ pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, - (uintptr_t)DEFAULT_RCBA | 1); + CONFIG_FIXED_RCBA_MMIO_BASE | 1); } void bootblock_soc_init(void) diff --git a/src/northbridge/intel/gm45/acpi/gm45.asl b/src/northbridge/intel/gm45/acpi/gm45.asl index 7f64219..8c5fb49 100644 --- a/src/northbridge/intel/gm45/acpi/gm45.asl +++ b/src/northbridge/intel/gm45/acpi/gm45.asl @@ -3,7 +3,6 @@ #include "hostbridge.asl" #include "../memmap.h" #include <southbridge/intel/i82801ix/i82801ix.h> -#include <southbridge/intel/common/rcba.h> /* PCI Device Resource Consumption */ Device (PDRC) @@ -14,7 +13,7 @@ // This does not seem to work correctly yet - set values statically for // now. Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) + Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c index fd7ce52..f2c0090 100644 --- a/src/northbridge/intel/gm45/pcie.c +++ b/src/northbridge/intel/gm45/pcie.c @@ -264,7 +264,7 @@ /* Link1: target port 0, component id 2 (ICH), link valid. */ DMIBAR32(DMILE1D) = (0 << 24) | (2 << 16) | (1 << 0); - DMIBAR32(DMILE1A) = (uintptr_t)DEFAULT_RCBA; + DMIBAR32(DMILE1A) = CONFIG_FIXED_RCBA_MMIO_BASE; /* Link2: component ID 1 (MCH), link valid */ DMIBAR32(DMILE2D) = diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 9a39647..50a1306 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include "../haswell.h" -#include <southbridge/intel/common/rcba.h> Name (_HID, EISAID ("PNP0A08")) // PCIe Name (_CID, EISAID ("PNP0A03")) // PCI @@ -175,7 +174,7 @@ Name (_UID, 1) Name (PDRS, ResourceTemplate () { - Memory32Fixed (ReadWrite, DEFAULT_RCBA, 0x00004000) + Memory32Fixed (ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, 0x00004000) Memory32Fixed (ReadWrite, DEFAULT_MCHBAR, 0x00008000) Memory32Fixed (ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed (ReadWrite, DEFAULT_EPBAR, 0x00001000) diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 8af6eb2..c2c8143 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -511,7 +511,7 @@ reg32 &= ~(0xffff << 16); reg32 |= 1 | (2 << 16); DMIBAR32(DMILE1D) = reg32; - DMIBAR64(DMILE1A) = (uintptr_t)DEFAULT_RCBA; + DMIBAR64(DMILE1A) = CONFIG_FIXED_RCBA_MMIO_BASE; DMIBAR64(DMILE2A) = (uintptr_t)DEFAULT_EPBAR; reg32 = DMIBAR32(DMILE2D); diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index 3227c02..f5d500b2 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -56,7 +56,7 @@ .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .hpet_address = HPET_ADDR, - .rcba = (uintptr_t)DEFAULT_RCBA, + .rcba = CONFIG_FIXED_RCBA_MMIO_BASE, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, .temp_mmio_base = 0xfed08000, diff --git a/src/northbridge/intel/i945/acpi/i945.asl b/src/northbridge/intel/i945/acpi/i945.asl index 11d3b50..5e7f4ec 100644 --- a/src/northbridge/intel/i945/acpi/i945.asl +++ b/src/northbridge/intel/i945/acpi/i945.asl @@ -2,7 +2,6 @@ #include "hostbridge.asl" #include "../i945.h" -#include <southbridge/intel/common/rcba.h> /* Operating System Capabilities Method */ Method (_OSC, 4) @@ -38,7 +37,7 @@ //}) Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) + Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index dea4f9b..4564ff4 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -730,7 +730,7 @@ reg32 |= (1 << 0); DMIBAR32(DMILE1D) = reg32; - DMIBAR32(DMILE1A) = (uintptr_t)DEFAULT_RCBA; + DMIBAR32(DMILE1A) = CONFIG_FIXED_RCBA_MMIO_BASE; DMIBAR32(DMILE2D) |= (1 << 16) | (1 << 0); diff --git a/src/northbridge/intel/ironlake/acpi/ironlake.asl b/src/northbridge/intel/ironlake/acpi/ironlake.asl index 73242e4..c43b17b 100644 --- a/src/northbridge/intel/ironlake/acpi/ironlake.asl +++ b/src/northbridge/intel/ironlake/acpi/ironlake.asl @@ -2,7 +2,6 @@ #include "../ironlake.h" #include "hostbridge.asl" -#include <southbridge/intel/common/rcba.h> /* PCI Device Resource Consumption */ Device (PDRC) @@ -11,7 +10,7 @@ Name (_UID, 1) Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) + Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) diff --git a/src/northbridge/intel/pineview/acpi/pineview.asl b/src/northbridge/intel/pineview/acpi/pineview.asl index 4620c4f..2f34b0d 100644 --- a/src/northbridge/intel/pineview/acpi/pineview.asl +++ b/src/northbridge/intel/pineview/acpi/pineview.asl @@ -2,7 +2,6 @@ #include "hostbridge.asl" #include "../memmap.h" -#include <southbridge/intel/common/rcba.h> /* PCI Device Resource Consumption */ Device (PDRC) @@ -13,7 +12,7 @@ /* This does not seem to work correctly yet - set values statically for now. */ Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) + Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl index 1e47c1f..16bcd54 100644 --- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl @@ -2,7 +2,6 @@ #include "hostbridge.asl" #include "peg.asl" -#include <southbridge/intel/common/rcba.h> /* PCI Device Resource Consumption */ Device (PDRC) @@ -11,7 +10,7 @@ Name (_UID, 1) Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) + Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, 0x00004000) // Filled by _CRS Memory32Fixed(ReadWrite, 0, 0x00008000, MCHB) Memory32Fixed(ReadWrite, 0, 0x00001000, DMIB) diff --git a/src/northbridge/intel/x4x/acpi/x4x.asl b/src/northbridge/intel/x4x/acpi/x4x.asl index 33cb7ad..60ee615 100644 --- a/src/northbridge/intel/x4x/acpi/x4x.asl +++ b/src/northbridge/intel/x4x/acpi/x4x.asl @@ -2,7 +2,6 @@ #include "hostbridge.asl" #include "../memmap.h" -#include <southbridge/intel/common/rcba.h> /* PCI Device Resource Consumption */ Device (PDRC) @@ -11,7 +10,7 @@ Name (_UID, 1) Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) + Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl index 4a033ab..8833a5e 100644 --- a/src/southbridge/intel/bd82x6x/acpi/pch.asl +++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl @@ -181,7 +181,7 @@ // ICH7 Root Complex Register Block. Memory Mapped through RCBA) - OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) + OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, 0x4000) Field(RCRB, DWordAcc, Lock, Preserve) { Offset(0x0000), // Backbone diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 767d3ad..6ed3dce 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -218,7 +218,7 @@ static void pch_enable_bars(void) { - pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(PCH_LPC_DEV, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1); pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index bef98fa..28337f6 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -186,7 +186,7 @@ return; /* Verify that RCBA is still valid */ - if (pci_read_config32(PCH_LPC_DEV, RCBA) != ((u32)DEFAULT_RCBA | RCBA_ENABLE)) + if (pci_read_config32(PCH_LPC_DEV, RCBA) != (CONFIG_FIXED_RCBA_MMIO_BASE | RCBA_ENABLE)) return; if (RCBA32(FD) & PCH_DISABLE_XHCI) diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index a14513d..5b5fe55 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -104,6 +104,10 @@ bool depends on SOUTHBRIDGE_INTEL_COMMON_PMBASE +config FIXED_RCBA_MMIO_BASE + hex + default 0xfed1c000 + config FIXED_SMBUS_IO_BASE hex depends on SOUTHBRIDGE_INTEL_COMMON_SMBUS diff --git a/src/southbridge/intel/common/rcba.h b/src/southbridge/intel/common/rcba.h index 712a477..4a9847a 100644 --- a/src/southbridge/intel/common/rcba.h +++ b/src/southbridge/intel/common/rcba.h @@ -3,9 +3,7 @@ #ifndef SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H #define SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H -#ifndef __ACPI__ - -#define DEFAULT_RCBA ((u8 *)0xfed1c000) +#define DEFAULT_RCBA ((u8 *)CONFIG_FIXED_RCBA_MMIO_BASE) /* Root Complex Register Block */ #define RCBA 0xf0 @@ -23,10 +21,4 @@ #define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or) #define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or) -#else - -#define DEFAULT_RCBA 0xfed1c000 - -#endif /* __ACPI__ */ - #endif /* SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H */ diff --git a/src/southbridge/intel/i82801gx/acpi/ich7.asl b/src/southbridge/intel/i82801gx/acpi/ich7.asl index 4d07720..4f55277 100644 --- a/src/southbridge/intel/i82801gx/acpi/ich7.asl +++ b/src/southbridge/intel/i82801gx/acpi/ich7.asl @@ -110,7 +110,7 @@ // ICH7 Root Complex Register Block. Memory Mapped through RCBA) - OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) + OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, 0x4000) Field(RCRB, DWordAcc, Lock, Preserve) { // Backbone diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c index 72281ea..c8a6117 100644 --- a/src/southbridge/intel/i82801gx/early_init.c +++ b/src/southbridge/intel/i82801gx/early_init.c @@ -48,7 +48,7 @@ void i82801gx_setup_bars(void) { const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); - pci_write_config32(d31f0, RCBA, (uint32_t)DEFAULT_RCBA | 1); + pci_write_config32(d31f0, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1); pci_write_config32(d31f0, PMBASE, DEFAULT_PMBASE | 1); pci_write_config8(d31f0, ACPI_CNTL, ACPI_EN); diff --git a/src/southbridge/intel/i82801ix/acpi/ich9.asl b/src/southbridge/intel/i82801ix/acpi/ich9.asl index f720505..3455acf 100644 --- a/src/southbridge/intel/i82801ix/acpi/ich9.asl +++ b/src/southbridge/intel/i82801ix/acpi/ich9.asl @@ -110,7 +110,7 @@ // ICH9 Root Complex Register Block. Memory Mapped through RCBA) - OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) + OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, 0x4000) Field(RCRB, DWordAcc, Lock, Preserve) { Offset(0x0000), // Backbone diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c index 3c0f3ae..f781098 100644 --- a/src/southbridge/intel/i82801ix/early_init.c +++ b/src/southbridge/intel/i82801ix/early_init.c @@ -51,7 +51,7 @@ enable_smbus(); /* Set up RCBA. */ - pci_write_config32(d31f0, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(d31f0, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1); /* Set up PMBASE. */ pci_write_config32(d31f0, D31F0_PMBASE, DEFAULT_PMBASE | 1); diff --git a/src/southbridge/intel/i82801jx/acpi/ich10.asl b/src/southbridge/intel/i82801jx/acpi/ich10.asl index d6136af..53ead1c 100644 --- a/src/southbridge/intel/i82801jx/acpi/ich10.asl +++ b/src/southbridge/intel/i82801jx/acpi/ich10.asl @@ -112,7 +112,7 @@ // ICH10 Root Complex Register Block. Memory Mapped through RCBA) - OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) + OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, 0x4000) Field(RCRB, DWordAcc, Lock, Preserve) { Offset(0x0000), // Backbone diff --git a/src/southbridge/intel/i82801jx/early_init.c b/src/southbridge/intel/i82801jx/early_init.c index 7714609..327c8fc 100644 --- a/src/southbridge/intel/i82801jx/early_init.c +++ b/src/southbridge/intel/i82801jx/early_init.c @@ -50,7 +50,7 @@ const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); /* Set up RCBA. */ - pci_write_config32(d31f0, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(d31f0, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1); /* Set up PMBASE. */ pci_write_config32(d31f0, D31F0_PMBASE, DEFAULT_PMBASE | 1); diff --git a/src/southbridge/intel/ibexpeak/bootblock.c b/src/southbridge/intel/ibexpeak/bootblock.c index 944378e..99fa530 100644 --- a/src/southbridge/intel/ibexpeak/bootblock.c +++ b/src/southbridge/intel/ibexpeak/bootblock.c @@ -80,7 +80,7 @@ /* Enable RCBA */ pci_devfn_t lpc_dev = PCI_DEV(0, 0x1f, 0); - pci_write_config32(lpc_dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(lpc_dev, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1); enable_port80_on_lpc(); set_spi_speed(); diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c index f5285c1..2fa4b52 100644 --- a/src/southbridge/intel/ibexpeak/early_pch.c +++ b/src/southbridge/intel/ibexpeak/early_pch.c @@ -30,7 +30,7 @@ void ibexpeak_setup_bars(void) { printk(BIOS_DEBUG, "Setting up static southbridge registers..."); - pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1); pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); /* Enable ACPI BAR */ diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index a878dc2..f97a5ad 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -19,7 +19,7 @@ } // Root Complex Register Block - OperationRegion (RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) + OperationRegion (RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, 0x4000) Field (RCRB, DWordAcc, Lock, Preserve) { Offset (0x3404), // High Performance Timer Configuration diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index 802c58e..c063bfb 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -7,7 +7,7 @@ static void map_rcba(void) { - pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(PCH_LPC_DEV, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1); } static void enable_port80_on_lpc(void) diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 8cc6a87..ace8b54 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -36,7 +36,7 @@ static void pch_enable_bars(void) { - pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(PCH_LPC_DEV, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1); pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); /* Enable ACPI BAR */ diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 24a5a7e..20b9b43 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -557,9 +557,9 @@ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; /* RCBA */ - if ((uintptr_t)DEFAULT_RCBA < default_decode_base) { + if (CONFIG_FIXED_RCBA_MMIO_BASE < default_decode_base) { res = new_resource(dev, RCBA); - res->base = (resource_t)(uintptr_t)DEFAULT_RCBA; + res->base = (resource_t)CONFIG_FIXED_RCBA_MMIO_BASE; res->size = 16 * 1024; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED | IORESOURCE_RESERVE; -- To view, visit https://review.coreboot.org/c/coreboot/+/50036 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I642958fbd6f02dbf54812d6a75d6bc3087acc77a Gerrit-Change-Number: 50036 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede: Create kracko variant
by Patrick Georgi (Code Review) 05 Feb '21

05 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50255 ) Change subject: mb/google/dedede: Create kracko variant ...................................................................... mb/google/dedede: Create kracko variant Create the kracko variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:178092096 BRANCH=dedede TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_KRACKO Change-Id: I7f8c7a4d4967e99896166ec9dd6b7381b7f6e5ed Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50255 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg(a)chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/Kconfig.name A src/mainboard/google/dedede/variants/kracko/include/variant/ec.h A src/mainboard/google/dedede/variants/kracko/include/variant/gpio.h A src/mainboard/google/dedede/variants/kracko/memory/Makefile.inc A src/mainboard/google/dedede/variants/kracko/memory/dram_id.generated.txt A src/mainboard/google/dedede/variants/kracko/memory/mem_parts_used.txt A src/mainboard/google/dedede/variants/kracko/overridetree.cb 8 files changed, 138 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Paul Fagerburg: Looks good to me, approved diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 466a672..0fbacfc 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -99,6 +99,7 @@ default "Sasuke" if BOARD_GOOGLE_SASUKE default "Storo" if BOARD_GOOGLE_STORO default "Sasukette" if BOARD_GOOGLE_SASUKETTE + default "Kracko" if BOARD_GOOGLE_KRACKO config MAX_CPUS int @@ -134,5 +135,6 @@ default "sasuke" if BOARD_GOOGLE_SASUKE default "storo" if BOARD_GOOGLE_STORO default "sasukette" if BOARD_GOOGLE_SASUKETTE + default "kracko" if BOARD_GOOGLE_KRACKO endif #BOARD_GOOGLE_BASEBOARD_DEDEDE diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 97b90c2..a1d129e 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -104,3 +104,9 @@ bool "-> Sasukette" select BOARD_GOOGLE_BASEBOARD_DEDEDE select BASEBOARD_DEDEDE_LAPTOP + +config BOARD_GOOGLE_KRACKO + bool "-> Kracko" + select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BASEBOARD_DEDEDE_LAPTOP + select DRIVERS_GENERIC_MAX98357A diff --git a/src/mainboard/google/dedede/variants/kracko/include/variant/ec.h b/src/mainboard/google/dedede/variants/kracko/include/variant/ec.h new file mode 100644 index 0000000..08870e0 --- /dev/null +++ b/src/mainboard/google/dedede/variants/kracko/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/dedede/variants/kracko/include/variant/gpio.h b/src/mainboard/google/dedede/variants/kracko/include/variant/gpio.h new file mode 100644 index 0000000..9078664 --- /dev/null +++ b/src/mainboard/google/dedede/variants/kracko/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/dedede/variants/kracko/memory/Makefile.inc b/src/mainboard/google/dedede/variants/kracko/memory/Makefile.inc new file mode 100644 index 0000000..f6282bf --- /dev/null +++ b/src/mainboard/google/dedede/variants/kracko/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR diff --git a/src/mainboard/google/dedede/variants/kracko/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/kracko/memory/dram_id.generated.txt new file mode 100644 index 0000000..856d016 --- /dev/null +++ b/src/mainboard/google/dedede/variants/kracko/memory/dram_id.generated.txt @@ -0,0 +1,4 @@ +DRAM Part Name ID to assign +MT53E512M32D2NP-046 WT:E 0 (0000) +H9HCNNNBKMMLXR-NEE 0 (0000) +K4U6E3S4AA-MGCR 0 (0000) diff --git a/src/mainboard/google/dedede/variants/kracko/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/kracko/memory/mem_parts_used.txt new file mode 100644 index 0000000..26c06b6 --- /dev/null +++ b/src/mainboard/google/dedede/variants/kracko/memory/mem_parts_used.txt @@ -0,0 +1,3 @@ +MT53E512M32D2NP-046 WT:E +H9HCNNNBKMMLXR-NEE +K4U6E3S4AA-MGCR diff --git a/src/mainboard/google/dedede/variants/kracko/overridetree.cb b/src/mainboard/google/dedede/variants/kracko/overridetree.cb new file mode 100644 index 0000000..8620882 --- /dev/null +++ b/src/mainboard/google/dedede/variants/kracko/overridetree.cb @@ -0,0 +1,102 @@ +chip soc/intel/jasperlake + + # USB Port Configuration + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WF Camera + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Trackpad | + #| I2C1 | Digitizer | + #| I2C2 | Touchscreen | + #| I2C3 | | + #| I2C4 | Audio | + #| I2C5 | P-Sensor | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + + device domain 0 on + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""UFCamera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + chip drivers/usb/acpi + register "desc" = ""WFCamera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.6 on end + end + end + end + end # USB xHCI + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)" + register "wake" = "GPE0_DW0_03" + register "probed" = "1" + device i2c 15 on end + end + end #I2C 0 + device pci 15.3 off end #I2C 3 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C 4 + device pci 1f.3 on + chip drivers/generic/max98357a + register "hid" = ""MX98360A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)" + device generic 0 on end + end + end # Intel HDA + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/50255 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f8c7a4d4967e99896166ec9dd6b7381b7f6e5ed Gerrit-Change-Number: 50255 Gerrit-PatchSet: 2 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede: Modify USB 3.0 PHY parameters for galith
by Angel Pons (Code Review) 05 Feb '21

05 Feb '21

Attention is currently required from: Furquan Shaikh, Frank Chu, Tim Wawrzynczak. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50253 ) Change subject: mb/google/dedede: Modify USB 3.0 PHY parameters for galith ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/50253/comment/9797817a_3098397a PS2, Line 7: galith > Galtic/Galnat/Galith be used the same board, create varient name use galtic […] Ah, alright. Thanks for the clarification! -- To view, visit https://review.coreboot.org/c/coreboot/+/50253 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66dc9b5a7280bfd42592b07f160f48797613fdd6 Gerrit-Change-Number: 50253 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 05 Feb 2021 08:57:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: src: Remove redundant include <rules.h>
by Kyösti Mälkki (Code Review) 05 Feb '21

05 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Philipp Hug, Lee Leahy, Marshall Dawson, Huang Jin, Patrick Rudolph, ron minnich, HAOUAS Elyes, Felix Held. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50300 ) Change subject: src: Remove redundant include <rules.h> ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50300 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4692246d059734bb5bad6c64042b64068636ab6 Gerrit-Change-Number: 50300 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Huang Jin <huang.jin(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 05 Feb 2021 08:37:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit February 2021