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Change subject: soc/intel/*: Update microcode as specified for MP-init
......................................................................
Patch Set 13: Code-Review+1
(2 comments)
Patchset:
PS13:
Ack on the pre-FSP platforms and FSP platforms
with neither USE_INTEL_FSP_MP_INIT nor
USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI.
The rest seems hidden in a mist.
File src/soc/intel/alderlake/cpu.c:
https://review.coreboot.org/c/coreboot/+/49899/comment/4ffc95ce_9e913d44
PS13, Line 70: PRMRR
Subrata, Nate, where is the sequence documented for platforms without
`SkipMpInit` but with `CpuMpPpi`? How can we know when things are done?
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Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50306 )
Change subject: util/autoport: Fix a typo in readme.md
......................................................................
util/autoport: Fix a typo in readme.md
Change-Id: Ifa1e751354c644e2ad9613253b90eb5db0a1f043
Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io>
---
M util/autoport/readme.md
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/50306/1
diff --git a/util/autoport/readme.md b/util/autoport/readme.md
index f2b2697..907d600 100644
--- a/util/autoport/readme.md
+++ b/util/autoport/readme.md
@@ -269,7 +269,7 @@
* If they use different data, use several files.
If memory initialization is not working, in particular write training (timB)
-on DIMM's second rank fails, try enbling rank 1 mirroring, which can't be
+on DIMM's second rank fails, try enabling rank 1 mirroring, which can't be
detected by inteltool. It is described by SPD field "Address Mapping from Edge
Connector to DRAM", byte `63` (`0x3f`). Bit 0 describes Rank 1 Mapping,
0 = standard, 1 = mirrored; set it to 1. Bits 1-7 are reserved.
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Change subject: soc/amd/stoneyridge: remove STONEYRIDGE_ACPI_IO_BASE Kconfig option
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/amd/stoneyridge: remove STONEYRIDGE_ prefix of ACPI_IO_BASE define
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
File src/soc/amd/stoneyridge/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/50291/comment/0f992704_903243a1
PS1, Line 30:
Should we line these up?
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Change subject: soc/amd/common: Drop ACPIMMIO bank for SMBus device PCI config
......................................................................
Patch Set 9:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/42685/comment/9d5422d3_b89d4ab7
PS9, Line 12: we execute had control over the UART configuration...
> Well your previous comment says one could have just used PCI config writes, so this change isn't rea […]
i'd expect both to work, but i haven't verified that. when i've verified that, this code can be dropped and i can suggest you a commit message for this
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Change subject: soc/amd/common: Refactor single GPIO programming
......................................................................
Patch Set 14:
(2 comments)
File src/soc/amd/common/block/gpio_banks/gpio.c:
https://review.coreboot.org/c/coreboot/+/42691/comment/62af0c39_6016dc6c
PS4, Line 216: if (gev_tbl == NULL)
> I'm sorry I'm currently being lazy. […]
what you commented on was changed in the last patch and not related to this one, so i'll just ack this
File src/soc/amd/common/block/gpio_banks/gpio.c:
https://review.coreboot.org/c/coreboot/+/42691/comment/0e8e1f1f_e17fcd01
PS14, Line 184: g
> I agree, this is something we can change afterwards
works for me
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EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50050 )
Change subject: soc/intel/skylake: Move L1_substates_control to pcie_rp.h
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Patchset:
PS2:
I suggest align with UPD.. This is why I missed this chip.c. I searched by name..
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