coreboot-gerrit February 2021

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Change in coreboot[master]: mainboard/amd/bilby: Add Bilby CRB board
by ritul guru (Code Review) 05 Feb '21

05 Feb '21

ritul guru has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/50281 ) Change subject: mainboard/amd/bilby: Add Bilby CRB board ...................................................................... Abandoned raised other PR https://review.coreboot.org/c/coreboot/+/50315 -- To view, visit https://review.coreboot.org/c/coreboot/+/50281 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: … [View More]

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Change in coreboot[master]: sb/intel/bd82x6x: Read ME MBP HWA request
by Angel Pons (Code Review) 05 Feb '21

05 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45266 ) Change subject: sb/intel/bd82x6x: Read ME MBP HWA request ...................................................................... sb/intel/bd82x6x: Read ME MBP HWA request On AMT-enabled systems, the ME can request some information about the hardware with a HWA request, which is a specific type of MBP item. Read the information provided by this item into the MBP data struct. This silences a … [View More]spurious error about an unknown MBP item. Handling the HWA request is not simple, and does not appear to be necessary anyway. Change-Id: I4bddad6cbfaaad6854266d760f86c9a90705a200 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/me.h M src/southbridge/intel/bd82x6x/me_8.x.c 2 files changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/45266/1 diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h index 29089a9..2290c63 100644 --- a/src/southbridge/intel/bd82x6x/me.h +++ b/src/southbridge/intel/bd82x6x/me.h @@ -354,6 +354,17 @@ } __packed platform_type_rule_data; typedef struct { + union { + u32 data; + struct { + u32 media_table_push : 1; + u32 reserved : 31; + } bits; + }; + u8 available; +} __packed mbp_hwa_request; + +typedef struct { mefwcaps_sku fw_capabilities; u8 available; } mbp_fw_caps; @@ -382,6 +393,7 @@ mbp_icc_profile icc_profile; tdt_state_info at_state; u32 mfsintegrity; + mbp_hwa_request hwa_request; } me_bios_payload; typedef struct { diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 96e9a51..a701315 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -320,6 +320,10 @@ case MBP_IDENT(KERNEL, MFS_FAILURE): SET_UP_COPY(mfsintegrity); + case MBP_IDENT(HWA, REQUEST): + mbp_data->hwa_request.available = 1; + SET_UP_COPY(hwa_request.data); + default: printk(BIOS_ERR, "ME: Unknown MBP item! Skipping...\n"); while (copy_size--) -- To view, visit https://review.coreboot.org/c/coreboot/+/45266 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4bddad6cbfaaad6854266d760f86c9a90705a200 Gerrit-Change-Number: 45266 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange [View Less]

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Change in coreboot[master]: sb/intel/bd82x6x: Clean up MBP item ID handling
by Angel Pons (Code Review) 05 Feb '21

05 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45263 ) Change subject: sb/intel/bd82x6x: Clean up MBP item ID handling ...................................................................... sb/intel/bd82x6x: Clean up MBP item ID handling Since this ID is only used to concatenate two values, it doesn't matter how it is defined as long as the definition is the same everywhere. Update the `MBP_MAKE_IDENT` macro to match what Lynx Point does. Also, … [View More]improve some log messages to print the components of the item ID. Change-Id: I908a6973ab64b1162ec5b835c7c4ffba671d4f05 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/me.h M src/southbridge/intel/bd82x6x/me_8.x.c 2 files changed, 7 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/45263/1 diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h index dc1fa48..29089a9 100644 --- a/src/southbridge/intel/bd82x6x/me.h +++ b/src/southbridge/intel/bd82x6x/me.h @@ -284,7 +284,7 @@ /* HWA Items */ #define MBP_HWA_REQUEST_ITEM 1 -#define MBP_MAKE_IDENT(appid, item) (((item) << 8) + (appid)) +#define MBP_MAKE_IDENT(appid, item) (((appid) << 8) | (item)) #define MBP_IDENT(appid, item) MBP_MAKE_IDENT(MBP_APPID_##appid, MBP_##appid##_##item##_ITEM) diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 6d0a82d..45e7efe 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -239,7 +239,6 @@ mbp_header mbp_hdr; mbp_item_header mbp_item_hdr; u32 me2host_pending; - u32 mbp_item_id; struct mei_csr host; me2host_pending = me_to_host_words_pending(); @@ -266,7 +265,6 @@ while (mbp_hdr.num_entries--) { u32 *copy_addr; u32 copy_size, buffer_room; - void *p; if (!me2host_pending) { printk(BIOS_ERR, "ME: no mbp data %d entries to go!\n", @@ -285,8 +283,6 @@ me2host_pending -= mbp_item_hdr.length; - mbp_item_id = MBP_MAKE_IDENT(mbp_item_hdr.app_id, (u32)mbp_item_hdr.item_id); - copy_size = mbp_item_hdr.length - 1; #define SET_UP_COPY(field) { copy_addr = (u32 *)&mbp_data->field; \ @@ -294,10 +290,10 @@ break; \ } - p = &mbp_item_hdr; - printk(BIOS_INFO, "ME: MBP item header %8.8x\n", *((u32*)p)); + printk(BIOS_INFO, "ME: MBP item: app id = %u, item id = %u, length = %u\n", + mbp_item_hdr.app_id, mbp_item_hdr.item_id, mbp_item_hdr.length); - switch (mbp_item_id) { + switch (MBP_MAKE_IDENT(mbp_item_hdr.app_id, mbp_item_hdr.item_id)) { case MBP_IDENT(KERNEL, FW_VER): SET_UP_COPY(fw_version_name); @@ -325,17 +321,15 @@ SET_UP_COPY(mfsintegrity); default: - printk(BIOS_ERR, "ME: unknown mbp item id 0x%x! Skipping\n", - mbp_item_id); + printk(BIOS_WARN, "ME: Unknown MBP item! Skipping...\n"); while (copy_size--) read_cb(); continue; } if (buffer_room != copy_size) { - printk(BIOS_ERR, "ME: buffer room %d != %d copy size" - " for item 0x%x!!!\n", - buffer_room, copy_size, mbp_item_id); + printk(BIOS_ERR, "ME: buffer room %d != %d copy size!!!\n", + buffer_room, copy_size); return -1; } while (copy_size--) -- To view, visit https://review.coreboot.org/c/coreboot/+/45263 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I908a6973ab64b1162ec5b835c7c4ffba671d4f05 Gerrit-Change-Number: 45263 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange [View Less]

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Change in coreboot[master]: sb/intel/bd82x6x/me_8.x.c: Improve ME MBP entry decoding
by Angel Pons (Code Review) 05 Feb '21

05 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45262 ) Change subject: sb/intel/bd82x6x/me_8.x.c: Improve ME MBP entry decoding ...................................................................... sb/intel/bd82x6x/me_8.x.c: Improve ME MBP entry decoding Backport the MBP macros from Lynx Point, adjusting the definitions as required. Keep the original math for now, to preserve reproducibility. Note that HWP Request isn't being handled in the … [View More]current code. Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change. Change-Id: I36736bd03ca24ac3b319bf8e3d6eeb82a4104c86 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/me.h M src/southbridge/intel/bd82x6x/me_8.x.c 2 files changed, 38 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/45262/1 diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h index ce1817f0..dc1fa48 100644 --- a/src/southbridge/intel/bd82x6x/me.h +++ b/src/southbridge/intel/bd82x6x/me.h @@ -259,6 +259,35 @@ int intel_me7_send_eop(void); int intel_me8_send_eop(void); +/* + * ME to BIOS Payload definitions + */ +#define MBP_APPID_KERNEL 1 +#define MBP_APPID_ICC 2 +#define MBP_APPID_INTEL_AT 3 +#define MBP_APPID_HWA 4 + +/* Kernel items */ +#define MBP_KERNEL_FW_VER_ITEM 1 +#define MBP_KERNEL_FW_CAP_ITEM 2 +#define MBP_KERNEL_ROM_BIST_ITEM 3 +#define MBP_KERNEL_PLAT_KEY_ITEM 4 +#define MBP_KERNEL_FW_TYPE_ITEM 5 +#define MBP_KERNEL_MFS_FAILURE_ITEM 6 + +/* ICC Items */ +#define MBP_ICC_PROFILE_ITEM 1 + +/* Intel AT items */ +#define MBP_INTEL_AT_STATE_ITEM 1 + +/* HWA Items */ +#define MBP_HWA_REQUEST_ITEM 1 + +#define MBP_MAKE_IDENT(appid, item) (((item) << 8) + (appid)) + +#define MBP_IDENT(appid, item) MBP_MAKE_IDENT(MBP_APPID_##appid, MBP_##appid##_##item##_ITEM) + typedef struct { u32 major_version : 16; u32 minor_version : 16; diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 3613fe4..6d0a82d 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -285,8 +285,7 @@ me2host_pending -= mbp_item_hdr.length; - mbp_item_id = (((u32)mbp_item_hdr.item_id) << 8) + - mbp_item_hdr.app_id; + mbp_item_id = MBP_MAKE_IDENT(mbp_item_hdr.app_id, (u32)mbp_item_hdr.item_id); copy_size = mbp_item_hdr.length - 1; @@ -299,30 +298,30 @@ printk(BIOS_INFO, "ME: MBP item header %8.8x\n", *((u32*)p)); switch (mbp_item_id) { - case 0x101: + case MBP_IDENT(KERNEL, FW_VER): SET_UP_COPY(fw_version_name); - case 0x102: + case MBP_IDENT(ICC, PROFILE): SET_UP_COPY(icc_profile); - case 0x103: + case MBP_IDENT(INTEL_AT, STATE): SET_UP_COPY(at_state); - case 0x201: + case MBP_IDENT(KERNEL, FW_CAP): mbp_data->fw_caps_sku.available = 1; SET_UP_COPY(fw_caps_sku.fw_capabilities); - case 0x301: + case MBP_IDENT(KERNEL, ROM_BIST): SET_UP_COPY(rom_bist_data); - case 0x401: + case MBP_IDENT(KERNEL, PLAT_KEY): SET_UP_COPY(platform_key); - case 0x501: + case MBP_IDENT(KERNEL, FW_TYPE): mbp_data->fw_plat_type.available = 1; SET_UP_COPY(fw_plat_type.rule_data); - case 0x601: + case MBP_IDENT(KERNEL, MFS_FAILURE): SET_UP_COPY(mfsintegrity); default: -- To view, visit https://review.coreboot.org/c/coreboot/+/45262 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36736bd03ca24ac3b319bf8e3d6eeb82a4104c86 Gerrit-Change-Number: 45262 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange [View Less]

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Change in coreboot[master]: sb/intel/bd82x6x: Factor out `mkhi_get_fwcaps`
by Angel Pons (Code Review) 05 Feb '21

05 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45261 ) Change subject: sb/intel/bd82x6x: Factor out `mkhi_get_fwcaps` ...................................................................... sb/intel/bd82x6x: Factor out `mkhi_get_fwcaps` Both versions of this function do the same, but handle the received data differently. Use the version from `me_8.x.c` and adapt `me.c` as needed. Change-Id: I0792341ac0152eba3a8917fa23cad09d9054637d Signed-off-by: … [View More]Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me.h M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/bd82x6x/me_common.c 4 files changed, 30 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/45261/1 diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 56602e6..100ee7e 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -58,32 +58,6 @@ return 0; } -/* Get ME Firmware Capabilities */ -static int __unused mkhi_get_fwcaps(void) -{ - u32 rule_id = 0; - struct me_fwcaps cap; - struct mkhi_header mkhi = { - .group_id = MKHI_GROUP_ID_FWCAPS, - .command = MKHI_FWCAPS_GET_RULE, - }; - struct mei_header mei = { - .is_complete = 1, - .host_address = MEI_HOST_ADDRESS, - .client_address = MEI_ADDRESS_MKHI, - .length = sizeof(mkhi) + sizeof(rule_id), - }; - - /* Send request and wait for response */ - if (mei_sendrecv(&mei, &mkhi, &rule_id, &cap, sizeof(cap)) < 0) { - printk(BIOS_ERR, "ME: GET FWCAPS message failed\n"); - return -1; - } - - intel_me_print_fwcaps(&cap.caps_sku); - return 0; -} - #ifdef __SIMPLE_DEVICE__ /* Send END OF POST message to the ME */ @@ -203,7 +177,9 @@ /* Print ME firmware version */ mkhi_get_fw_version(); /* Print ME firmware capabilities */ - mkhi_get_fwcaps(); + mefwcaps_sku cap; + if (mkhi_get_fwcaps(&cap) != 0) + intel_me_print_fwcaps(&cap); } /* diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h index e7ce1d6..ce1817f0 100644 --- a/src/southbridge/intel/bd82x6x/me.h +++ b/src/southbridge/intel/bd82x6x/me.h @@ -375,6 +375,8 @@ u8 reserved[3]; } __packed; +int mkhi_get_fwcaps(mefwcaps_sku *cap); + void intel_me_print_fwcaps(const mefwcaps_sku *const cap); #endif /* _INTEL_ME_H */ diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 96c9e86..3613fe4 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -40,31 +40,6 @@ } /* Get ME Firmware Capabilities */ -static int mkhi_get_fwcaps(mefwcaps_sku *cap) -{ - u32 rule_id = 0; - struct me_fwcaps cap_msg; - struct mkhi_header mkhi = { - .group_id = MKHI_GROUP_ID_FWCAPS, - .command = MKHI_FWCAPS_GET_RULE, - }; - struct mei_header mei = { - .is_complete = 1, - .host_address = MEI_HOST_ADDRESS, - .client_address = MEI_ADDRESS_MKHI, - .length = sizeof(mkhi) + sizeof(rule_id), - }; - - /* Send request and wait for response */ - if (mei_sendrecv(&mei, &mkhi, &rule_id, &cap_msg, sizeof(cap_msg)) < 0) { - printk(BIOS_ERR, "ME: GET FWCAPS message failed\n"); - return -1; - } - *cap = cap_msg.caps_sku; - return 0; -} - -/* Get ME Firmware Capabilities */ static void __unused me_print_fwcaps(mbp_fw_caps *caps_section) { mefwcaps_sku *cap = &caps_section->fw_capabilities; diff --git a/src/southbridge/intel/bd82x6x/me_common.c b/src/southbridge/intel/bd82x6x/me_common.c index d9cd68a..b0a9fe2 100644 --- a/src/southbridge/intel/bd82x6x/me_common.c +++ b/src/southbridge/intel/bd82x6x/me_common.c @@ -30,6 +30,31 @@ return me_bios_path_values[path]; } +/* Get ME Firmware Capabilities */ +int mkhi_get_fwcaps(mefwcaps_sku *cap) +{ + u32 rule_id = 0; + struct me_fwcaps cap_msg; + struct mkhi_header mkhi = { + .group_id = MKHI_GROUP_ID_FWCAPS, + .command = MKHI_FWCAPS_GET_RULE, + }; + struct mei_header mei = { + .is_complete = 1, + .host_address = MEI_HOST_ADDRESS, + .client_address = MEI_ADDRESS_MKHI, + .length = sizeof(mkhi) + sizeof(rule_id), + }; + + /* Send request and wait for response */ + if (mei_sendrecv(&mei, &mkhi, &rule_id, &cap_msg, sizeof(cap_msg)) < 0) { + printk(BIOS_ERR, "ME: GET FWCAPS message failed\n"); + return -1; + } + *cap = cap_msg.caps_sku; + return 0; +} + static inline void print_cap(const char *name, int state) { printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/45261 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0792341ac0152eba3a8917fa23cad09d9054637d Gerrit-Change-Number: 45261 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange [View Less]

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Change in coreboot[master]: sb/intel/bd82x6x: Factor out handling of ME fwcaps
by Angel Pons (Code Review) 05 Feb '21

05 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42053 ) Change subject: sb/intel/bd82x6x: Factor out handling of ME fwcaps ...................................................................... sb/intel/bd82x6x: Factor out handling of ME fwcaps Although we use different mechanisms to fetch the ME firmware capabilities depending on the PCH, we can still deduplicate most things. Change-Id: Icdabf433ef53709b770373b2b246b6fd0f9d1d02 Signed-off-by: … [View More]Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me.h M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/bd82x6x/me_common.c 4 files changed, 61 insertions(+), 93 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/42053/1 diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 38cdb48..036d10d 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -59,54 +59,15 @@ return 0; } -static inline void print_cap(const char *name, int state) +/* Get and print ME Firmware Capabilities */ +static void me_print_fwcaps(void) { - printk(BIOS_DEBUG, "ME Capability: %-30s : %sabled\n", - name, state ? "en" : "dis"); -} + mefwcaps_sku cap; -/* Get ME Firmware Capabilities */ -static int mkhi_get_fwcaps(void) -{ - u32 rule_id = 0; - struct me_fwcaps cap; - struct mkhi_header mkhi = { - .group_id = MKHI_GROUP_ID_FWCAPS, - .command = MKHI_FWCAPS_GET_RULE, - }; - struct mei_header mei = { - .is_complete = 1, - .host_address = MEI_HOST_ADDRESS, - .client_address = MEI_ADDRESS_MKHI, - .length = sizeof(mkhi) + sizeof(rule_id), - }; + if (mkhi_get_fwcaps(&cap)) + return; - /* Send request and wait for response */ - if (mei_sendrecv(&mei, &mkhi, &rule_id, &cap, sizeof(cap)) < 0) { - printk(BIOS_ERR, "ME: GET FWCAPS message failed\n"); - return -1; - } - - print_cap("Full Network manageability", cap.caps_sku.full_net); - print_cap("Regular Network manageability", cap.caps_sku.std_net); - print_cap("Manageability", cap.caps_sku.manageability); - print_cap("Small business technology", cap.caps_sku.small_business); - print_cap("Level III manageability", cap.caps_sku.l3manageability); - print_cap("IntelR Anti-Theft (AT)", cap.caps_sku.intel_at); - print_cap("IntelR Capability Licensing Service (CLS)", - cap.caps_sku.intel_cls); - print_cap("IntelR Power Sharing Technology (MPC)", - cap.caps_sku.intel_mpc); - print_cap("ICC Over Clocking", cap.caps_sku.icc_over_clocking); - print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp); - print_cap("IPV6", cap.caps_sku.ipv6); - print_cap("KVM Remote Control (KVM)", cap.caps_sku.kvm); - print_cap("Outbreak Containment Heuristic (OCH)", cap.caps_sku.och); - print_cap("Virtual LAN (VLAN)", cap.caps_sku.vlan); - print_cap("TLS", cap.caps_sku.tls); - print_cap("Wireless LAN (WLAN)", cap.caps_sku.wlan); - - return 0; + me_display_fwcaps(&cap); } /* Determine the path that we should take based on ME status */ @@ -200,7 +161,7 @@ /* Print ME firmware version */ mkhi_get_fw_version(); /* Print ME firmware capabilities */ - mkhi_get_fwcaps(); + me_print_fwcaps(); } /* diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h index 29d5749..9ae8030 100644 --- a/src/southbridge/intel/bd82x6x/me.h +++ b/src/southbridge/intel/bd82x6x/me.h @@ -372,4 +372,7 @@ u8 reserved[3]; } __packed; +void me_display_fwcaps(const mefwcaps_sku *const cap); +int mkhi_get_fwcaps(mefwcaps_sku *const cap); + #endif /* _INTEL_ME_H */ diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 5659f7a..7eceb7c 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -28,12 +28,6 @@ #include <vendorcode/google/chromeos/gnvs.h> #endif -static inline void print_cap(const char *name, int state) -{ - printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n", - name, state ? " en" : "dis"); -} - static void me_print_fw_version(mbp_fw_version_name *vers_name) { if (!vers_name->major_version) { @@ -47,31 +41,6 @@ } /* Get ME Firmware Capabilities */ -static int mkhi_get_fwcaps(mefwcaps_sku *cap) -{ - u32 rule_id = 0; - struct me_fwcaps cap_msg; - struct mkhi_header mkhi = { - .group_id = MKHI_GROUP_ID_FWCAPS, - .command = MKHI_FWCAPS_GET_RULE, - }; - struct mei_header mei = { - .is_complete = 1, - .host_address = MEI_HOST_ADDRESS, - .client_address = MEI_ADDRESS_MKHI, - .length = sizeof(mkhi) + sizeof(rule_id), - }; - - /* Send request and wait for response */ - if (mei_sendrecv(&mei, &mkhi, &rule_id, &cap_msg, sizeof(cap_msg)) < 0) { - printk(BIOS_ERR, "ME: GET FWCAPS message failed\n"); - return -1; - } - *cap = cap_msg.caps_sku; - return 0; -} - -/* Get ME Firmware Capabilities */ static void me_print_fwcaps(mbp_fw_caps *caps_section) { mefwcaps_sku *cap = &caps_section->fw_capabilities; @@ -81,22 +50,7 @@ return; } - print_cap("Full Network manageability", cap->full_net); - print_cap("Regular Network manageability", cap->std_net); - print_cap("Manageability", cap->manageability); - print_cap("Small business technology", cap->small_business); - print_cap("Level III manageability", cap->l3manageability); - print_cap("IntelR Anti-Theft (AT)", cap->intel_at); - print_cap("IntelR Capability Licensing Service (CLS)", cap->intel_cls); - print_cap("IntelR Power Sharing Technology (MPC)", cap->intel_mpc); - print_cap("ICC Over Clocking", cap->icc_over_clocking); - print_cap("Protected Audio Video Path (PAVP)", cap->pavp); - print_cap("IPV6", cap->ipv6); - print_cap("KVM Remote Control (KVM)", cap->kvm); - print_cap("Outbreak Containment Heuristic (OCH)", cap->och); - print_cap("Virtual LAN (VLAN)", cap->vlan); - print_cap("TLS", cap->tls); - print_cap("Wireless LAN (WLAN)", cap->wlan); + me_display_fwcaps(cap); } /* Determine the path that we should take based on ME status */ diff --git a/src/southbridge/intel/bd82x6x/me_common.c b/src/southbridge/intel/bd82x6x/me_common.c index 59c0b38..b6f97b4 100644 --- a/src/southbridge/intel/bd82x6x/me_common.c +++ b/src/southbridge/intel/bd82x6x/me_common.c @@ -30,6 +30,56 @@ return me_bios_path_values[path]; } +static inline void print_cap(const char *const name, const bool state) +{ + printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n", name, state ? " en" : "dis"); +} + +void me_display_fwcaps(const mefwcaps_sku *const cap) +{ + print_cap("Full Network manageability", cap->full_net); + print_cap("Regular Network manageability", cap->std_net); + print_cap("Manageability", cap->manageability); + print_cap("Small business technology", cap->small_business); + print_cap("Level III manageability", cap->l3manageability); + print_cap("IntelR Anti-Theft (AT)", cap->intel_at); + print_cap("IntelR Capability Licensing Service (CLS)", cap->intel_cls); + print_cap("IntelR Power Sharing Technology (MPC)", cap->intel_mpc); + print_cap("ICC Over Clocking", cap->icc_over_clocking); + print_cap("Protected Audio Video Path (PAVP)", cap->pavp); + print_cap("IPV6", cap->ipv6); + print_cap("KVM Remote Control (KVM)", cap->kvm); + print_cap("Outbreak Containment Heuristic (OCH)", cap->och); + print_cap("Virtual LAN (VLAN)", cap->vlan); + print_cap("TLS", cap->tls); + print_cap("Wireless LAN (WLAN)", cap->wlan); +} + +/* Get ME Firmware Capabilities */ +int mkhi_get_fwcaps(mefwcaps_sku *const cap) +{ + u32 rule_id = 0; + struct me_fwcaps cap_msg; + struct mkhi_header mkhi = { + .group_id = MKHI_GROUP_ID_FWCAPS, + .command = MKHI_FWCAPS_GET_RULE, + }; + struct mei_header mei = { + .is_complete = 1, + .host_address = MEI_HOST_ADDRESS, + .client_address = MEI_ADDRESS_MKHI, + .length = sizeof(mkhi) + sizeof(rule_id), + }; + + /* Send request and wait for response */ + if (mei_sendrecv(&mei, &mkhi, &rule_id, &cap_msg, sizeof(cap_msg)) < 0) { + printk(BIOS_ERR, "ME: GET FWCAPS message failed\n"); + return -1; + } + *cap = cap_msg.caps_sku; + return 0; +} + /* MMIO base address for MEI interface */ static u32 *mei_base_address; -- To view, visit https://review.coreboot.org/c/coreboot/+/42053 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdabf433ef53709b770373b2b246b6fd0f9d1d02 Gerrit-Change-Number: 42053 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange [View Less]

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Change in coreboot[master]: sb/intel/bd82x6x: Relocate `intel_me_finalize_smm` function
by Angel Pons (Code Review) 05 Feb '21

05 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45260 ) Change subject: sb/intel/bd82x6x: Relocate `intel_me_finalize_smm` function ...................................................................... sb/intel/bd82x6x: Relocate `intel_me_finalize_smm` function This allows us to hide two small functions, which have been inlined. Change-Id: Ifc787c903380f748812f1ae5bf627613fb5c3987 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/… [View More]southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me.h M src/southbridge/intel/bd82x6x/me_common.c 3 files changed, 46 insertions(+), 47 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/45260/1 diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 854698b..af411cc 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -111,7 +111,7 @@ #ifdef __SIMPLE_DEVICE__ /* Send END OF POST message to the ME */ -static int intel_me7_send_eop(void) +int intel_me7_send_eop(void) { struct mkhi_header mkhi = { .group_id = MKHI_GROUP_ID_GEN, @@ -134,48 +134,6 @@ return 0; } -void intel_me_finalize_smm(void) -{ - struct me_hfs hfs; - u32 reg32; - - update_mei_base_address(); - - /* S3 path will have hidden this device already */ - if (!is_mei_base_address_valid()) - return; - - /* Make sure ME is in a mode that expects EOP */ - reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS); - memcpy(&hfs, &reg32, sizeof(u32)); - - /* Abort and leave device alone if not normal mode */ - if (hfs.fpt_bad || - hfs.working_state != ME_HFS_CWS_NORMAL || - hfs.operation_mode != ME_HFS_MODE_NORMAL) - return; - - /* Try to send EOP command so ME stops accepting other commands */ - const u16 did = pci_read_config16(PCH_ME_DEV, PCI_DEVICE_ID); - switch (did) { - case 0x1c3a: - intel_me7_send_eop(); - break; - case 0x1e3a: - intel_me8_send_eop(); - break; - default: - printk(BIOS_ERR, "No EOP handler for ME %04x.\n", did); - } - - /* Make sure IO is disabled */ - pci_and_config16(PCH_ME_DEV, PCI_COMMAND, - ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); - - /* Hide the PCI device */ - RCBA32_OR(FD2, PCH_DISABLE_MEI1); -} - #else /* Determine the path that we should take based on ME status */ diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h index 8dd34bc..dca1d3e 100644 --- a/src/southbridge/intel/bd82x6x/me.h +++ b/src/southbridge/intel/bd82x6x/me.h @@ -242,8 +242,6 @@ int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, void *req_data, void *rsp_data, int rsp_bytes); -void update_mei_base_address(void); -bool is_mei_base_address_valid(void); int intel_mei_setup(struct device *dev); int intel_me_extend_valid(struct device *dev); void intel_me_hide(struct device *dev); @@ -258,6 +256,7 @@ void intel_me_finalize_smm(void); +int intel_me7_send_eop(void); int intel_me8_send_eop(void); typedef struct { diff --git a/src/southbridge/intel/bd82x6x/me_common.c b/src/southbridge/intel/bd82x6x/me_common.c index 1ce61a1..94e5c9a 100644 --- a/src/southbridge/intel/bd82x6x/me_common.c +++ b/src/southbridge/intel/bd82x6x/me_common.c @@ -322,16 +322,58 @@ #ifdef __SIMPLE_DEVICE__ -void update_mei_base_address(void) +static inline void update_mei_base_address(void) { mei_base_address = (u32 *)(pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); } -bool is_mei_base_address_valid(void) +static inline bool is_mei_base_address_valid(void) { return mei_base_address && mei_base_address != (u32 *)0xfffffff0; } +void intel_me_finalize_smm(void) +{ + struct me_hfs hfs; + u32 reg32; + + update_mei_base_address(); + + /* S3 path will have hidden this device already */ + if (!is_mei_base_address_valid()) + return; + + /* Make sure ME is in a mode that expects EOP */ + reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS); + memcpy(&hfs, &reg32, sizeof(u32)); + + /* Abort and leave device alone if not normal mode */ + if (hfs.fpt_bad || + hfs.working_state != ME_HFS_CWS_NORMAL || + hfs.operation_mode != ME_HFS_MODE_NORMAL) + return; + + /* Try to send EOP command so ME stops accepting other commands */ + const u16 did = pci_read_config16(PCH_ME_DEV, PCI_DEVICE_ID); + switch (did) { + case 0x1c3a: + intel_me7_send_eop(); + break; + case 0x1e3a: + intel_me8_send_eop(); + break; + default: + printk(BIOS_ERR, "No EOP handler for ME %04x.\n", did); + } + + /* Make sure IO is disabled */ + pci_and_config16(PCH_ME_DEV, PCI_COMMAND, + ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); + + /* Hide the PCI device */ + RCBA32_OR(FD2, PCH_DISABLE_MEI1); +} + #else /* Prepare ME for MEI messages */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45260 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc787c903380f748812f1ae5bf627613fb5c3987 Gerrit-Change-Number: 45260 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange [View Less]

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Change in coreboot[master]: sb/intel/bd82x6x: Factor out ME finalization function
by Angel Pons (Code Review) 05 Feb '21

05 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45259 ) Change subject: sb/intel/bd82x6x: Factor out ME finalization function ...................................................................... sb/intel/bd82x6x: Factor out ME finalization function The only difference between ME7 and ME8 is that the latter returns an acknowledgment value, which we should read out. The rest is the same. Change-Id: Icf9004467c3cca4185b45ccd92822f1574ef1efb Signed-… [View More]off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me.h M src/southbridge/intel/bd82x6x/me_8.x.c 3 files changed, 59 insertions(+), 95 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/45259/1 diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 3876b02..854698b 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -27,30 +27,6 @@ #include <vendorcode/google/chromeos/gnvs.h> #endif -/* Send END OF POST message to the ME */ -static int __unused mkhi_end_of_post(void) -{ - struct mkhi_header mkhi = { - .group_id = MKHI_GROUP_ID_GEN, - .command = MKHI_END_OF_POST, - }; - struct mei_header mei = { - .is_complete = 1, - .host_address = MEI_HOST_ADDRESS, - .client_address = MEI_ADDRESS_MKHI, - .length = sizeof(mkhi), - }; - - /* Send request and wait for response */ - if (mei_sendrecv(&mei, &mkhi, NULL, NULL, 0) < 0) { - printk(BIOS_ERR, "ME: END OF POST message failed\n"); - return -1; - } - - printk(BIOS_INFO, "ME: END OF POST message successful\n"); - return 0; -} - /* Get ME firmware version */ static int __unused mkhi_get_fw_version(void) { @@ -134,7 +110,31 @@ #ifdef __SIMPLE_DEVICE__ -static void intel_me7_finalize_smm(void) +/* Send END OF POST message to the ME */ +static int intel_me7_send_eop(void) +{ + struct mkhi_header mkhi = { + .group_id = MKHI_GROUP_ID_GEN, + .command = MKHI_END_OF_POST, + }; + struct mei_header mei = { + .is_complete = 1, + .host_address = MEI_HOST_ADDRESS, + .client_address = MEI_ADDRESS_MKHI, + .length = sizeof(mkhi), + }; + + /* Send request and wait for response */ + if (mei_sendrecv(&mei, &mkhi, NULL, NULL, 0) < 0) { + printk(BIOS_ERR, "ME: END OF POST message failed\n"); + return -1; + } + + printk(BIOS_INFO, "ME: END OF POST message successful\n"); + return 0; +} + +void intel_me_finalize_smm(void) { struct me_hfs hfs; u32 reg32; @@ -156,7 +156,17 @@ return; /* Try to send EOP command so ME stops accepting other commands */ - mkhi_end_of_post(); + const u16 did = pci_read_config16(PCH_ME_DEV, PCI_DEVICE_ID); + switch (did) { + case 0x1c3a: + intel_me7_send_eop(); + break; + case 0x1e3a: + intel_me8_send_eop(); + break; + default: + printk(BIOS_ERR, "No EOP handler for ME %04x.\n", did); + } /* Make sure IO is disabled */ pci_and_config16(PCH_ME_DEV, PCI_COMMAND, @@ -166,21 +176,6 @@ RCBA32_OR(FD2, PCH_DISABLE_MEI1); } -void intel_me_finalize_smm(void) -{ - u16 did = pci_read_config16(PCH_ME_DEV, PCI_DEVICE_ID); - switch (did) { - case 0x1c3a: - intel_me7_finalize_smm(); - break; - case 0x1e3a: - intel_me8_finalize_smm(); - break; - default: - printk(BIOS_ERR, "No finalize handler for ME %04x.\n", did); - } -} - #else /* Determine the path that we should take based on ME status */ diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h index f6cd96b..8dd34bc 100644 --- a/src/southbridge/intel/bd82x6x/me.h +++ b/src/southbridge/intel/bd82x6x/me.h @@ -257,7 +257,8 @@ int intel_early_me_init_done(u8 status); void intel_me_finalize_smm(void); -void intel_me8_finalize_smm(void); + +int intel_me8_send_eop(void); typedef struct { u32 major_version : 16; diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index d47c1da..fa51fd7 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -27,33 +27,6 @@ #include <vendorcode/google/chromeos/gnvs.h> #endif -/* Send END OF POST message to the ME */ -static int __unused mkhi_end_of_post(void) -{ - struct mkhi_header mkhi = { - .group_id = MKHI_GROUP_ID_GEN, - .command = MKHI_END_OF_POST, - }; - struct mei_header mei = { - .is_complete = 1, - .host_address = MEI_HOST_ADDRESS, - .client_address = MEI_ADDRESS_MKHI, - .length = sizeof(mkhi), - }; - - u32 eop_ack; - - /* Send request and wait for response */ - printk(BIOS_NOTICE, "ME: %s\n", __func__); - if (mei_sendrecv(&mei, &mkhi, NULL, &eop_ack, sizeof(eop_ack)) < 0) { - printk(BIOS_ERR, "ME: END OF POST message failed\n"); - return -1; - } - - printk(BIOS_INFO, "ME: END OF POST message successful (%d)\n", eop_ack); - return 0; -} - static inline void print_cap(const char *name, int state) { printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n", @@ -127,36 +100,31 @@ #ifdef __SIMPLE_DEVICE__ -void intel_me8_finalize_smm(void) +/* Send END OF POST message to the ME */ +int intel_me8_send_eop(void) { - struct me_hfs hfs; - u32 reg32; + struct mkhi_header mkhi = { + .group_id = MKHI_GROUP_ID_GEN, + .command = MKHI_END_OF_POST, + }; + struct mei_header mei = { + .is_complete = 1, + .host_address = MEI_HOST_ADDRESS, + .client_address = MEI_ADDRESS_MKHI, + .length = sizeof(mkhi), + }; - update_mei_base_address(); + u32 eop_ack; - /* S3 path will have hidden this device already */ - if (!is_mei_base_address_valid()) - return; + /* Send request and wait for response */ + printk(BIOS_NOTICE, "ME: %s\n", __func__); + if (mei_sendrecv(&mei, &mkhi, NULL, &eop_ack, sizeof(eop_ack)) < 0) { + printk(BIOS_ERR, "ME: END OF POST message failed\n"); + return -1; + } - /* Make sure ME is in a mode that expects EOP */ - reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS); - memcpy(&hfs, &reg32, sizeof(u32)); - - /* Abort and leave device alone if not normal mode */ - if (hfs.fpt_bad || - hfs.working_state != ME_HFS_CWS_NORMAL || - hfs.operation_mode != ME_HFS_MODE_NORMAL) - return; - - /* Try to send EOP command so ME stops accepting other commands */ - mkhi_end_of_post(); - - /* Make sure IO is disabled */ - pci_and_config16(PCH_ME_DEV, PCI_COMMAND, - ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); - - /* Hide the PCI device */ - RCBA32_OR(FD2, PCH_DISABLE_MEI1); + printk(BIOS_INFO, "ME: END OF POST message successful (%d)\n", eop_ack); + return 0; } #else /* !__SIMPLE_DEVICE__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf9004467c3cca4185b45ccd92822f1574ef1efb Gerrit-Change-Number: 45259 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange [View Less]

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Change in coreboot[master]: mb/emulation/qemu-q35: Mark TSEG region as reserved
by Angel Pons (Code Review) 05 Feb '21

05 Feb '21

Attention is currently required from: Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50267 ) Change subject: mb/emulation/qemu-q35: Mark TSEG region as reserved ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50267 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-… [View More]

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Change in coreboot[master]: mb/emulation/qemu-q35: Mark TSEG region as reserved
by Patrick Rudolph (Code Review) 05 Feb '21

05 Feb '21

Attention is currently required from: Patrick Rudolph. Hello build bot (Jenkins), Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50267 to look at the new patch set (#3). Change subject: mb/emulation/qemu-q35: Mark TSEG region as reserved ...................................................................... mb/emulation/qemu-q35: Mark TSEG region as reserved Mark TSEG as reserved, which is done on other platforms as well. For … [View More]

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coreboot-gerrit February 2021