coreboot-gerrit February 2021

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Change in coreboot[master]: device: correct code style
by Felix Held (Code Review) 05 Feb '21

05 Feb '21

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49963 ) Change subject: device: correct code style ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: i find keeping the else block even though the if blocks before that return much clearer, since it makes the control flow more obvious. i also think that even though the curly brackets aren't required if there's only one statement after an if condition it's not great to remove those. i'll put the curly brackets for single statement if blocks on the agenda for the next coreboot meeting -- To view, visit https://review.coreboot.org/c/coreboot/+/49963 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I780251d946d5bea97658476d61d25555ec768dfc Gerrit-Change-Number: 49963 Gerrit-PatchSet: 4 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 05 Feb 2021 14:58:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/mancomb: Add new mainboard
by Felix Held (Code Review) 05 Feb '21

05 Feb '21

Attention is currently required from: Furquan Shaikh, Martin Roth, Mathew King. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50007 ) Change subject: mb/google/mancomb: Add new mainboard ...................................................................... Patch Set 7: (1 comment) File src/mainboard/google/mancomb/Kconfig: https://review.coreboot.org/c/coreboot/+/50007/comment/f0d2aaa9_044e5ab1 PS7, Line 11: select BOARD_ROMSIZE_KB_16384 is missing here -- To view, visit https://review.coreboot.org/c/coreboot/+/50007 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1264f44a0b986f7f7c89ac7b42f1e4e4119a35e6 Gerrit-Change-Number: 50007 Gerrit-PatchSet: 7 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Mathew King <mathewk(a)chromium.org> Gerrit-Comment-Date: Fri, 05 Feb 2021 14:19:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: tests: Add lib/stack-test test case
by Name of user not set (Code Review) 05 Feb '21

05 Feb '21

jacz(a)semihalf.com has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50305 ) Change subject: tests: Add lib/stack-test test case ...................................................................... tests: Add lib/stack-test test case Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: Icf0cceac290618a50ecc4e65f1f9551dbf31bd32 --- M tests/lib/Makefile.inc A tests/lib/stack-test.c 2 files changed, 137 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/50305/1 diff --git a/tests/lib/Makefile.inc b/tests/lib/Makefile.inc index ccc6596..2c80b93 100644 --- a/tests/lib/Makefile.inc +++ b/tests/lib/Makefile.inc @@ -13,6 +13,7 @@ tests-y += imd_cbmem-romstage-test tests-y += imd_cbmem-ramstage-test tests-y += region_file-test +tests-y += stack-test string-test-srcs += tests/lib/string-test.c string-test-srcs += src/lib/string.c @@ -71,3 +72,7 @@ region_file-test-srcs += tests/lib/region_file-test.c region_file-test-srcs += src/commonlib/region.c region_file-test-srcs += tests/stubs/console.c + +stack-test-srcs += tests/lib/stack-test.c +stack-test-srcs += src/lib/stack.c +stack-test-srcs += tests/stubs/console.c diff --git a/tests/lib/stack-test.c b/tests/lib/stack-test.c new file mode 100644 index 0000000..9dde157 --- /dev/null +++ b/tests/lib/stack-test.c @@ -0,0 +1,132 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <tests/test.h> +#include <lib.h> +#include <symbols.h> + + +#if CONFIG_STACK_SIZE == 0 +# define STACK_SIZE 0x1000 +#else +# define STACK_SIZE CONFIG_STACK_SIZE +#endif + +/* Value used for stack initialization. Change if implementation changes. */ +#define STACK_GUARD_VALUE 0xDEADBEEF + +__weak extern u8 _stack[]; +__weak extern u8 _estack[]; +TEST_REGION(stack, STACK_SIZE); + + +static void fill_stack(u32 value) +{ + u32 *stack = (u32 *)_stack; + for (size_t i = 0; i < STACK_SIZE / sizeof(u32); ++i) + stack[i] = value; +} + +/* Fill stack region with guard value. */ +static void clean_stack(void) +{ + fill_stack(STACK_GUARD_VALUE); +} + +static int setup_stack_test(void **state) +{ + void *top_of_stack = _stack + sizeof(_stack); + + clean_stack(); + *state = top_of_stack; + + return 0; +} + +static void test_empty_stack(void **state) +{ + void *top_of_stack = *state; + + /* Expect succes when checking empty stack. */ + assert_int_equal(0, checkstack(top_of_stack, 0)); +} + +static void test_almost_full_stack(void **state) +{ + void *top_of_stack = *state; + u32 *stack = (u32 *)_stack; + + /* Fill stack with random value except last word */ + for (size_t i = 1; i < STACK_SIZE / sizeof(u32); ++i) + stack[i] = 0xAA11FF44; + + /* Expect success when checking almost stack, because last guard value is present */ + assert_int_equal(0, checkstack(top_of_stack, 0)); +} + +static void test_full_stack(void **state) +{ + void *top_of_stack = *state; + + /* Fill stack with value different than stack guard */ + fill_stack(0x600DB015); + + /* Expect failure when checking full stack as absence of guard value at the end of + the stack indicates stack overrun. */ + assert_int_equal(-1, checkstack(top_of_stack, 0)); +} + +static void test_partialy_filled_stack(void **state) +{ + void *top_of_stack = *state; + u32 *stack = (u32 *)_stack; + size_t i = STACK_SIZE / sizeof(u32) / 2; + + for (; i < STACK_SIZE / sizeof(u32); ++i) + stack[i] = 0x4321ABDC + i; + + /* Expect success when checking almost stack, because only part of stack is filled with + non-guard value. */ + assert_int_equal(0, checkstack(top_of_stack, 0)); +} + +static void test_alternately_filled_stack(void **state) +{ + void *top_of_stack = *state; + u32 *stack = (u32 *)_stack; + size_t i; + + for (i = 0; i < STACK_SIZE / sizeof(u32); i += 2) + stack[i] = STACK_GUARD_VALUE; + + for (i = 1; i < STACK_SIZE / sizeof(u32); i += 2) + stack[i] = 0x42420707; + + assert_int_equal(0, checkstack(top_of_stack, 0)); +} + +static void test_incorrectly_initialized_stack(void **state) +{ + void *top_of_stack = *state; + u32 *stack = (u32 *)_stack; + + /* Remove last stack guard value */ + stack[0] = 0xFF00FF11; + + /* Expect failure when there is no last stack guard value even if no other value was + changed. */ + assert_int_equal(-1, checkstack(top_of_stack, 0)); +} + +int main(void) +{ + const struct CMUnitTest tests[] = { + cmocka_unit_test_setup(test_empty_stack, setup_stack_test), + cmocka_unit_test_setup(test_almost_full_stack, setup_stack_test), + cmocka_unit_test_setup(test_full_stack, setup_stack_test), + cmocka_unit_test_setup(test_partialy_filled_stack, setup_stack_test), + cmocka_unit_test_setup(test_alternately_filled_stack, setup_stack_test), + cmocka_unit_test_setup(test_incorrectly_initialized_stack, setup_stack_test), + }; + + return cmocka_run_group_tests(tests, NULL, NULL); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/50305 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf0cceac290618a50ecc4e65f1f9551dbf31bd32 Gerrit-Change-Number: 50305 Gerrit-PatchSet: 1 Gerrit-Owner: jacz(a)semihalf.com Gerrit-MessageType: newchange

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Change in coreboot[master]: util/lint: Add test for documentation in util dirs
by Martin Roth (Code Review) 05 Feb '21

05 Feb '21

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48967 ) Change subject: util/lint: Add test for documentation in util dirs ...................................................................... util/lint: Add test for documentation in util dirs Make sure that any new directories added to the util directory get documentation added. Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I8bb415c72cf05b91c84f0a945d7767134a74c44c --- A util/lint/lint-stable-025-description-md 1 file changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/48967/1 diff --git a/util/lint/lint-stable-025-description-md b/util/lint/lint-stable-025-description-md new file mode 100755 index 0000000..88c3d76 --- /dev/null +++ b/util/lint/lint-stable-025-description-md @@ -0,0 +1,16 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0-or-later +# +# DESCR: Check that every utility has a description + +LC_ALL=C export LC_ALL +FAIL=0 + +for i in util/*/; do + if [ ! -r "$i/description.md" ]; then + echo " Failure: util directory $i missing description.md file." + FAIL=1 + fi +done + +exit $FAIL -- To view, visit https://review.coreboot.org/c/coreboot/+/48967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8bb415c72cf05b91c84f0a945d7767134a74c44c Gerrit-Change-Number: 48967 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/fsp2_0: Add support for MP services2 PPI
by Aamir Bohra (Code Review) 05 Feb '21

05 Feb '21

Attention is currently required from: Furquan Shaikh, Martin Roth, Tim Wawrzynczak, Meera Ravindranath, Andrey Petrov, Patrick Rudolph. Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49474 ) Change subject: drivers/intel/fsp2_0: Add support for MP services2 PPI ...................................................................... Patch Set 11: (1 comment) File src/drivers/intel/fsp2_0/include/fsp/ppi/mp_service_ppi.h: https://review.coreboot.org/c/coreboot/+/49474/comment/bff42314_2132daf8 PS10, Line 38: efi_return_status_t mp_api_unsupported(void); > nit: This can be an inline function too here in . […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/49474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id74baf17fb90147d229c78be90268fdc3ec1badc Gerrit-Change-Number: 49474 Gerrit-PatchSet: 11 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 05 Feb 2021 13:35:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0: Add support for MP services2 PPI
by Aamir Bohra (Code Review) 05 Feb '21

05 Feb '21

Attention is currently required from: Martin Roth, Tim Wawrzynczak, Meera Ravindranath, Aamir Bohra, Andrey Petrov, Patrick Rudolph. Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Subrata Banik, Meera Ravindranath, Tim Wawrzynczak, Andrey Petrov, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49474 to look at the new patch set (#11). Change subject: drivers/intel/fsp2_0: Add support for MP services2 PPI ...................................................................... drivers/intel/fsp2_0: Add support for MP services2 PPI Add support for MP services2 PPIs, which is slight modification over MP services 1 PPIs. A new API StartupAllCPUs have been added to allow running a task on BSP and all APs. Also the EFI_PEI_SERVICES parameter has been removed from all MP PPI APIs. This implementation also selects the respective MP services PPI version supported for SoCs BUG=b:169196864 Change-Id: Id74baf17fb90147d229c78be90268fdc3ec1badc Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/include/fsp/ppi/mp_service_ppi.h M src/drivers/intel/fsp2_0/ppi/Kconfig M src/drivers/intel/fsp2_0/ppi/Makefile.inc A src/drivers/intel/fsp2_0/ppi/mp_service1.c A src/drivers/intel/fsp2_0/ppi/mp_service2.c M src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c M src/include/efi/efi_datatype.h M src/soc/intel/alderlake/Kconfig M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/tigerlake/Kconfig A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/MpServices2.h 14 files changed, 527 insertions(+), 89 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/49474/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/49474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id74baf17fb90147d229c78be90268fdc3ec1badc Gerrit-Change-Number: 49474 Gerrit-PatchSet: 11 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: arch/x86/cpu.c: Remove redundant <arch/cpu.h>
by HAOUAS Elyes (Code Review) 05 Feb '21

05 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50304 ) Change subject: arch/x86/cpu.c: Remove redundant <arch/cpu.h> ...................................................................... arch/x86/cpu.c: Remove redundant <arch/cpu.h> Change-Id: Iad7f23080814c6606603d9472a1bd34a6b1bd1a9 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/cpu.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/50304/1 diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index d054cfe..3230e41 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -9,7 +9,6 @@ #include <cpu/x86/mp.h> #include <cpu/x86/lapic.h> #include <cpu/x86/tsc.h> -#include <arch/cpu.h> #include <device/path.h> #include <device/device.h> #include <smp/spinlock.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/50304 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad7f23080814c6606603d9472a1bd34a6b1bd1a9 Gerrit-Change-Number: 50304 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell/include/soc/me.h: Clean includes
by HAOUAS Elyes (Code Review) 05 Feb '21

05 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50303 ) Change subject: soc/intel/broadwell/include/soc/me.h: Clean includes ...................................................................... soc/intel/broadwell/include/soc/me.h: Clean includes Change-Id: I740b0f3341ecc49382f44e8ccabc07148c5cad79 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/broadwell/include/soc/me.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/50303/1 diff --git a/src/soc/intel/broadwell/include/soc/me.h b/src/soc/intel/broadwell/include/soc/me.h index 5282441..b0c50a2 100644 --- a/src/soc/intel/broadwell/include/soc/me.h +++ b/src/soc/intel/broadwell/include/soc/me.h @@ -3,7 +3,7 @@ #ifndef _BROADWELL_ME_H_ #define _BROADWELL_ME_H_ -#include <commonlib/loglevel.h> +#include <stdint.h> #define ME_RETRY 100000 /* 1 second */ #define ME_DELAY 10 /* 10 us */ -- To view, visit https://review.coreboot.org/c/coreboot/+/50303 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I740b0f3341ecc49382f44e8ccabc07148c5cad79 Gerrit-Change-Number: 50303 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/quark/storage_test.c: Remove redundant <commonlib/cbmem_id.h>
by HAOUAS Elyes (Code Review) 05 Feb '21

05 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50302 ) Change subject: soc/intel/quark/storage_test.c: Remove redundant <commonlib/cbmem_id.h> ...................................................................... soc/intel/quark/storage_test.c: Remove redundant <commonlib/cbmem_id.h> <commonlib/cbmem_id.h> is already included through <cbmem.h>. Change-Id: I0fb22114621a52359dd876fa70d881a1379d4cc2 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/quark/storage_test.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/50302/1 diff --git a/src/soc/intel/quark/storage_test.c b/src/soc/intel/quark/storage_test.c index 9c8a549..1eed84e 100644 --- a/src/soc/intel/quark/storage_test.c +++ b/src/soc/intel/quark/storage_test.c @@ -3,7 +3,6 @@ #include <device/pci_ops.h> #include <assert.h> #include <cbmem.h> -#include <commonlib/cbmem_id.h> #include <commonlib/sdhci.h> #include <commonlib/storage.h> #include <console/console.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/50302 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fb22114621a52359dd876fa70d881a1379d4cc2 Gerrit-Change-Number: 50302 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/shadowmountain: Add the ramstage code
by Aamir Bohra (Code Review) 05 Feb '21

05 Feb '21

Attention is currently required from: V Sowmya, Martin Roth, Tim Wawrzynczak, Subrata Banik, Balaji Manigandan. Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49732 ) Change subject: mb/intel/shadowmountain: Add the ramstage code ...................................................................... Patch Set 3: (1 comment) File src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/49732/comment/935fd2f2_5dc298fe PS3, Line 41: # Enable PCH PCIE RP 5 using CLK 1 : register "PchPcieRpEnable[4]" = "1" : register "PcieClkSrcClkReq[1]" = "1" : register "PcieClkSrcUsage[1]" = "0x4" : register "PcieRpClkReqDetect[4]" = i think this would need a rebase as per https://review.coreboot.org/c/coreboot/+/48340 -- To view, visit https://review.coreboot.org/c/coreboot/+/49732 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I419eecefddf9ee6e4249ada041ebeb1b78e85eb7 Gerrit-Change-Number: 49732 Gerrit-PatchSet: 3 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Comment-Date: Fri, 05 Feb 2021 11:50:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit February 2021