coreboot-gerrit February 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/intel/shadowmountain: Add the ramstage code
by Aamir Bohra (Code Review) 05 Feb '21

05 Feb '21

Attention is currently required from: V Sowmya, Martin Roth, Tim Wawrzynczak, Subrata Banik, Balaji Manigandan. Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49732 ) Change subject: mb/intel/shadowmountain: Add the ramstage code ...................................................................... Patch Set 3: (1 comment) File src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/49732/comment/935fd2f2_5dc298fe PS3, Line 41: # Enable PCH PCIE RP 5 using CLK 1 : register "PchPcieRpEnable[4]" = "1" : register "PcieClkSrcClkReq[1]" = "1" : register "PcieClkSrcUsage[1]" = "0x4" : register "PcieRpClkReqDetect[4]" = i think this would need a rebase as per https://review.coreboot.org/c/coreboot/+/48340 -- To view, visit https://review.coreboot.org/c/coreboot/+/49732 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I419eecefddf9ee6e4249ada041ebeb1b78e85eb7 Gerrit-Change-Number: 49732 Gerrit-PatchSet: 3 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Comment-Date: Fri, 05 Feb 2021 11:50:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: acpi: Fix BERT size_t printf format error
by HAOUAS Elyes (Code Review) 05 Feb '21

05 Feb '21

Attention is currently required from: Francois Toguo Fotso, Benjamin Doron, Patrick Rudolph. HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50051 ) Change subject: acpi: Fix BERT size_t printf format error ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50051 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb1db6c0c3eb4947bd3617e418bac238b70ec08f Gerrit-Change-Number: 50051 Gerrit-PatchSet: 2 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 05 Feb 2021 10:51:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/ocp/deltalake: Implement skipping TXT lockdown via VPD
by Johnny Lin (Code Review) 05 Feb '21

05 Feb '21

Attention is currently required from: Anjaneya "Reddy" Chagam, Patrick Rudolph, Jonathan Zhang, Rocky Phagura, Arthur Heymans, Morgan Jang. Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50237 ) Change subject: mb/ocp/deltalake: Implement skipping TXT lockdown via VPD ...................................................................... Patch Set 1: (1 comment) File src/mainboard/ocp/deltalake/ramstage.c: https://review.coreboot.org/c/coreboot/+/50237/comment/a4d7e77e_4c0e6d78 PS1, Line 375: printk(BIOS_INFO, "Not able to get VPD %s, default set to %d\n", Can it also print out the vpd value when vpd_get_bool returns true? For cases like if it's set to 0 or 1 it can still be printed. Thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/50237 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5daf96bdda9c36054c410b07b08bcd3482d777c Gerrit-Change-Number: 50237 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Rocky Phagura <rphagura(a)fb.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Comment-Date: Fri, 05 Feb 2021 10:26:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8192: Use LZ4 compression for MCUs
by Patrick Georgi (Code Review) 05 Feb '21

05 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50278 ) Change subject: soc/mediatek/mt8192: Use LZ4 compression for MCUs ...................................................................... soc/mediatek/mt8192: Use LZ4 compression for MCUs For MT8192 MCUs, replace LZMA compression with LZ4 to speed up boot process. The loading (plus decompression) time of mcupm.bin and sspm.bin is consistently reduced by 8ms, respectively. BUG=b:177389446 TEST=emerge-asurada coreboot TEST=Hayato booted up BRANCH=none Change-Id: Ida35e7f6e0572ad43082e53bcc69bc708cf7da44 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50278 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/soc/mediatek/mt8192/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 9d22ef2..9109e61 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -78,7 +78,7 @@ $(foreach fw, $(call strip_quotes,$(mcu-firmware-files)), \ $(eval $(fw)-file := $(MT8192_BLOB_DIR)/$(fw)) \ $(eval $(fw)-type := raw) \ - $(eval $(fw)-compression := $(CBFS_COMPRESS_FLAG)) \ + $(eval $(fw)-compression := LZ4) \ $(if $(wildcard $($(fw)-file)), $(eval cbfs-files-y += $(fw)), ) \ ) -- To view, visit https://review.coreboot.org/c/coreboot/+/50278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida35e7f6e0572ad43082e53bcc69bc708cf7da44 Gerrit-Change-Number: 50278 Gerrit-PatchSet: 2 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Yidi Lin <yidi.lin(a)mediatek.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: device/device.c: Print done at end of assign_resources()
by Patrick Georgi (Code Review) 05 Feb '21

05 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50189 ) Change subject: device/device.c: Print done at end of assign_resources() ...................................................................... device/device.c: Print done at end of assign_resources() First and last printk() log the same string. Add done at end of function. BUG = N/A TEST = Build and boot faceboot FBG1701 Change-Id: I66a64c7473a65206c3a4c4396c8c8ecba1eb1a57 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50189 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/device/device.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/device/device.c b/src/device/device.c index fe1ced5..18efd5d 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -284,7 +284,7 @@ curdev->ops->set_resources(curdev); } post_log_clear(); - printk(BIOS_SPEW, "%s %s, bus %d link: %d\n", + printk(BIOS_SPEW, "%s %s, bus %d link: %d done\n", dev_path(bus->dev), __func__, bus->secondary, bus->link_num); } -- To view, visit https://review.coreboot.org/c/coreboot/+/50189 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66a64c7473a65206c3a4c4396c8c8ecba1eb1a57 Gerrit-Change-Number: 50189 Gerrit-PatchSet: 4 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: device: correct code style
by Patrick Georgi (Code Review) 05 Feb '21

05 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49963 ) Change subject: device: correct code style ...................................................................... device: correct code style Revise the following aspects to follow coreboot's coding style: - Drop braces for single-statement condition and loop bodies. - Use `__func__` to print the current function's name. - Reflow pointer dereferences to fit in a single line. - Adjust the `*` position in pointer variable declarations. - Drop unnecessary `else` statements. BUG = N/A TEST = Build Compulab Intense-PC with secure oprom enabled Change-Id: I780251d946d5bea97658476d61d25555ec768dfc Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49963 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/device/azalia_device.c M src/device/device.c M src/device/device_const.c M src/device/device_util.c M src/device/i2c_bus.c 5 files changed, 41 insertions(+), 46 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c index e1899f1..e383821 100644 --- a/src/device/azalia_device.c +++ b/src/device/azalia_device.c @@ -174,9 +174,9 @@ reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID; write32(base + HDA_ICII_REG, reg32); - while (timeout--) { + while (timeout--) udelay(1); - } + timeout = 50; while (timeout--) { reg32 = read32(base + HDA_ICII_REG); diff --git a/src/device/device.c b/src/device/device.c index ffdfeac..fe1ced5 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -166,8 +166,8 @@ if (!curdev->ops || !curdev->ops->read_resources) { if (curdev->path.type != DEVICE_PATH_APIC) - printk(BIOS_ERR, "%s missing read_resources\n", - dev_path(curdev)); + printk(BIOS_ERR, "%s missing %s\n", + dev_path(curdev), __func__); continue; } post_log_path(curdev); @@ -178,8 +178,8 @@ read_resources(link); } post_log_clear(); - printk(BIOS_SPEW, "%s read_resources bus %d link: %d done\n", - dev_path(bus->dev), bus->secondary, bus->link_num); + printk(BIOS_SPEW, "%s %s bus %d link: %d done\n", + dev_path(bus->dev), __func__, bus->secondary, bus->link_num); } struct device *vga_pri = NULL; @@ -210,11 +210,10 @@ "A bridge on the path doesn't support 16-bit VGA decoding!"); } - if (dev->on_mainboard) { + if (dev->on_mainboard) vga_onboard = dev; - } else { + else vga = dev; - } /* It isn't safe to enable all VGA cards. */ dev->command &= ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO); @@ -269,8 +268,8 @@ { struct device *curdev; - printk(BIOS_SPEW, "%s assign_resources, bus %d link: %d\n", - dev_path(bus->dev), bus->secondary, bus->link_num); + printk(BIOS_SPEW, "%s %s, bus %d link: %d\n", + dev_path(bus->dev), __func__, bus->secondary, bus->link_num); for (curdev = bus->children; curdev; curdev = curdev->sibling) { if (!curdev->enabled || !curdev->resource_list) @@ -285,8 +284,8 @@ curdev->ops->set_resources(curdev); } post_log_clear(); - printk(BIOS_SPEW, "%s assign_resources, bus %d link: %d\n", - dev_path(bus->dev), bus->secondary, bus->link_num); + printk(BIOS_SPEW, "%s %s, bus %d link: %d\n", + dev_path(bus->dev), __func__, bus->secondary, bus->link_num); } /** diff --git a/src/device/device_const.c b/src/device/device_const.c index 5288a74..2ce76c6 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -9,7 +9,7 @@ #include <device/resource.h> /** Linked list of ALL devices */ -DEVTREE_CONST struct device * DEVTREE_CONST all_devices = &dev_root; +DEVTREE_CONST struct device *DEVTREE_CONST all_devices = &dev_root; /** * Given a PCI bus and a devfn number, find the device structure. diff --git a/src/device/device_util.c b/src/device/device_util.c index 0337fb2..71c281e 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -370,7 +370,8 @@ resource->next = NULL; tail = dev->resource_list; if (tail) { - while (tail->next) tail = tail->next; + while (tail->next) + tail = tail->next; tail->next = resource; } else { dev->resource_list = resource; @@ -555,7 +556,7 @@ /* If it is a subtractive resource recurse. */ if (res->flags & IORESOURCE_SUBTRACTIVE) { - struct bus * subbus; + struct bus *subbus; for (subbus = curdev->link_list; subbus; subbus = subbus->next) if (subbus->link_num @@ -604,11 +605,10 @@ return; dev->enabled = enable; - if (dev->ops && dev->ops->enable) { + if (dev->ops && dev->ops->enable) dev->ops->enable(dev); - } else if (dev->chip_ops && dev->chip_ops->enable_dev) { + else if (dev->chip_ops && dev->chip_ops->enable_dev) dev->chip_ops->enable_dev(dev); - } } void disable_children(struct bus *bus) @@ -814,7 +814,7 @@ buf, resource_type(resource), comment); } -void show_all_devs_resources(int debug_level, const char* msg) +void show_all_devs_resources(int debug_level, const char *msg) { struct device *dev; diff --git a/src/device/i2c_bus.c b/src/device/i2c_bus.c index a65cdad..93ec854 100644 --- a/src/device/i2c_bus.c +++ b/src/device/i2c_bus.c @@ -48,19 +48,17 @@ .len = sizeof(val), }; - const int ret = busdev->ops->ops_i2c_bus-> - transfer(busdev, &msg, 1); + const int ret = busdev->ops->ops_i2c_bus->transfer(busdev, &msg, 1); if (ret) return ret; else return val; } else if (busdev->ops->ops_smbus_bus->recv_byte) { return busdev->ops->ops_smbus_bus->recv_byte(dev); - } else { - printk(BIOS_ERR, "%s Missing ops_smbus_bus->recv_byte", - dev_path(busdev)); - return -1; } + + printk(BIOS_ERR, "%s Missing ops_smbus_bus->recv_byte", dev_path(busdev)); + return -1; } int i2c_dev_writeb(struct device *const dev, uint8_t val) @@ -79,11 +77,11 @@ return busdev->ops->ops_i2c_bus->transfer(busdev, &msg, 1); } else if (busdev->ops->ops_smbus_bus->send_byte) { return busdev->ops->ops_smbus_bus->send_byte(dev, val); - } else { - printk(BIOS_ERR, "%s Missing ops_smbus_bus->send_byte", - dev_path(busdev)); - return -1; } + + printk(BIOS_ERR, "%s Missing ops_smbus_bus->send_byte", + dev_path(busdev)); + return -1; } int i2c_dev_readb_at(struct device *const dev, uint8_t off) @@ -109,23 +107,21 @@ }, }; - const int ret = busdev->ops->ops_i2c_bus-> - transfer(busdev, msg, ARRAY_SIZE(msg)); + const int ret = busdev->ops->ops_i2c_bus->transfer(busdev, msg, + ARRAY_SIZE(msg)); if (ret) return ret; else return val; } else if (busdev->ops->ops_smbus_bus->read_byte) { return busdev->ops->ops_smbus_bus->read_byte(dev, off); - } else { - printk(BIOS_ERR, "%s Missing ops_smbus_bus->read_byte", - dev_path(busdev)); - return -1; } + + printk(BIOS_ERR, "%s Missing ops_smbus_bus->read_byte", dev_path(busdev)); + return -1; } -int i2c_dev_writeb_at(struct device *const dev, - const uint8_t off, const uint8_t val) +int i2c_dev_writeb_at(struct device *const dev, const uint8_t off, const uint8_t val) { struct device *const busdev = i2c_busdev(dev); if (!busdev) @@ -142,15 +138,15 @@ return busdev->ops->ops_i2c_bus->transfer(busdev, &msg, 1); } else if (busdev->ops->ops_smbus_bus->write_byte) { return busdev->ops->ops_smbus_bus->write_byte(dev, off, val); - } else { - printk(BIOS_ERR, "%s Missing ops_smbus_bus->write_byte", - dev_path(busdev)); - return -1; } + + printk(BIOS_ERR, "%s Missing ops_smbus_bus->write_byte", + dev_path(busdev)); + return -1; } -int i2c_dev_read_at16(struct device *const dev, - uint8_t *const buf, const size_t len, uint16_t off) +int i2c_dev_read_at16(struct device *const dev, uint8_t *const buf, const size_t len, + uint16_t off) { struct device *const busdev = i2c_busdev(dev); if (!busdev) @@ -173,8 +169,8 @@ }; write_be16(&off, off); - const int ret = busdev->ops->ops_i2c_bus->transfer( - busdev, msg, ARRAY_SIZE(msg)); + const int ret = busdev->ops->ops_i2c_bus->transfer(busdev, msg, + ARRAY_SIZE(msg)); if (ret) return ret; else -- To view, visit https://review.coreboot.org/c/coreboot/+/49963 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I780251d946d5bea97658476d61d25555ec768dfc Gerrit-Change-Number: 49963 Gerrit-PatchSet: 4 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/ocp/deltalake: Override SMBIOS type 4 max speed
by Tim Chu (Code Review) 05 Feb '21

05 Feb '21

Tim Chu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48640 ) Change subject: mb/ocp/deltalake: Override SMBIOS type 4 max speed ...................................................................... mb/ocp/deltalake: Override SMBIOS type 4 max speed Override SMBIOS type 4 max speed. This field should be maximum speed supported by the system. 4000MHz is expected for Delta Lake. Tested=Execute "dmidecode -t 4" to check max speed is correct. Signed-off-by: Tim Chu <Tim.Chu(a)quantatw.com> Change-Id: I67edf657a2fe66b38e08056d558e1b360c4b8adc --- M src/mainboard/ocp/deltalake/ramstage.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48640/1 diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index 72a74da..64229fe 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -96,6 +96,12 @@ return 0x10; } +unsigned int smbios_cpu_get_max_speed_mhz(void) +{ + /* This will return 4000MHz */ + return 0xfa0; +} + /* System Slot Socket, Stack, Type and Data bus width Information */ typedef struct { u8 stack; -- To view, visit https://review.coreboot.org/c/coreboot/+/48640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67edf657a2fe66b38e08056d558e1b360c4b8adc Gerrit-Change-Number: 48640 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86/smbios: Correct SMBIOS type 4 max speed
by Tim Chu (Code Review) 05 Feb '21

05 Feb '21

Tim Chu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48636 ) Change subject: arch/x86/smbios: Correct SMBIOS type 4 max speed ...................................................................... arch/x86/smbios: Correct SMBIOS type 4 max speed Now smbios type 4 max speed field will use the maximum speed of processor itself if CPUID value can be accessed. However, this field should be the maximum processor speed supported by th system. Here we use smbios_cpu_get_max_speed_mhz only to get correct value. Tested=Execute "dmidecode -t 4" to check max speed is correct. Signed-off-by: Tim Chu <Tim.Chu(a)quantatw.com> Change-Id: Iae8e01a5e455709a57d60a840f279685c8aab80f --- M src/arch/x86/smbios.c 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/48636/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index aaf989d..3caf1c1 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -673,15 +673,16 @@ t->processor_upgrade = get_socket_type(); len = t->length + smbios_string_table_len(t->eos); if (cpu_have_cpuid() && cpuid_get_max_func() >= 0x16) { - t->max_speed = cpuid_ebx(0x16); t->current_speed = cpuid_eax(0x16); /* base frequency */ t->external_clock = cpuid_ecx(0x16); } else { - t->max_speed = smbios_cpu_get_max_speed_mhz(); t->current_speed = smbios_cpu_get_current_speed_mhz(); t->external_clock = smbios_processor_external_clock(); } + /* This field identifies a capability for the system, not the processor itself. */ + t->max_speed = smbios_cpu_get_max_speed_mhz(); + if (cpu_have_cpuid()) { res = cpuid(1); -- To view, visit https://review.coreboot.org/c/coreboot/+/48636 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae8e01a5e455709a57d60a840f279685c8aab80f Gerrit-Change-Number: 48636 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork: update telemetry settings for Woomax
by Patrick Georgi (Code Review) 05 Feb '21

05 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50256 ) Change subject: mb/google/zork: update telemetry settings for Woomax ...................................................................... mb/google/zork: update telemetry settings for Woomax Improve performance and meet stardust test requirement. PcdSet32(PcdTelemetry_VddcrVddfull_Scale_Current,102586) PcdSet32(PcdTelemetry_VddcrVddOffset, 0) PcdSet32(PcdTelemetry_VddcrSocfull_Scale_Current,24674) PcdSet32(PcdTelemetry_VddcrSocOffset, 0) BUG=b:176156237 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Change-Id: I81dbfafffe7625c3d0d80419466240508f9b041b Reviewed-on: https://review.coreboot.org/c/coreboot/+/50256 Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/zork/variants/woomax/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Kane Chen: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/zork/variants/woomax/overridetree.cb b/src/mainboard/google/zork/variants/woomax/overridetree.cb index 15d6ee8..95c7823 100644 --- a/src/mainboard/google/zork/variants/woomax/overridetree.cb +++ b/src/mainboard/google/zork/variants/woomax/overridetree.cb @@ -16,9 +16,9 @@ register "stapm_time_constant_s" = "200" register "sustained_power_limit_mW" = "15000" - register "telemetry_vddcr_vdd_slope_mA" = "101070" + register "telemetry_vddcr_vdd_slope_mA" = "102586" register "telemetry_vddcr_vdd_offset" = "0" - register "telemetry_vddcr_soc_slope_mA" = "24560" + register "telemetry_vddcr_soc_slope_mA" = "24674" register "telemetry_vddcr_soc_offset" = "0" # End : OPN Performance Configuration -- To view, visit https://review.coreboot.org/c/coreboot/+/50256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81dbfafffe7625c3d0d80419466240508f9b041b Gerrit-Change-Number: 50256 Gerrit-PatchSet: 3 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Edward Hill <ecgh(a)google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Chuang <alanchuang(a)google.com> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/skylake/acpi/irqlinks.asl: Fix typo in comment
by Patrick Georgi (Code Review) 05 Feb '21

05 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50269 ) Change subject: soc/intel/skylake/acpi/irqlinks.asl: Fix typo in comment ...................................................................... soc/intel/skylake/acpi/irqlinks.asl: Fix typo in comment Change-Id: Ifbe012a9867a6814f64abcfe336e5edca19df879 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50269 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/skylake/acpi/irqlinks.asl 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/src/soc/intel/skylake/acpi/irqlinks.asl b/src/soc/intel/skylake/acpi/irqlinks.asl index da82523..483be59 100644 --- a/src/soc/intel/skylake/acpi/irqlinks.asl +++ b/src/soc/intel/skylake/acpi/irqlinks.asl @@ -5,7 +5,7 @@ * * Due to what appears to be an ACPI interpreter bug we do not use * the PCRB() method here as it may not be defined yet because the method - * definiton depends on the order of the include files in pch.asl. + * definition depends on the order of the include files in pch.asl. * * https://bugs.acpica.org/show_bug.cgi?id=1201 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/50269 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbe012a9867a6814f64abcfe336e5edca19df879 Gerrit-Change-Number: 50269 Gerrit-PatchSet: 3 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit February 2021