coreboot-gerrit February 2021

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Change in coreboot[master]: soc/intel/alderlake: Increase VBT size to 9 KiB
by Maulik V Vaghela (Code Review) 05 Feb '21

05 Feb '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik. Hello build bot (Jenkins), Tim Wawrzynczak, Rizwan Qureshi, Subrata Banik, Meera Ravindranath, Ronak Kanabar, Aamir Bohra, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50299 to look at the new patch set (#3). Change subject: soc/intel/alderlake: Increase VBT size to 9 KiB ...................................................................... soc/intel/alderlake: Increase VBT size to 9 KiB Alderlake includes latest VBT (version 237 onwards),which has size of 8.5 KiB. This change is specific to alderlake so utilizing Kconfig option to increase VBT size specifically for ADL platforms. BUG=None BRANCH=None TEST=Include new VBT and boot the platform. Able to see firmware screen Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Change-Id: I438f4bce0a2dfa208e1cd59d1cd5dd1c5ad50833 --- M src/soc/intel/alderlake/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/50299/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/50299 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I438f4bce0a2dfa208e1cd59d1cd5dd1c5ad50833 Gerrit-Change-Number: 50299 Gerrit-PatchSet: 3 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Increase VBT size to 9 KiB
by Furquan Shaikh (Code Review) 05 Feb '21

05 Feb '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50299 ) Change subject: soc/intel/alderlake: Increase VBT size to 9 KiB ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/50299/comment/dc1eb0b7_349cfbdf PS2, Line 17: signed-off-by No Signed-off-by line in commit message 'S' needs to be uppercase. -- To view, visit https://review.coreboot.org/c/coreboot/+/50299 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I438f4bce0a2dfa208e1cd59d1cd5dd1c5ad50833 Gerrit-Change-Number: 50299 Gerrit-PatchSet: 2 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Fri, 05 Feb 2021 07:14:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Increase VBT size to 9 KiB
by Maulik V Vaghela (Code Review) 05 Feb '21

05 Feb '21

Attention is currently required from: Subrata Banik. Hello Rizwan Qureshi, Subrata Banik, Meera Ravindranath, Ronak Kanabar, Aamir Bohra, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50299 to look at the new patch set (#2). Change subject: soc/intel/alderlake: Increase VBT size to 9 KiB ...................................................................... soc/intel/alderlake: Increase VBT size to 9 KiB Alderlake includes latest VBT (version 237 onwards),which has size of 8.5 KiB. This change is specific to alderlake so utilizing Kconfig option to increase VBT size specifically for ADL platforms. BUG=None BRANCH=None TEST=Include new VBT and boot the platform. Able to see firmware screen signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Change-Id: I438f4bce0a2dfa208e1cd59d1cd5dd1c5ad50833 --- M src/soc/intel/alderlake/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/50299/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50299 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I438f4bce0a2dfa208e1cd59d1cd5dd1c5ad50833 Gerrit-Change-Number: 50299 Gerrit-PatchSet: 2 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Increase VBT size to 9 KiB
by Maulik V Vaghela (Code Review) 05 Feb '21

05 Feb '21

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50299 ) Change subject: soc/intel/alderlake: Increase VBT size to 9 KiB ...................................................................... soc/intel/alderlake: Increase VBT size to 9 KiB Alderlake includes latest VBT (version 237 onwards),which has size of 8.5 KiB. This change is specific to alderlake so utilizing Kconfig option to increase VBT size specifically for ADL platforms. BUG=None BRANCH=None TEST=Include new VBT and boot the platform. Able to see firmware screen signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Change-Id: I438f4bce0a2dfa208e1cd59d1cd5dd1c5ad50833 --- M src/soc/intel/alderlake/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/50299/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 806c91b..ccd21c9 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -198,6 +198,10 @@ default 0xfe03e000 depends on INTEL_LPSS_UART_FOR_CONSOLE +config VBT_DATA_SIZE_KB + int + default 9 + # Clock divider parameters for 115200 baud rate # Baudrate = (UART source clcok * M) /(N *16) # ADL UART source clock: 120MHz -- To view, visit https://review.coreboot.org/c/coreboot/+/50299 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I438f4bce0a2dfa208e1cd59d1cd5dd1c5ad50833 Gerrit-Change-Number: 50299 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/fsp2_0: Add support for MP services2 PPI
by Furquan Shaikh (Code Review) 05 Feb '21

05 Feb '21

Attention is currently required from: Martin Roth, Tim Wawrzynczak, Meera Ravindranath, Aamir Bohra, Andrey Petrov, Patrick Rudolph. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49474 ) Change subject: drivers/intel/fsp2_0: Add support for MP services2 PPI ...................................................................... Patch Set 10: Code-Review+2 (1 comment) File src/drivers/intel/fsp2_0/include/fsp/ppi/mp_service_ppi.h: https://review.coreboot.org/c/coreboot/+/49474/comment/caa73b42_f5d78b67 PS10, Line 38: efi_return_status_t mp_api_unsupported(void); nit: This can be an inline function too here in .h file -- To view, visit https://review.coreboot.org/c/coreboot/+/49474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id74baf17fb90147d229c78be90268fdc3ec1badc Gerrit-Change-Number: 49474 Gerrit-PatchSet: 10 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 05 Feb 2021 06:49:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] soc/intel/braswell: Use acpigen for wifi_regulatory_domain()
by Kyösti Mälkki (Code Review) 05 Feb '21

05 Feb '21

Attention is currently required from: Patrick Rudolph. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50298 ) Change subject: [WIP] soc/intel/braswell: Use acpigen for wifi_regulatory_domain() ...................................................................... [WIP] soc/intel/braswell: Use acpigen for wifi_regulatory_domain() Change-Id: I012dc849b69c6c504f005a71c885ab230f3b795a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/cyan/dsdt.asl M src/mainboard/intel/strago/dsdt.asl M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/acpi/globalnvs.asl D src/soc/intel/common/acpi/wifi.asl 5 files changed, 1 insertion(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/50298/1 diff --git a/src/mainboard/google/cyan/dsdt.asl b/src/mainboard/google/cyan/dsdt.asl index 8c363ad..ddf0fbb 100644 --- a/src/mainboard/google/cyan/dsdt.asl +++ b/src/mainboard/google/cyan/dsdt.asl @@ -40,9 +40,6 @@ { Name (_ADR, 0x001C0002) // _ADR: Address OperationRegion(RPXX, PCI_Config, 0x00, 0x10) - - /* Wifi Device */ - #include <soc/intel/common/acpi/wifi.asl> } } #include <southbridge/intel/common/acpi/sleepstates.asl> diff --git a/src/mainboard/intel/strago/dsdt.asl b/src/mainboard/intel/strago/dsdt.asl index dfe9809..003cc1b 100644 --- a/src/mainboard/intel/strago/dsdt.asl +++ b/src/mainboard/intel/strago/dsdt.asl @@ -35,9 +35,6 @@ { Name (_ADR, 0x001C0002) // _ADR: Address OperationRegion(RPXX, PCI_Config, 0x00, 0x10) - - /* Wifi Device */ - #include <soc/intel/common/acpi/wifi.asl> } } #include <southbridge/intel/common/acpi/sleepstates.asl> diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 2c3118e..aa524d3 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> #include <device/mmio.h> #include <arch/smp/mpspec.h> @@ -16,13 +15,11 @@ #include <soc/iomap.h> #include <soc/irq.h> #include <soc/msr.h> -#include <soc/nvs.h> #include <soc/pattrs.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <string.h> #include <types.h> -#include <wrdd.h> #define MWAIT_RES(state, sub_state) \ { \ @@ -59,15 +56,6 @@ } }; -void soc_fill_gnvs(struct global_nvs *gnvs) -{ - /* Fill in the Wi-Fi Region ID */ - if (CONFIG(HAVE_REGULATORY_DOMAIN)) - gnvs->cid1 = wifi_regulatory_domain(); - else - gnvs->cid1 = WRDD_DEFAULT_REGULATORY_DOMAIN; -} - int acpi_sci_irq(void) { u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL); diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl index 9a43671..4650882 100644 --- a/src/soc/intel/braswell/acpi/globalnvs.asl +++ b/src/soc/intel/braswell/acpi/globalnvs.asl @@ -27,7 +27,7 @@ PM1I, 32, /* 0x15 - System Wake Source - PM1 Index */ GPEI, 32, /* 0x19 - GPE Wake Source */ BDID, 8, /* 0x1d - Board ID */ - CID1, 16, /* 0x1e - Wifi Domain Type */ + , 16, /* 0x1e - Wifi Domain Type */ /* Device Config */ S5U0, 8, /* 0x20 - Enable USB0 in S5 */ diff --git a/src/soc/intel/common/acpi/wifi.asl b/src/soc/intel/common/acpi/wifi.asl deleted file mode 100644 index 23923a5..0000000 --- a/src/soc/intel/common/acpi/wifi.asl +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Device (WIFI) -{ - Name (_ADR, Zero) - OperationRegion(WIXX, PCI_Config, 0x00, 0x10) - Name (WRDX, Package() - { - // Revision - 0, - Package() - { - // DomainType, 0x7:WiFi - 0x00000007, - // Default Regulatory Domain Country identifier - 0x4150, - } - }) - Method(WRDD,0,Serialized) - { - DeRefOf (WRDX[1])[1] = \CID1 // Country identifier - - Return(WRDX) - } - -} -- To view, visit https://review.coreboot.org/c/coreboot/+/50298 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I012dc849b69c6c504f005a71c885ab230f3b795a Gerrit-Change-Number: 50298 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel: Drop CID1 from GNVS
by Kyösti Mälkki (Code Review) 05 Feb '21

05 Feb '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50297 ) Change subject: soc/intel: Drop CID1 from GNVS ...................................................................... soc/intel: Drop CID1 from GNVS The only reference to CID1 is in common/acpi/wifi.asl and only two braswell boards include it. Everywhere else the value in GNVS was unused. Change-Id: I09ea756fb3743e33d1e221f0a0df3a6fdc3fc3ba Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/alderlake/acpi.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/common/block/acpi/acpi/globalnvs.asl M src/soc/intel/elkhartlake/acpi.c M src/soc/intel/icelake/acpi.c M src/soc/intel/jasperlake/acpi.c M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/tigerlake/acpi.c 9 files changed, 2 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/50297/1 diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c index c1c53a6..2eb6101 100644 --- a/src/soc/intel/alderlake/acpi.c +++ b/src/soc/intel/alderlake/acpi.c @@ -20,7 +20,6 @@ #include <soc/systemagent.h> #include <string.h> #include <types.h> -#include <wrdd.h> /* * List of supported C-states in this processor. @@ -275,9 +274,6 @@ /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable; - /* Fill in the Wifi Region id */ - gnvs->cid1 = wifi_regulatory_domain(); - /* Set USB2/USB3 wake enable bitmaps. */ gnvs->u2we = config->usb2_wake_enable_bitmap; gnvs->u3we = config->usb3_wake_enable_bitmap; diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index bc00221..03bf3c8 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -18,7 +18,6 @@ #include <soc/pm.h> #include <soc/systemagent.h> #include <string.h> -#include <wrdd.h> #include "chip.h" @@ -179,9 +178,6 @@ /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable; - /* Fill in the Wifi Region id */ - gnvs->cid1 = wifi_regulatory_domain(); - /* Set USB2/USB3 wake enable bitmaps. */ gnvs->u2we = config->usb2_wake_enable_bitmap; gnvs->u3we = config->usb3_wake_enable_bitmap; diff --git a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl index 18852d4..d9ecfb3 100644 --- a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl +++ b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl @@ -20,7 +20,7 @@ DPTE, 8, // 0x1c - Enable DPTF NHLA, 64, // 0x1d - 0x24 NHLT Address NHLL, 32, // 0x25 - 0x28 NHLT Length - CID1, 16, // 0x29 - 0x2a Wifi Country Identifier + , 16, // 0x29 - 0x2a Wifi Country Identifier U2WE, 16, // 0x2b - 0x2c USB2 Wake Enable Bitmap U3WE, 16, // 0x2d - 0x2e USB3 Wake Enable Bitmap UIOR, 8, // 0x2f - UART debug controller init on S3 resume diff --git a/src/soc/intel/elkhartlake/acpi.c b/src/soc/intel/elkhartlake/acpi.c index 102e7d9..12706c9 100644 --- a/src/soc/intel/elkhartlake/acpi.c +++ b/src/soc/intel/elkhartlake/acpi.c @@ -19,7 +19,6 @@ #include <soc/soc_chip.h> #include <soc/systemagent.h> #include <string.h> -#include <wrdd.h> /* * List of supported C-states in this processor. @@ -243,9 +242,6 @@ /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable; - /* Fill in the Wifi Region id */ - gnvs->cid1 = wifi_regulatory_domain(); - /* Set USB2/USB3 wake enable bitmaps. */ gnvs->u2we = config->usb2_wake_enable_bitmap; gnvs->u3we = config->usb3_wake_enable_bitmap; diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index 753ee87..67c43e2 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -16,7 +16,6 @@ #include <soc/soc_chip.h> #include <soc/systemagent.h> #include <string.h> -#include <wrdd.h> /* * List of supported C-states in this processor. @@ -174,9 +173,6 @@ /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable; - /* Fill in the Wifi Region id */ - gnvs->cid1 = wifi_regulatory_domain(); - /* Set USB2/USB3 wake enable bitmaps. */ gnvs->u2we = config->usb2_wake_enable_bitmap; gnvs->u3we = config->usb3_wake_enable_bitmap; diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c index 596ef35..f33bebd 100644 --- a/src/soc/intel/jasperlake/acpi.c +++ b/src/soc/intel/jasperlake/acpi.c @@ -19,7 +19,6 @@ #include <soc/soc_chip.h> #include <soc/systemagent.h> #include <string.h> -#include <wrdd.h> /* * List of supported C-states in this processor. @@ -270,9 +269,6 @@ /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable; - /* Fill in the Wifi Region id */ - gnvs->cid1 = wifi_regulatory_domain(); - /* Set USB2/USB3 wake enable bitmaps. */ gnvs->u2we = config->usb2_wake_enable_bitmap; gnvs->u3we = config->usb3_wake_enable_bitmap; diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 95cce82..100f16f 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -29,7 +29,6 @@ #include <soc/systemagent.h> #include <string.h> #include <types.h> -#include <wrdd.h> #include <device/pci_ops.h> #include "chip.h" @@ -163,9 +162,6 @@ /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable; - /* Fill in the Wifi Region id */ - gnvs->cid1 = wifi_regulatory_domain(); - /* Set USB2/USB3 wake enable bitmaps. */ gnvs->u2we = config->usb2_wake_enable_bitmap; gnvs->u3we = config->usb3_wake_enable_bitmap; diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index d5b2c20..1ae61fd 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -37,7 +37,7 @@ DPTE, 8, // 0x30 - Enable DPTF NHLA, 64, // 0x31 - NHLT Address NHLL, 32, // 0x39 - NHLT Length - CID1, 16, // 0x3d - Wifi Country Identifier + , 16, // 0x3d - Wifi Country Identifier U2WE, 16, // 0x3f - USB2 Wake Enable Bitmap U3WE, 8, // 0x41 - USB3 Wake Enable Bitmap UIOR, 8, // 0x42 - UART debug controller init on S3 resume diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index ac21f13..17d8a34 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -19,7 +19,6 @@ #include <soc/soc_chip.h> #include <soc/systemagent.h> #include <string.h> -#include <wrdd.h> /* * List of supported C-states in this processor. @@ -270,9 +269,6 @@ /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable; - /* Fill in the Wifi Region id */ - gnvs->cid1 = wifi_regulatory_domain(); - /* Set USB2/USB3 wake enable bitmaps. */ gnvs->u2we = config->usb2_wake_enable_bitmap; gnvs->u3we = config->usb3_wake_enable_bitmap; -- To view, visit https://review.coreboot.org/c/coreboot/+/50297 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09ea756fb3743e33d1e221f0a0df3a6fdc3fc3ba Gerrit-Change-Number: 50297 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork: update USB 3 controller phy Parameter for dirinboz
by Kangheui Won (Code Review) 05 Feb '21

05 Feb '21

Attention is currently required from: Kevin Chiu, Martin Roth, Furquan Shaikh, Bhanu Prakash Maiya, Felix Held. Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50282 ) Change subject: mb/google/zork: update USB 3 controller phy Parameter for dirinboz ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50282 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42a94e03fb6f8230d4356d16b8e0d2164bc61e3f Gerrit-Change-Number: 50282 Gerrit-PatchSet: 3 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 05 Feb 2021 06:06:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: add UPD for RV2 USB3 phy setting adjust
by Kangheui Won (Code Review) 05 Feb '21

05 Feb '21

Attention is currently required from: Kevin Chiu, chris wang, Felix Held. Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50240 ) Change subject: soc/amd/picasso: add UPD for RV2 USB3 phy setting adjust ...................................................................... Patch Set 13: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50240 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d5f69e840952cc5171af1ce8597628d1bede5cb Gerrit-Change-Number: 50240 Gerrit-PatchSet: 13 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: chris wang <Chris.Wang(a)amd.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 05 Feb 2021 06:06:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/kukui: Add byte mode/single rank DRAM support for burnet/esche
by Yu-Ping Wu (Code Review) 05 Feb '21

05 Feb '21

Attention is currently required from: Hung-Te Lin, Kevin Chiu. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50276 ) Change subject: mb/google/kukui: Add byte mode/single rank DRAM support for burnet/esche ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/50276/comment/a2a051de_4870d90d PS3, Line 15: > Add […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/50276 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa735c23889860218f6f6571cf0bc0b21b304b51 Gerrit-Change-Number: 50276 Gerrit-PatchSet: 4 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Comment-Date: Fri, 05 Feb 2021 05:55:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit February 2021