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Change subject: soc/amd/picasso: add UPD for RV2 USB3 phy setting adjust
......................................................................
Patch Set 13: Code-Review+2
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Change subject: mb/google/kukui: Add byte mode/single rank DRAM support for burnet/esche
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/50276/comment/a2a051de_4870d90d
PS3, Line 15:
> Add […]
Done
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Change subject: mb/google/kukui: Add byte mode/single rank DRAM support for burnet/esche
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/50276/comment/c13e2243_2695d8d0
PS3, Line 15:
> Add […]
Done
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Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#4).
Change subject: mb/google/kukui: Add byte mode/single rank DRAM support for burnet/esche
......................................................................
mb/google/kukui: Add byte mode/single rank DRAM support for burnet/esche
ID#5: Hynix - H9HCNNNFAMMLXR-NEE (Byte mode)
ID#7: MICRON - MT53E1G32D2NP-046 WT:A (Single rank)
BUG=b:165768895
BRANCH=kukui
TEST=1. emerge-jacuzzi coreboot
2. power on test ok
Change-Id: Iaa735c23889860218f6f6571cf0bc0b21b304b51
Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com>
---
M src/mainboard/google/kukui/sdram_configs.c
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/50276/4
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Change subject: mb/google/kukui: Add byte mode/single rank DRAM support for burnet/esche
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/50276/comment/9c9bc650_8aab33b4
PS3, Line 15:
Add
BRANCH=kukui
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Hello Hung-Te Lin, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/50294
to look at the new patch set (#2).
Change subject: Add mediatek mt8192 dram vendor code
......................................................................
Add mediatek mt8192 dram vendor code
Move coreboot mt8192 soc dram code to vendor folder,
it's more convinient to maintain mediatek dram codes.
Signed-off-by: Xi Chen <xixi.chen(a)mediatek.com>
Change-Id: I3853204578069c6abf52689ea6f5d88841414bd4
---
M src/soc/mediatek/mt8192/Kconfig
M src/soc/mediatek/mt8192/Makefile.inc
M src/vendorcode/Makefile.inc
A src/vendorcode/mediatek/Kconfig
A src/vendorcode/mediatek/Makefile.inc
A src/vendorcode/mediatek/mt8192/Makefile.inc
R src/vendorcode/mediatek/mt8192/dpm.c
R src/vendorcode/mediatek/mt8192/dramc_ana_init_config.c
R src/vendorcode/mediatek/mt8192/dramc_dig_config.c
R src/vendorcode/mediatek/mt8192/dramc_dvfs.c
R src/vendorcode/mediatek/mt8192/dramc_param.c
R src/vendorcode/mediatek/mt8192/dramc_pi_basic_api.c
R src/vendorcode/mediatek/mt8192/dramc_pi_calibration_api.c
R src/vendorcode/mediatek/mt8192/dramc_pi_main.c
R src/vendorcode/mediatek/mt8192/dramc_power.c
R src/vendorcode/mediatek/mt8192/dramc_subsys_config.c
R src/vendorcode/mediatek/mt8192/dramc_tracking.c
R src/vendorcode/mediatek/mt8192/dramc_utility.c
R src/vendorcode/mediatek/mt8192/emi.c
R src/vendorcode/mediatek/mt8192/include/soc/dpm.h
R src/vendorcode/mediatek/mt8192/include/soc/dramc_ac_timing.h
R src/vendorcode/mediatek/mt8192/include/soc/dramc_common_mt8192.h
R src/vendorcode/mediatek/mt8192/include/soc/dramc_param.h
R src/vendorcode/mediatek/mt8192/include/soc/dramc_pi_api.h
R src/vendorcode/mediatek/mt8192/include/soc/dramc_power.h
R src/vendorcode/mediatek/mt8192/include/soc/dramc_register.h
R src/vendorcode/mediatek/mt8192/include/soc/dramc_register_bits_def.h
R src/vendorcode/mediatek/mt8192/include/soc/emi.h
R src/vendorcode/mediatek/mt8192/memory.c
29 files changed, 62 insertions(+), 44 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/50294/2
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Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42685 )
Change subject: soc/amd/common: Drop ACPIMMIO bank for SMBus device PCI config
......................................................................
Patch Set 9:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/42685/comment/1669bd3a_3cacb3c5
PS9, Line 12: we execute had control over the UART configuration...
> I'll try to look into it. we might still need the ~1. […]
Well your previous comment says one could have just used PCI config writes, so this change isn't really about the UART any longer. I was just too lazy to change the commit message.
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Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: [WIP] ACPI: Unify acpi_wake_source and CBMEM_ID_POWER_STATE
......................................................................
[WIP] ACPI: Unify acpi_wake_source and CBMEM_ID_POWER_STATE
TBD: Promote acpi_pm_gpe_state and create/unify common
structur to store in CBMEM_ID_POWER_STATE.
Change-Id: Ia6688ec7abf16ed15f3db5da41b6e5ed73ffbc7d
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/soc/amd/common/block/acpi/Makefile.inc
D src/soc/amd/common/block/acpi/pm_state.c
M src/soc/intel/baytrail/ramstage.c
M src/soc/intel/broadwell/pch/Makefile.inc
D src/soc/intel/broadwell/pch/ramstage.c
M src/soc/intel/common/block/acpi/Makefile.inc
D src/soc/intel/common/block/acpi/acpi_wake_source.c
7 files changed, 0 insertions(+), 233 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/49357/2
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Hello Lance Zhao, build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Andrey Petrov, Patrick Rudolph, Felix Held,
I'd like you to reexamine a change. Please visit
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Change subject: [WIP] ACPI: Add acpi_reset_gnvs_for_wake()
......................................................................
[WIP] ACPI: Add acpi_reset_gnvs_for_wake()
With chipset_power_state filled in romstage CBMEM hooks and
GNVS allocated early in ramstage, GNVS wake source is now
also filled for normal boot path.
TBD: pm1i and gpei are indeces but u64 at places
Change-Id: I2d44770392d14d2d6e22cc98df9d1751c8717ff3
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/acpi/gnvs.c
M src/include/acpi/acpi_gnvs.h
M src/soc/amd/common/block/acpi/pm_state.c
M src/soc/amd/picasso/acpi.c
M src/soc/amd/stoneyridge/acpi.c
M src/soc/intel/alderlake/acpi.c
M src/soc/intel/apollolake/acpi.c
M src/soc/intel/baytrail/acpi.c
M src/soc/intel/baytrail/ramstage.c
M src/soc/intel/braswell/acpi.c
M src/soc/intel/broadwell/pch/lpc.c
M src/soc/intel/broadwell/pch/ramstage.c
M src/soc/intel/cannonlake/acpi.c
M src/soc/intel/common/block/acpi/acpi_wake_source.c
M src/soc/intel/elkhartlake/acpi.c
M src/soc/intel/icelake/acpi.c
M src/soc/intel/jasperlake/acpi.c
M src/soc/intel/skylake/acpi.c
M src/soc/intel/tigerlake/acpi.c
19 files changed, 63 insertions(+), 131 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/50004/6
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