coreboot-gerrit February 2021

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Change in coreboot[master]: soc/intel/tgl: Enable/Disable S0ix substates
by Furquan Shaikh (Code Review) 04 Feb '21

04 Feb '21

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Change in coreboot[master]: soc/amd/cezanne/fch: add ACPI I/O port setup
by Raul Rangel (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50270 ) Change subject: soc/amd/cezanne/fch: add ACPI I/O port setup ...................................................................... Patch Set 2: Code-Review+2 (1 comment) File src/soc/amd/cezanne/include/soc/iomap.h: https://review.coreboot.org/c/coreboot/+/50270/comment/c0aceafd_d3889601 PS2, Line 25: 0x10 > also that is hex, so there are more than 2 bytes in between 8 and 10 ;) all your base are belong to us! -- To view, visit https://review.coreboot.org/c/coreboot/+/50270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If80b841df12d351d5a0c1e0d2e7bf1e31b03447f Gerrit-Change-Number: 50270 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 04 Feb 2021 21:57:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne/fch: add ACPI I/O port setup
by Felix Held (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50270 ) Change subject: soc/amd/cezanne/fch: add ACPI I/O port setup ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/cezanne/include/soc/iomap.h: https://review.coreboot.org/c/coreboot/+/50270/comment/a0897c0f_7773d24b PS2, Line 25: 0x10 > TMR_BLK is 4 bytes. […] also that is hex, so there are more than 2 bytes in between 8 and 10 ;) -- To view, visit https://review.coreboot.org/c/coreboot/+/50270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If80b841df12d351d5a0c1e0d2e7bf1e31b03447f Gerrit-Change-Number: 50270 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Thu, 04 Feb 2021 21:56:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne/fch: add ACPI I/O port setup
by Felix Held (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50270 ) Change subject: soc/amd/cezanne/fch: add ACPI I/O port setup ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/cezanne/include/soc/iomap.h: https://review.coreboot.org/c/coreboot/+/50270/comment/4bf47122_d4575a45 PS2, Line 25: 0x10 > So in CB:41128 this was changed to 0x0c. […] TMR_BLK is 4 bytes. the offsets in this patch are the ones from the reference code; the ppr doesn't match the code and i've already filed a bug report on that internally. the patch you linked matched that to the docs that don't match the refcode. see my comment above about the same line in an older revision -- To view, visit https://review.coreboot.org/c/coreboot/+/50270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If80b841df12d351d5a0c1e0d2e7bf1e31b03447f Gerrit-Change-Number: 50270 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Thu, 04 Feb 2021 21:55:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: [UNTESTED] soc/amd/picasso/iomap: change ACPI_CPU_CONTROL to match AGESA
by Martin Roth (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50288 ) Change subject: [UNTESTED] soc/amd/picasso/iomap: change ACPI_CPU_CONTROL to match AGESA ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Tested on Morphius. Goes into suspend & resumes. Powerstates C1 & C2 work according to Powertop. Chris said something about cc6 in the previous patch that set it to 0x13, but I don't have the tool he used to do that. -- To view, visit https://review.coreboot.org/c/coreboot/+/50288 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80e11d9792ee4138cb376ebbe0438dc304b54527 Gerrit-Change-Number: 50288 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 04 Feb 2021 21:51:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tgl: Enable/Disable S0ix substates
by Shreesh Chhabbi (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Furquan Shaikh. Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49766 ) Change subject: soc/intel/tgl: Enable/Disable S0ix substates ...................................................................... Patch Set 11: (1 comment) File src/soc/intel/tigerlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/49766/comment/937f4409_8cd07aeb PS9, Line 60: and UP4 > I don't think this is correct for UP4. Ok. I thought that its applicable for both up3 and up4. I can make this only for up3. Is there a way to differentiate up3 from up4 in soc code? Do you have any suggestions to implement this? -- To view, visit https://review.coreboot.org/c/coreboot/+/49766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9 Gerrit-Change-Number: 49766 Gerrit-PatchSet: 11 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Thu, 04 Feb 2021 21:51:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tgl: Enable/Disable S0ix substates
by Furquan Shaikh (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Shreesh Chhabbi. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49766 ) Change subject: soc/intel/tgl: Enable/Disable S0ix substates ...................................................................... Patch Set 11: (8 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/49766/comment/09e55669_edf706d6 PS9, Line 7: Disable S0i3.2 & S0i3.3 substates : : S0i3.2 and S0i3.3 are applicable only if wake on voice is : disabled. As per Platform Design Guide, S0i3.2 and S0i3.3 : substates need to be disabled for Tigerlake. This needs update https://review.coreboot.org/c/coreboot/+/49766/comment/4a4f0e1e_be107afc PS9, Line 12: Can you please check what is the lowest power state reported by coreboot and actually observed on volteer devices? I see you have commented that you need to update volteer and tglrvp devicetrees. It would be good to validate the entire series. File src/soc/intel/tigerlake/chip.h: https://review.coreboot.org/c/coreboot/+/49766/comment/78878b4e_dad500f2 PS9, Line 502: enabled Rather than saying "enabled", I think it should say "Mainboard design uses external clock gating" since this is very much dependent on the hardware design. Same for external phy gating and external bypass rails. https://review.coreboot.org/c/coreboot/+/49766/comment/03df9929_a518f390 PS9, Line 506: ExternalClkGated nit: use external_clk_gated instead of ExternalClkGated. I know this file uses a mix of both styles, but the former is preferred. Also, the latter is mostly used for FSP UPDs. Same for configs below. File src/soc/intel/tigerlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/49766/comment/2dae88e3_2af37d56 PS9, Line 60: and UP4 I don't think this is correct for UP4. https://review.coreboot.org/c/coreboot/+/49766/comment/41a822b2_f9873292 PS9, Line 67: recommended It would be good to capture in commit message what "recommended" means i.e. it is possible to achieve this state, but is known to provide lower savings than shallower states. https://review.coreboot.org/c/coreboot/+/49766/comment/f65d0c3f_f953247e PS9, Line 71: /* If external phy gating is not implemented, S0i3.3/S0i3.4/S0i2.2 are not recommended. */ > line over 96 characters Can you please split this into multi-line comment? https://review.coreboot.org/c/coreboot/+/49766/comment/17db7814_fbff986c PS9, Line 76: if (is_dev_enabled(pcidev_path_on_root(PCH_DEVFN_CNVI_BT)) || is_dev_enabled(pcidev_path_on_root(PCH_DEVFN_CNVI_WIFI)) || is_dev_enabled(pcidev_path_on_root(PCH_DEVFN_ISH))) > line over 96 characters split into multiple lines: if (is_dev_enabled() || is_dev_enabled() || is_dev_enabled()) or you can add a helper: if (is_cnvi_or_ish_enabled()) and implement is_cnvi_or_ish_enabled() such that: bool is_cnvi_or_ish_enabled(void) { return is_dev_enabled() || is_dev_enabled() || is_dev_enabled(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/49766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9 Gerrit-Change-Number: 49766 Gerrit-PatchSet: 11 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Comment-Date: Thu, 04 Feb 2021 21:36:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tgl: Enable/Disable S0ix substates
by Shreesh Chhabbi (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Furquan Shaikh. Hello build bot (Jenkins), Furquan Shaikh, Ravishankar Sarawadi, Duncan Laurie, Alex Levin, Duncan Laurie, Sukumar Ghorai, Raj Astekar, Patrick Rudolph, Shreesh Chhabbi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49766 to look at the new patch set (#11). Change subject: soc/intel/tgl: Enable/Disable S0ix substates ...................................................................... soc/intel/tgl: Enable/Disable S0ix substates S0i3.2 and S0i3.3 are applicable only if wake on voice is disabled. As per Platform Design Guide, S0i3.2 and S0i3.3 substates need to be disabled for Tigerlake. BUG=b:177821896 TEST=Build coreboot for volteer Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9 --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params.c 2 files changed, 54 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/49766/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/49766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9 Gerrit-Change-Number: 49766 Gerrit-PatchSet: 11 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/tgl: Disable S0i3.2 & S0i3.3 substates
by Shreesh Chhabbi (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Furquan Shaikh, Shreesh Chhabbi. Hello build bot (Jenkins), Furquan Shaikh, Ravishankar Sarawadi, Duncan Laurie, Alex Levin, Duncan Laurie, Sukumar Ghorai, Raj Astekar, Patrick Rudolph, Shreesh Chhabbi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49766 to look at the new patch set (#10). Change subject: soc/intel/tgl: Disable S0i3.2 & S0i3.3 substates ...................................................................... soc/intel/tgl: Disable S0i3.2 & S0i3.3 substates S0i3.2 and S0i3.3 are applicable only if wake on voice is disabled. As per Platform Design Guide, S0i3.2 and S0i3.3 substates need to be disabled for Tigerlake. BUG=b:177821896 TEST=Build coreboot for volteer Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9 --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params.c 2 files changed, 54 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/49766/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/49766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9 Gerrit-Change-Number: 49766 Gerrit-PatchSet: 10 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/cezanne/fch: add ACPI I/O port setup
by Raul Rangel (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50270 ) Change subject: soc/amd/cezanne/fch: add ACPI I/O port setup ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/cezanne/include/soc/iomap.h: https://review.coreboot.org/c/coreboot/+/50270/comment/b540af2f_fc2dc47c PS2, Line 25: 0x10 So in CB:41128 this was changed to 0x0c. Is the TMR_BLK only 2 bytes? -- To view, visit https://review.coreboot.org/c/coreboot/+/50270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If80b841df12d351d5a0c1e0d2e7bf1e31b03447f Gerrit-Change-Number: 50270 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 04 Feb 2021 21:32:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit February 2021