Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50270 )
Change subject: soc/amd/cezanne/fch: add ACPI I/O port setup
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Patch Set 2:
(1 comment)
File src/soc/amd/cezanne/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/50270/comment/4bf47122_d4575a45
PS2, Line 25: 0x10
So in CB:41128 this was changed to 0x0c. […]
TMR_BLK is 4 bytes. the offsets in this patch are the ones from the reference code; the ppr doesn't match the code and i've already filed a bug report on that internally. the patch you linked matched that to the docs that don't match the refcode. see my comment above about the same line in an older revision
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