Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50270 )
Change subject: soc/amd/cezanne/fch: add ACPI I/O port setup
......................................................................
Patch Set 2:
(1 comment)
File src/soc/amd/cezanne/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/50270/comment/a0897c0f_7773d24b
PS2, Line 25: 0x10
TMR_BLK is 4 bytes. […]
also that is hex, so there are more than 2 bytes in between 8 and 10 ;)
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