Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held.
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50270 )
Change subject: soc/amd/cezanne/fch: add ACPI I/O port setup
......................................................................
Patch Set 2:
(1 comment)
File src/soc/amd/cezanne/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/50270/comment/b540af2f_fc2dc47c
PS2, Line 25: 0x10
So in CB:41128 this was changed to 0x0c. Is the TMR_BLK only 2 bytes?
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