coreboot-gerrit February 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: Documentation: Codify some guidelines for headers and chain-including
by HAOUAS Elyes (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Martin Roth, Julius Werner. HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50247 ) Change subject: Documentation: Codify some guidelines for headers and chain-including ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > I'd rather have Elyes ask before pushing 20 changes on the topic for review too. […] Please see https://review.coreboot.org/c/coreboot/+/50286 Thx -- To view, visit https://review.coreboot.org/c/coreboot/+/50247 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbcde306a814f52b3a41b58c7a33bdd99b0187e0 Gerrit-Change-Number: 50247 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 04 Feb 2021 20:11:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Comment-In-Reply-To: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: Add chain-include list of headers
by HAOUAS Elyes (Code Review) 04 Feb '21

04 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50286 ) Change subject: Documentation: Add chain-include list of headers ...................................................................... Documentation: Add chain-include list of headers This list a non exhaustive intentionally indirect includes. Change-Id: I474d0d4bd660b62c24508bc3eba67154e820d8a4 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- A Documentation/chain-include.md 1 file changed, 39 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/50286/1 diff --git a/Documentation/chain-include.md b/Documentation/chain-include.md new file mode 100644 index 0000000..82b8fee --- /dev/null +++ b/Documentation/chain-include.md @@ -0,0 +1,39 @@ +# Chain includes + +This is a non exhaustive list of headers that intentionally chain-include other headers: + +* include/cbfs.h: + * commonlib/cbfs.h: + * commonlib/bsd/cbfs_private.h: + * commonlib/bsd/cb_err.h + * commonlib/bsd/cbfs_serialized.h + +* include/console/console.h + * commonlib/loglevel.h + * console/vtxprintf.h + +* include/device/mmio.h: + * arch/mmio.h + +* include/device/pci_ops.h: + * arch/pci_ops.h: + * device/pci_mmio_cfg.h + * arch/pci_io_cfg.h: + * arch/io.h + +* include/gpio.h: + * soc/gpio.h + +* include/types.h: + * commonlib/bsd/cb_err.h + * stdbool.h + * stdint.h + * stddef.h + + +**NOTE**: +* src/include/*.h files: To avoid redundant inclusions, it would be better to direct include +the header when this one is in src/include root directory. +* src/include/types.h: <types.h> is not mandatory if you use only one or two src/include/*.h +chain-provided by <types.h>. + -- To view, visit https://review.coreboot.org/c/coreboot/+/50286 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I474d0d4bd660b62c24508bc3eba67154e820d8a4 Gerrit-Change-Number: 50286 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/mancomb: Add new mainboard
by Mathew King (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Furquan Shaikh, Martin Roth. Mathew King has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50007 ) Change subject: mb/google/mancomb: Add new mainboard ...................................................................... Patch Set 7: (2 comments) File src/mainboard/google/monkey_island/variants/baseboard/mancomb/gpio.c: https://review.coreboot.org/c/coreboot/+/50007/comment/558e72e1_ffae4d7c PS5, Line 8: 0 > Not required. Ack https://review.coreboot.org/c/coreboot/+/50007/comment/0d67791b_8d6ee4cc PS5, Line 13: 0 > Not required. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/50007 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1264f44a0b986f7f7c89ac7b42f1e4e4119a35e6 Gerrit-Change-Number: 50007 Gerrit-PatchSet: 7 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Thu, 04 Feb 2021 19:59:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork: Use Kconfig SPI speed & read mode in devicetree
by Martin Roth (Code Review) 04 Feb '21

04 Feb '21

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50285 ) Change subject: mb/google/zork: Use Kconfig SPI speed & read mode in devicetree ...................................................................... mb/google/zork: Use Kconfig SPI speed & read mode in devicetree We have Kconfig controls for the Fast SPI speed and SPI read mode, so tie those to the devicetree controls for those values. BUG=None TEST=Boot & Verify speeds & Mode are correct. BRANCH=Zork Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I116adf4fe0de5a2790894618ccff8ebf629fab34 --- M src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb M src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/50285/1 diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index e014ce3..a24699c 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -145,10 +145,10 @@ # SPI Configuration register "common_config.spi_config" = "{ .normal_speed = SPI_SPEED_33M, /* MHz */ - .fast_speed = SPI_SPEED_66M, /* MHz */ + .fast_speed = CONFIG_EFS_SPI_SPEED, .altio_speed = SPI_SPEED_66M, /* MHz */ .tpm_speed = SPI_SPEED_66M, /* MHz */ - .read_mode = SPI_READ_MODE_DUAL122, + .read_mode = CONFIG_EFS_SPI_READ_MODE, }" # eSPI Configuration diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index 5ec9010..8bcf003 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -137,10 +137,10 @@ # SPI Configuration register "common_config.spi_config" = "{ .normal_speed = SPI_SPEED_33M, /* MHz */ - .fast_speed = SPI_SPEED_66M, /* MHz */ + .fast_speed = CONFIG_EFS_SPI_SPEED, .altio_speed = SPI_SPEED_66M, /* MHz */ .tpm_speed = SPI_SPEED_66M, /* MHz */ - .read_mode = SPI_READ_MODE_DUAL122, + .read_mode = CONFIG_EFS_SPI_READ_MODE, }" # USB OC pin mapping -- To view, visit https://review.coreboot.org/c/coreboot/+/50285 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I116adf4fe0de5a2790894618ccff8ebf629fab34 Gerrit-Change-Number: 50285 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork: update telemetry settings for dirinboz
by Martin Roth (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Kevin Chiu, Furquan Shaikh, Bhanu Prakash Maiya, Eric Peers, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50283 ) Change subject: mb/google/zork: update telemetry settings for dirinboz ...................................................................... Patch Set 3: Code-Review+2 (1 comment) Patchset: PS3: The -25 seems odd to me, but that's what the bug specifies, so LGTM. -- To view, visit https://review.coreboot.org/c/coreboot/+/50283 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0c941815d062d9af01858faf2121bc69f23ab44 Gerrit-Change-Number: 50283 Gerrit-PatchSet: 3 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 04 Feb 2021 19:11:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork: Adjust Dirinboz H1 I2C CLK
by Martin Roth (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Kevin Chiu, Furquan Shaikh, Bhanu Prakash Maiya, Eric Peers. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50284 ) Change subject: mb/google/zork: Adjust Dirinboz H1 I2C CLK ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50284 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9067db9fc7a4d6aa2ce33b86ba6a611dfd5d7838 Gerrit-Change-Number: 50284 Gerrit-PatchSet: 4 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Comment-Date: Thu, 04 Feb 2021 19:10:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0/memory_init: check if UPD struct has expected size
by Marshall Dawson (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Furquan Shaikh, Meera Ravindranath, Andrey Petrov, Patrick Rudolph, Felix Held. Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50241 ) Change subject: drivers/intel/fsp2_0/memory_init: check if UPD struct has expected size ...................................................................... Patch Set 1: (1 comment) File src/drivers/intel/fsp2_0/memory_init.c: https://review.coreboot.org/c/coreboot/+/50241/comment/58e346bf_08aa1b25 PS1, Line 242: != > you mean >, since <= would be break the good case as well? if hdr->cfg_region_size is bigger than si […] After looking at the code again, yes you're right. We set up the UPD region to be sizeof(fspm_upd) so we need to ensure the FSP's cfg_region doesn't exceed that. -- To view, visit https://review.coreboot.org/c/coreboot/+/50241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7e9f6f20d0091bbb4abfd42abb40b485da2079d Gerrit-Change-Number: 50241 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin Frodsham <justin.frodsham(a)amd.corp-partner.google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 04 Feb 2021 19:08:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne/fch: add ACPI I/O port setup
by Marshall Dawson (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Felix Held. Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50270 ) Change subject: soc/amd/cezanne/fch: add ACPI I/O port setup ...................................................................... Patch Set 1: Code-Review+2 (2 comments) File src/soc/amd/cezanne/include/soc/iomap.h: https://review.coreboot.org/c/coreboot/+/50270/comment/31854bf9_d85658b8 PS1, Line 19: 0x0400 Curious why not use CONFIG_CEZANNE_ACPI_IO_BASE. 0x400 should be fine though. https://review.coreboot.org/c/coreboot/+/50270/comment/664ef160_31ed8c83 PS1, Line 25: 0x10 This differs from Picasso. Was changed in CB:44135 however I believe we stripped it from AGESA so it shouldn't be an issue. -- To view, visit https://review.coreboot.org/c/coreboot/+/50270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If80b841df12d351d5a0c1e0d2e7bf1e31b03447f Gerrit-Change-Number: 50270 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 04 Feb 2021 18:58:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/purism/librem_cnl: Implement `die_notify`
by Matt DeVillier (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Martin Roth, Benjamin Doron, Angel Pons. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50013 ) Change subject: mb/purism/librem_cnl: Implement `die_notify` ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > GPP_E8 is SATALED# for the SoC. […] GPP_E8 is NC on the Librem 14 -- To view, visit https://review.coreboot.org/c/coreboot/+/50013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ffac0ab02e52e9fbba7990f401d87e50a1b5154 Gerrit-Change-Number: 50013 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 04 Feb 2021 18:51:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/purism/librem_cnl: Implement `die_notify`
by Benjamin Doron (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Martin Roth, Matt DeVillier, Angel Pons. Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50013 ) Change subject: mb/purism/librem_cnl: Implement `die_notify` ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > Hmmm... Good point. […] GPP_E8 is SATALED# for the SoC. Unless the GPIO is known to be routed differently for some variants, I assume it's safe to move die.c out of variants. -- To view, visit https://review.coreboot.org/c/coreboot/+/50013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ffac0ab02e52e9fbba7990f401d87e50a1b5154 Gerrit-Change-Number: 50013 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 04 Feb 2021 18:29:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit February 2021