coreboot-gerrit September 2020

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Change in coreboot[master]: Add config IPMI_KCS_IO_TIMEOUT for IPMI KCS timeout value
by Johnny Lin (Code Review) 09 Sep '20

09 Sep '20

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45103 ) Change subject: Add config IPMI_KCS_IO_TIMEOUT for IPMI KCS timeout value ...................................................................... Add config IPMI_KCS_IO_TIMEOUT for IPMI KCS timeout value The current value of 1000 cycles of 100ns would see timeout occurs on OCP Delta Lake, especially when the log level is smaller than 8 because the prink(BIOS_SPEW, ..) in ipmi_kcs_status() creates delay and avoid the problem, but after setting log level to 4 we see the timeout occurs. Default remains as 1000. Change-Id: I42ede1d9200bb5d0dbb455d2ff66e2816f10e86b Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/drivers/ipmi/Kconfig M src/drivers/ipmi/ipmi_kcs.c 2 files changed, 9 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/45103/1 diff --git a/src/drivers/ipmi/Kconfig b/src/drivers/ipmi/Kconfig index 44ed17e..f86f609 100644 --- a/src/drivers/ipmi/Kconfig +++ b/src/drivers/ipmi/Kconfig @@ -33,3 +33,10 @@ help The PNP base address of BMC KCS. It must be equal to the pnp port value defined in devicetree for chip drivers/ipmi. + +config IPMI_KCS_IO_TIMEOUT + int + default 1000 + depends on IPMI_KCS + help + The timeout time for a single KCS IO in the unit of 100 microseconds. diff --git a/src/drivers/ipmi/ipmi_kcs.c b/src/drivers/ipmi/ipmi_kcs.c index 1d6b71c..e1f6c75 100644 --- a/src/drivers/ipmi/ipmi_kcs.c +++ b/src/drivers/ipmi/ipmi_kcs.c @@ -35,7 +35,7 @@ static int wait_ibf_timeout(int port) { - int timeout = 1000; + int timeout = CONFIG_IPMI_KCS_IO_TIMEOUT; do { if (!(ipmi_kcs_status(port) & IPMI_KCS_IBF)) return 0; @@ -47,7 +47,7 @@ static int wait_obf_timeout(int port) { - int timeout = 1000; + int timeout = CONFIG_IPMI_KCS_IO_TIMEOUT; do { if ((ipmi_kcs_status(port) & IPMI_KCS_OBF)) return 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/45103 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42ede1d9200bb5d0dbb455d2ff66e2816f10e86b Gerrit-Change-Number: 45103 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer/variants/eldrid: add memory.c for ddr4 support
by Nick Chen (Code Review) 09 Sep '20

09 Sep '20

Nick Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44632 ) Change subject: mb/google/volteer/variants/eldrid: add memory.c for ddr4 support ...................................................................... mb/google/volteer/variants/eldrid: add memory.c for ddr4 support Add new memory.c to support DDR4 memory types. Use the new meminit_ddr() and variant_memory_sku() for eldrid variant code on memory.c BUG=b:161772961 TEST='emerge-volteer coreboot chromeos-bootimage' and verify that volteer can boots. NOTE that tests the ddr4 side of the implementation. Change-Id: I2c7b30093a8d85bac5aba5b83768af5eb36c4f70 --- A src/mainboard/google/volteer/variants/eldrid/Makefile.inc A src/mainboard/google/volteer/variants/eldrid/gpio.c A src/mainboard/google/volteer/variants/eldrid/memory.c M src/mainboard/google/volteer/variants/eldrid/overridetree.cb 4 files changed, 523 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/44632/1 diff --git a/src/mainboard/google/volteer/variants/eldrid/Makefile.inc b/src/mainboard/google/volteer/variants/eldrid/Makefile.inc new file mode 100644 index 0000000..343c7db --- /dev/null +++ b/src/mainboard/google/volteer/variants/eldrid/Makefile.inc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + +romstage-y += memory.c + +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/eldrid/gpio.c b/src/mainboard/google/volteer/variants/eldrid/gpio.c new file mode 100644 index 0000000..0ff354e --- /dev/null +++ b/src/mainboard/google/volteer/variants/eldrid/gpio.c @@ -0,0 +1,298 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */ + PAD_CFG_GPO(GPP_A7, 1, DEEP), + /* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_A8, 0, DEEP), + /* A10 : I2S2_RXD ==> EN_SPKR_PA */ + PAD_CFG_GPO(GPP_A10, 1, DEEP), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), + /* A15 : USB_OC2# ==> NC */ + PAD_NC(GPP_A15, NONE), + /* A16 : USB_OC3# ==> USB_C0_OC_ODL */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A18 : DDSP_HPDB ==> NC */ + PAD_NC(GPP_A18, NONE), + /* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), + /* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */ + PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_A21, 1, DEEP), + /* A22 : DDPC_CTRLDATA ==> NC */ + PAD_NC(GPP_A22, NONE), + /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ + PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), + + /* B2 : VRALERT# ==> EN_PP3300_SSD */ + PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), + /* B3 : CPU_GP2 ==> NC */ + PAD_NC(GPP_B3, NONE), + /* B5 : ISH_I2C0_CVF_SDA ==> NC */ + PAD_NC(GPP_B5, NONE), + /* B6 : ISH_I2C0_CVF_SCL ==> NC */ + PAD_NC(GPP_B6, NONE), + /* B7 : ISH_12C1_SDA ==> ISH_I2C0_SENSOR_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + /* B8 : ISH_I2C1_SCL ==> ISH_I2C0_SENSOR_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C5 : SML0ALERT# ==> GPP_C5_BOOT_STRAP_0 */ + PAD_CFG_GPI(GPP_C5, NONE, DEEP), + /* C7 : SML1DATA ==> NC */ + PAD_NC(GPP_C7, NONE), + /* C10 : UART0_RTS# ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C10, 0, DEEP), + /* C13 : UART1_TXD ==> NC */ + PAD_NC(GPP_C13, NONE), + /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* C20 : UART2_RXD ==> FPMCU_INT_L */ + /* APIC interrupt conflict, so used GPI_INT; see b/147500717 */ + PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + + /* D1 : ISH_GP1 ==> NC */ + PAD_NC(GPP_D1, NONE), + /* D2 : ISH_GP2 ==> NC */ + PAD_NC(GPP_D2, NONE), + /* D3 : ISH_GP3 ==> NC */ + PAD_NC(GPP_D3, NONE), + /* D4 : IMGCLKOUT0 ==> NC */ + PAD_NC(GPP_D4, NONE), + /* D6 : SRCCLKREQ1# ==> WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* D12 : ISH_SPI_MOSI ==> PCH_GSPI2_CVF_MOSI_STRAP */ + PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1), + /* D13 : ISH_UART0_RXD ==> NC */ + PAD_NC(GPP_D13, NONE), + /* D14 : ISH_UART0_TXD ==> NC */ + PAD_NC(GPP_D14, NONE), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + /* D17 : ISH_GP4 ==> EN_FCAM_PWR */ + PAD_CFG_GPO(GPP_D17, 1, DEEP), + /* D18 : ISH_GP5 ==> NC */ + PAD_NC(GPP_D18, NONE), + + /* E0 : SATAXPCIE0 ==> USB_C1_RT_PWR_EN */ + PAD_CFG_GPO(GPP_E0, 1, DEEP), + /* E1 : SPI1_IO2 ==> NC */ + PAD_NC(GPP_E1, NONE), + /* E2 : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E2, NONE, DEEP), + /* E3 : CPU_GP0 ==> USI_REPORT_EN */ + PAD_CFG_GPO(GPP_E3, 1, DEEP), + /* E4 : SATA_DEVSLP0 ==> M2_SSD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E4, NONE, DEEP), + /* E6 : THC0_SPI1_RST# ==> GPP_E6_STRAP */ + PAD_CFG_GPI(GPP_E6, NONE, DEEP), + /* E7 : CPU_GP1 ==> USI_INT */ + PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE), + /* E8 : SPI1_CS1# ==> SLP_S0IX */ + PAD_CFG_GPO(GPP_E8, 0, DEEP), + /* E10 : SPI1_CS# ==> USB_C0_AUXP_DC */ + PAD_CFG_GPO(GPP_E10, 1, DEEP), + /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E11, NONE, DEEP), + /* E13 : SPI1_MOSI_IO0 ==> USB_C0_AUXN_DC */ + PAD_CFG_GPO(GPP_E13, 1, DEEP), + /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT), + /* E16 : ISH_GP7 ==> NC */ + PAD_NC(GPP_E16, NONE), + /* E17 : THC0_SPI1_INT# ==> NC */ + PAD_NC(GPP_E17, NONE), + /* E20 : DDP2_CTRLCLK ==> NC */ + PAD_NC(GPP_E20, NONE), + /* E21 : DDP2_CTRLDATA ==> NC */ + PAD_NC(GPP_E21, NONE), + /* E22 : DDPA_CTRLCLK ==> USB_C1_AUXP_DC: Retimer FW drives this pin */ + PAD_CFG_GPO(GPP_E22, 1, DEEP), + /* E23 : DDPA_CTRLDATA ==> USB_C1_AUXN_DC: Retimer FW drives this pin */ + PAD_CFG_GPO(GPP_E23, 1, DEEP), + + /* F6 : CNV_PA_BLANKING ==> NC */ + PAD_NC(GPP_F6, NONE), + /* F7 : GPPF7_STRAP ==> GPP_F7_STRAP */ + PAD_CFG_GPI(GPP_F7, NONE, DEEP), + /* F8 : I2S_MCLK2_INOUT ==> HP_INT_L */ + PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, EDGE_BOTH), + /* F10 : GPPF10_STRAP ==> GPP_F10_STRAP */ + PAD_CFG_GPI(GPP_F10, NONE, DEEP), + /* F11 : THC1_SPI2_CLK ==> NC */ + PAD_NC(GPP_F11, NONE), + /* F12 : GSXDOUT ==> NC */ + PAD_NC(GPP_F12, NONE), + /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ + PAD_CFG_GPO(GPP_F13, 1, DEEP), + /* F14 : GSXDIN ==> NC */ + PAD_NC(GPP_F14, NONE), + /* F15 : GSXSRESET# ==> NC */ + PAD_NC(GPP_F15, NONE), + /* F16 : GSXCLK ==> NC */ + PAD_NC(GPP_F16, NONE), + /* F17 : THC1_SPI2_RST# ==> NC */ + PAD_NC(GPP_F17, NONE), + /* F18 : THC1_SPI2_INT# ==> NC */ + PAD_NC(GPP_F18, NONE), + /* F19 : SRCCLKREQ6# ==> NC */ + PAD_NC(GPP_F19, NONE), + + /* H0 : GPPH0_BOOT_STRAP1 */ + PAD_CFG_GPI(GPP_H0, NONE, DEEP), + /* H1 : GPPH1_BOOT_STRAP2 */ + PAD_CFG_GPI(GPP_H1, NONE, DEEP), + /* H2 : GPPH2_BOOT_STRAP3 */ + PAD_CFG_GPI(GPP_H2, NONE, DEEP), + /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), + /* H4 : I2C2_SDA ==> NC */ + PAD_NC(GPP_H4, NONE), + /* H5 : I2C2_SCL ==> NC */ + PAD_NC(GPP_H5, NONE), + /* H6 : I2C3_SDA ==> NC */ + PAD_NC(GPP_H6, NONE), + /* H7 : I2C3_SCL ==> NC */ + PAD_NC(GPP_H7, NONE), + /* H8 : I2C4_SDA ==> NC */ + PAD_NC(GPP_H8, NONE), + /* H9 : I2C4_SCL ==> NC */ + PAD_NC(GPP_H9, NONE), + /* H10 : SRCCLKREQ4# ==> NC */ + PAD_NC(GPP_H10, NONE), + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H11, 1, DEEP), + /* H12 : M2_SKT2_CFG0 ==> NC */ + PAD_NC(GPP_H12, NONE), + /* H13 : M2_SKT2_CFG1 # ==> NC */ + PAD_NC(GPP_H13, NONE), + /* H14 : M2_SKT2_CFG2 # ==> NC */ + PAD_NC(GPP_H14, NONE), + /* H15 : M2_SKT2_CFG3 # ==> NC */ + PAD_NC(GPP_H15, NONE), + /* H16 : DDPB_CTRLCLK ==> NC */ + PAD_NC(GPP_H16, NONE), + /* H17 : DDPB_CTRLDATA ==> NC */ + PAD_NC(GPP_H17, NONE), + /* H19 : TIME_SYNC0 ==> NC */ + PAD_NC(GPP_H19, NONE), + /* H20 : IMGCLKOUT1 ==> NC */ + PAD_NC(GPP_H20, NONE), + /* H21 : IMGCLKOUT2 ==> NC */ + PAD_NC(GPP_H21, NONE), + /* H22 : IMGCLKOUT3 ==> NC */ + PAD_NC(GPP_H22, NONE), + + /* R0 : HDA_BCLK ==> I2S0_HP_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* R1 : HDA_SYNC ==> I2S0_HP_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), + /* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + /* R5 : HDA_SDI1 ==> NC */ + PAD_NC(GPP_R5, NONE), + /* R6 : I2S1_TXD ==> I2S1_PCH_TX_SPKR_RX_R */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + /* R7 : I2S1_SFRM ==> I2S1_SPKR_SFRM_R */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + + /* S0 : SNDW0_CLK ==> SNDW0_HP_CLK_R */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), + /* S1 : SNDW0_DATA ==> SNDW0_HP_DATA_R */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), + /* S2 : SNDW1_CLK ==> NC */ + PAD_NC(GPP_S2, NONE), + /* S3 : SNDW1_DATA ==> NC */ + PAD_NC(GPP_S3, NONE), + /* S4 : SNDW2_CLK ==> PCH_DMIC_CAM_SCL_R */ + PAD_CFG_NF(GPP_S4, NONE, DEEP, NF1), + /* S5 : SNDW2_DATA ==> PCH_DMIC_CAM_SDA_R */ + PAD_CFG_NF(GPP_S5, NONE, DEEP, NF1), + /* S6 : SNDW3_CLK ==> NC */ + PAD_NC(GPP_S6, NONE), + /* S7 : SNDW3_DATA ==> NC */ + PAD_NC(GPP_S7, NONE), + + /* GPD9: SLP_WLAN# ==> SLP_WLAN_L */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_A17, NONE, DEEP), + + /* B11 : PMCALERT# ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_GPI(GPP_B18, NONE, DEEP), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + + /* E12 : SPI1_MISO_IO1 ==> NC */ + PAD_NC(GPP_E12, NONE), + + /* F11 : THC1_SPI2_CLK ==> NC */ + PAD_NC(GPP_F11, NONE), + + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H11, 1, DEEP), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/volteer/variants/eldrid/memory.c b/src/mainboard/google/volteer/variants/eldrid/memory.c new file mode 100644 index 0000000..3291d5d --- /dev/null +++ b/src/mainboard/google/volteer/variants/eldrid/memory.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <gpio.h> + +static const struct mb_ddr4_cfg eldrid_memcfg = { +}; + +static const struct ddr_memory_cfg baseboard_memcfg = { + .mem_type = MEMTYPE_DDR4, + .ddr4_cfg = &eldrid_memcfg +}; + +const struct ddr_memory_cfg *variant_memory_params(void) +{ + return &baseboard_memcfg; +} + +int variant_memory_sku(void) +{ + gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_3, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_0, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} diff --git a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb index 89026b8..99d883b 100644 --- a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb +++ b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb @@ -3,8 +3,194 @@ register "TcssAuxOri" = "1" register "IomTypeCPortPadCfg[0]" = "0x090E000A" register "IomTypeCPortPadCfg[1]" = "0x090E000D" - + register "SaGv" = "SaGv_Disabled" + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C2 | WLAN, SAR0 | + #| I2C3 | Camera, SAR1 | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 163, + .scl_hcnt = 75, + .sda_hold = 36, + }, + }, + }" device domain 0 on + device pci 04.0 off + end + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F8)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + probe AUDIO MAX98357_ALC5682I_I2S + probe AUDIO MAX98373_ALC5682I_I2S + end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "0" + register "imon_slot_no" = "1" + register "uid" = "0" + register "desc" = ""Right Speaker Amp"" + register "name" = ""MAXR"" + device i2c 31 on + probe AUDIO MAX98373_ALC5682I_I2S + end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "2" + register "imon_slot_no" = "3" + register "uid" = "1" + register "desc" = ""Left Speaker Amp"" + register "name" = ""MAXL"" + device i2c 32 on + probe AUDIO MAX98373_ALC5682I_I2S + end + end + end + device pci 15.1 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "generic.enable_delay_ms" = "12" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 14 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN90FC"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "generic.reset_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end + end # I2C1 0xA0E9 + device pci 19.1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" + register "wake" = "GPE0_DW2_15" + register "probed" = "1" + device i2c 15 on end + end + end # I2C5 0xA0C6 + device pci 1f.3 on + chip drivers/generic/max98357a + register "hid" = ""MX98357A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" + register "sdmode_delay" = "5" + device generic 0 on + probe AUDIO MAX98357_ALC5682I_I2S + end + end + chip drivers/intel/soundwire + device generic 0 on + probe AUDIO MAX98373_ALC5682_SNDW + chip drivers/soundwire/alc5682 + # SoundWire Link 0 ID 1 + register "desc" = ""Headset Codec"" + device generic 0.1 on end + end + chip drivers/soundwire/max98373 + # SoundWire Link 1 ID 3 + register "desc" = ""Left Speaker Amp"" + device generic 1.3 on end + end + chip drivers/soundwire/max98373 + # SoundWire Link 1 ID 7 + register "desc" = ""Right Speaker Amp"" + device generic 1.7 on end + end + end + end + end + device pci 1f.2 hidden + # The pmc_mux chip driver is a placeholder for the + # PMC.MUX device in the ACPI hierarchy. + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "9" + register "usb3_port_number" = "1" + # SBU & HSL follow CC + device generic 0 on end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "4" + register "usb3_port_number" = "2" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 1 on + probe DB_USB USB4_GEN2 + probe DB_USB USB3_ACTIVE + probe DB_USB USB4_GEN3 + probe DB_USB USB3_NO_A + end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "4" + register "usb3_port_number" = "2" + # SBU & HSL follow CC + device generic 1 on + probe DB_USB USB3_PASSIVE + end + end + end + end + end # PMC end - end -- To view, visit https://review.coreboot.org/c/coreboot/+/44632 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c7b30093a8d85bac5aba5b83768af5eb36c4f70 Gerrit-Change-Number: 44632 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Chen <nick_xr_chen(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

10 64

Change in coreboot[master]: 3rdparty: Add submodule intel-sec-tools
by Philipp Deppenwiese (Code Review) 09 Sep '20

09 Sep '20

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45170 ) Change subject: 3rdparty: Add submodule intel-sec-tools ...................................................................... 3rdparty: Add submodule intel-sec-tools Project: https://github.com/9elements/converged-security-suite License: BSD-3 Tooling for Intel platform security features Change-Id: I7421b30eb38e64cf6b77b7e1c485c5700728997b Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- M .gitmodules A 3rdparty/intel-sec-tools 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/45170/1 diff --git a/.gitmodules b/.gitmodules index bc4a6eb..8b44384 100644 --- a/.gitmodules +++ b/.gitmodules @@ -51,3 +51,6 @@ url = ../qc_blobs.git update = none ignore = dirty +[submodule "3rdparty/intel-sec-tools"] + path = 3rdparty/intel-sec-tools + url = ../9esec-security-tooling.git diff --git a/3rdparty/intel-sec-tools b/3rdparty/intel-sec-tools new file mode 160000 index 0000000..a86ff5d --- /dev/null +++ b/3rdparty/intel-sec-tools @@ -0,0 +1 @@ +Subproject commit a86ff5d400983d685d4389c07433452c7a503300 -- To view, visit https://review.coreboot.org/c/coreboot/+/45170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7421b30eb38e64cf6b77b7e1c485c5700728997b Gerrit-Change-Number: 45170 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: soc/intel/cannonlake: Add PCIe ports on PCH-H
by Patrick Rudolph (Code Review) 09 Sep '20

09 Sep '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45065 ) Change subject: soc/intel/cannonlake: Add PCIe ports on PCH-H ...................................................................... soc/intel/cannonlake: Add PCIe ports on PCH-H Change-Id: I277f592cd8d2c86a9c7ba4b34d3f703f7d593582 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/cannonlake/acpi/pci_irqs.asl M src/soc/intel/cannonlake/acpi/pcie.asl M src/soc/intel/cannonlake/include/soc/irq.h 3 files changed, 158 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/45065/1 diff --git a/src/soc/intel/cannonlake/acpi/pci_irqs.asl b/src/soc/intel/cannonlake/acpi/pci_irqs.asl index 7439a0e..d70f5c7 100644 --- a/src/soc/intel/cannonlake/acpi/pci_irqs.asl +++ b/src/soc/intel/cannonlake/acpi/pci_irqs.asl @@ -24,6 +24,11 @@ Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ }, Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ }, Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ }, + /* PCI Express Port 17-24 */ + Package(){0x001BFFFF, 0, 0, PCIE_17_IRQ }, + Package(){0x001BFFFF, 1, 0, PCIE_18_IRQ }, + Package(){0x001BFFFF, 2, 0, PCIE_19_IRQ }, + Package(){0x001BFFFF, 3, 0, PCIE_20_IRQ }, /* eMMC */ Package(){0x001AFFFF, 0, 0, eMMC_IRQ }, /* SerialIo */ @@ -88,6 +93,11 @@ Package () { 0x001CFFFF, 1, 0, 10 }, Package () { 0x001CFFFF, 2, 0, 11 }, Package () { 0x001CFFFF, 3, 0, 11 }, + /* D27: PCI Express Port 17-24 */ + Package () { 0x001BFFFF, 0, 0, 11 }, + Package () { 0x001BFFFF, 1, 0, 10 }, + Package () { 0x001BFFFF, 2, 0, 11 }, + Package () { 0x001BFFFF, 3, 0, 11 }, /* D25: Can't use PIC*/ /* D23 */ Package () { 0x0017FFFF, 0, 0, 11 }, diff --git a/src/soc/intel/cannonlake/acpi/pcie.asl b/src/soc/intel/cannonlake/acpi/pcie.asl index 9c0933f..0371f89 100644 --- a/src/soc/intel/cannonlake/acpi/pcie.asl +++ b/src/soc/intel/cannonlake/acpi/pcie.asl @@ -54,7 +54,7 @@ Switch (ToInteger (Arg0)) { - Case (Package () { 1, 5, 9, 13 }) { + Case (Package () { 1, 5, 9, 13, 17, 21 }) { If (PICM) { Return (IQAA) } Else { @@ -62,7 +62,7 @@ } } - Case (Package () { 2, 6, 10, 14 }) { + Case (Package () { 2, 6, 10, 14, 18, 22 }) { If (PICM) { Return (IQBA) } Else { @@ -70,7 +70,7 @@ } } - Case (Package () { 3, 7, 11, 15 }) { + Case (Package () { 3, 7, 11, 15, 19, 23 }) { If (PICM) { Return (IQCA) } Else { @@ -78,7 +78,7 @@ } } - Case (Package () { 4, 8, 12, 16 }) { + Case (Package () { 4, 8, 12, 16, 20, 24 }) { If (PICM) { Return (IQDA) } Else { @@ -367,3 +367,139 @@ Return (IRQM (RPPN)) } } + +Device (RP17) +{ + Name (_ADR, 0x001B0000) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP18) +{ + Name (_ADR, 0x001B0001) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP19) +{ + Name (_ADR, 0x001B0002) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP20) +{ + Name (_ADR, 0x001B0003) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP21) +{ + Name (_ADR, 0x001B0004) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP22) +{ + Name (_ADR, 0x001B0005) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP23) +{ + Name (_ADR, 0x001B0006) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP24) +{ + Name (_ADR, 0x001B0007) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} diff --git a/src/soc/intel/cannonlake/include/soc/irq.h b/src/soc/intel/cannonlake/include/soc/irq.h index 05d4025..1aa6036 100644 --- a/src/soc/intel/cannonlake/include/soc/irq.h +++ b/src/soc/intel/cannonlake/include/soc/irq.h @@ -62,6 +62,14 @@ #define PCIE_10_IRQ 17 #define PCIE_11_IRQ 18 #define PCIE_12_IRQ 19 +#define PCIE_14_IRQ 16 +#define PCIE_15_IRQ 17 +#define PCIE_16_IRQ 18 +#define PCIE_17_IRQ 19 +#define PCIE_18_IRQ 16 +#define PCIE_19_IRQ 17 +#define PCIE_20_IRQ 18 +#define PCIE_21_IRQ 19 #define SATA_IRQ 16 -- To view, visit https://review.coreboot.org/c/coreboot/+/45065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I277f592cd8d2c86a9c7ba4b34d3f703f7d593582 Gerrit-Change-Number: 45065 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: geminilake: Factor out MAX_CPUS value
by Angel Pons (Code Review) 09 Sep '20

09 Sep '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45142 ) Change subject: geminilake: Factor out MAX_CPUS value ...................................................................... geminilake: Factor out MAX_CPUS value Both Gemini Lake boards in the tree use the same value. Change-Id: Ib6bd05206026736fd7e3d44b49e4d8ba217c2708 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/octopus/Kconfig M src/mainboard/intel/glkrvp/Kconfig M src/soc/intel/apollolake/Kconfig 3 files changed, 4 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/45142/1 diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index 4c0cdff..b9c6a1b 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -97,10 +97,6 @@ string default "Google_Octopus" -config MAX_CPUS - int - default 4 - config UART_FOR_CONSOLE int default 2 diff --git a/src/mainboard/intel/glkrvp/Kconfig b/src/mainboard/intel/glkrvp/Kconfig index 86920ca..7b1b564 100644 --- a/src/mainboard/intel/glkrvp/Kconfig +++ b/src/mainboard/intel/glkrvp/Kconfig @@ -68,10 +68,6 @@ string default "Intel_Glkrvp" if BOARD_INTEL_GLKRVP -config MAX_CPUS - int - default 4 - config UART_FOR_CONSOLE int default 2 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 7467f28..08710d2 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -107,6 +107,10 @@ select INTEL_GMA_SWSMISCI select HAVE_ASAN_IN_ROMSTAGE +config MAX_CPUS + int + default 4 if SOC_INTEL_GEMINILAKE + config CHROMEOS select CHROMEOS_RAMOOPS_DYNAMIC -- To view, visit https://review.coreboot.org/c/coreboot/+/45142 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6bd05206026736fd7e3d44b49e4d8ba217c2708 Gerrit-Change-Number: 45142 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: soc/ti/am335x: Fix MLO build
by Sam Lewis (Code Review) 09 Sep '20

09 Sep '20

Sam Lewis has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44381 ) Change subject: soc/ti/am335x: Fix MLO build ...................................................................... soc/ti/am335x: Fix MLO build Allows the AM335X to boot from the coreboot generated MLO by: - Fixing the load address in the MLO header to be the start of SRAM - Fixing the way that the bootblock size is calculated (which is embedded into the MLO so that the MLO knows how much to load into SRAM). The previous method relied on parsing cbfstool output - the output has changed format since this was originally written so this no longer works. Directly using the filesize of the built binary is probably a more stable way of doing this. As part of this, the start addresses of SRAM and DRAM were fixed to be consistent with the datasheet. TEST: Booted Beaglebone Black from MLO placed at offset 0x00 on an SD card Change-Id: I514d7cda65ddcbf27e78286dc6857c9e81ce6f9e Signed-off-by: Sam Lewis <sam.vr.lewis(a)gmail.com> --- M src/soc/ti/am335x/Makefile.inc M src/soc/ti/am335x/bootblock_media.c M src/soc/ti/am335x/header.c M src/soc/ti/am335x/memlayout.ld 4 files changed, 9 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/44381/1 diff --git a/src/soc/ti/am335x/Makefile.inc b/src/soc/ti/am335x/Makefile.inc index dd9e093..06ac1ee 100644 --- a/src/soc/ti/am335x/Makefile.inc +++ b/src/soc/ti/am335x/Makefile.inc @@ -29,17 +29,13 @@ header_ld := $(call src-to-obj,omap-header,$(dir)/header.ld) get_header_size= \ - $(eval omap_header_info=$(shell $(CBFSTOOL) $(1) print | grep $(2))) \ - $(shell echo $$(($(word 2,$(omap_header_info)) + \ - $(word 4,$(omap_header_info))))) + $(shell echo $$(wc -c < $(objcbfs)/bootblock.bin)) -$(obj)/omap-header.bin: $$(omap-header-objs) $(obj)/coreboot.rom +$(obj)/omap-header.bin: $$(omap-header-objs) $(objcbfs)/bootblock.bin @printf " CC $(subst $(obj)/,,$(@))\n" $(CC_omap-header) -nostdlib -nostartfiles -static -include $(obj)/config.h \ -Wl,--defsym,header_load_size=$(strip \ - $(call get_header_size,$(obj)/coreboot.rom, \ - $(CONFIG_CBFS_PREFIX)/romstage \ - ) \ + $(call get_header_size,$(obj)/coreboot.rom) \ ) \ -o $@.tmp $< -T $(header_ld) $(OBJCOPY_omap-header) --only-section=".header" -O binary $@.tmp $@ diff --git a/src/soc/ti/am335x/bootblock_media.c b/src/soc/ti/am335x/bootblock_media.c index 050e0b7..1c65c38 100644 --- a/src/soc/ti/am335x/bootblock_media.c +++ b/src/soc/ti/am335x/bootblock_media.c @@ -5,7 +5,7 @@ /* FIXME: No idea how big the internal SRAM actually is. */ static const struct mem_region_device boot_dev = - MEM_REGION_DEV_RO_INIT(_dram, CONFIG_ROM_SIZE); + MEM_REGION_DEV_RO_INIT(_sram, CONFIG_ROM_SIZE); const struct region_device *boot_device_ro(void) { diff --git a/src/soc/ti/am335x/header.c b/src/soc/ti/am335x/header.c index 9edfdd0..c0a7589 100644 --- a/src/soc/ti/am335x/header.c +++ b/src/soc/ti/am335x/header.c @@ -52,6 +52,6 @@ }, .image_header = { .size = (uintptr_t)&header_load_size, - .destination = (uintptr_t)_dram + .destination = (uintptr_t)_sram } }; diff --git a/src/soc/ti/am335x/memlayout.ld b/src/soc/ti/am335x/memlayout.ld index 78528e6..991e401 100644 --- a/src/soc/ti/am335x/memlayout.ld +++ b/src/soc/ti/am335x/memlayout.ld @@ -6,11 +6,14 @@ SECTIONS { - DRAM_START(0x40000000) + SRAM_START(0x402f0400) BOOTBLOCK(0x402f0400, 20K) ROMSTAGE(0x402f5400, 88K) FMAP_CACHE(0x4030b400, 2K) STACK(0x4030be00, 4K) + SRAM_END(0x40310000) + DRAM_START(0x80000000) + RAMSTAGE(0x80200000, 192K) /* TODO: Implement MMU support and move TTB to a better location. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44381 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I514d7cda65ddcbf27e78286dc6857c9e81ce6f9e Gerrit-Change-Number: 44381 Gerrit-PatchSet: 1 Gerrit-Owner: Sam Lewis <sam.vr.lewis(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: mb/ti/beaglebone: Init UART in early init
by Sam Lewis (Code Review) 09 Sep '20

09 Sep '20

Sam Lewis has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44380 ) Change subject: mb/ti/beaglebone: Init UART in early init ...................................................................... mb/ti/beaglebone: Init UART in early init The console is initialized before mainboard_init, so the peripheral should be initialized in bootblock_mainboard_early_init rather than bootblock_mainboard_init. Change-Id: I9f4ba29798eb0b1efea76f5ade4a234fb35a2f83 Signed-off-by: Sam Lewis <sam.vr.lewis(a)gmail.com> --- M src/mainboard/ti/beaglebone-black/bootblock.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/44380/1 diff --git a/src/mainboard/ti/beaglebone-black/bootblock.c b/src/mainboard/ti/beaglebone-black/bootblock.c index ca1a390..b7b0ee9 100644 --- a/src/mainboard/ti/beaglebone-black/bootblock.c +++ b/src/mainboard/ti/beaglebone-black/bootblock.c @@ -9,7 +9,7 @@ #include "leds.h" -void bootblock_mainboard_init(void) +void bootblock_mainboard_early_init(void) { write32(&am335x_cm_wkup->wkup_gpio0, CM_ST_SW_WKUP | CM_FCLK_EN); write32(&am335x_cm_per->gpio1, CM_ST_SW_WKUP | CM_FCLK_EN); -- To view, visit https://review.coreboot.org/c/coreboot/+/44380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f4ba29798eb0b1efea76f5ade4a234fb35a2f83 Gerrit-Change-Number: 44380 Gerrit-PatchSet: 1 Gerrit-Owner: Sam Lewis <sam.vr.lewis(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/uart/Kconfig: Drop unused symbols
by Angel Pons (Code Review) 09 Sep '20

09 Sep '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45049 ) Change subject: soc/intel/common/block/uart/Kconfig: Drop unused symbols ...................................................................... soc/intel/common/block/uart/Kconfig: Drop unused symbols They are not referenced anywhere. Change-Id: Iff2d3b0063da5796e0bff1ada08b0a544c3f9a5a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/common/block/uart/Kconfig 1 file changed, 0 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/45049/1 diff --git a/src/soc/intel/common/block/uart/Kconfig b/src/soc/intel/common/block/uart/Kconfig index e731465..7d30c41 100644 --- a/src/soc/intel/common/block/uart/Kconfig +++ b/src/soc/intel/common/block/uart/Kconfig @@ -4,18 +4,6 @@ help Intel Processor common UART support -config SOC_INTEL_COMMON_BLOCK_UART_LPSS_CLK_M_VAL - depends on SOC_INTEL_COMMON_BLOCK_UART - hex - help - Clock m-divisor value for m/n divider - -config SOC_INTEL_COMMON_BLOCK_UART_LPSS_CLK_N_VAL - depends on SOC_INTEL_COMMON_BLOCK_UART - hex - help - Clock m-divisor value for m/n divider - config INTEL_LPSS_UART_FOR_CONSOLE bool depends on SOC_INTEL_COMMON_BLOCK_UART -- To view, visit https://review.coreboot.org/c/coreboot/+/45049 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff2d3b0063da5796e0bff1ada08b0a544c3f9a5a Gerrit-Change-Number: 45049 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/mb/google: Update dalboz/trembyle template
by Rob Barnes (Code Review) 09 Sep '20

09 Sep '20

Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44947 ) Change subject: util/mb/google: Update dalboz/trembyle template ...................................................................... util/mb/google: Update dalboz/trembyle template Fix relative path to spd folder. BUG=b:167175547 TEST=None Change-Id: Iae88ff9c8255f60544312f0eeadf1ce617437baf Signed-off-by: Rob Barnes <robbarnes(a)google.com> --- M util/mainboard/google/dalboz/template/Makefile.inc M util/mainboard/google/trembyle/template/Makefile.inc 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/44947/1 diff --git a/util/mainboard/google/dalboz/template/Makefile.inc b/util/mainboard/google/dalboz/template/Makefile.inc index 9dc5159..295acd2 100644 --- a/util/mainboard/google/dalboz/template/Makefile.inc +++ b/util/mainboard/google/dalboz/template/Makefile.inc @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-or-later -subdirs-y += ../baseboard/spd +subdirs-y += ./spd diff --git a/util/mainboard/google/trembyle/template/Makefile.inc b/util/mainboard/google/trembyle/template/Makefile.inc index 9dc5159..295acd2 100644 --- a/util/mainboard/google/trembyle/template/Makefile.inc +++ b/util/mainboard/google/trembyle/template/Makefile.inc @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-or-later -subdirs-y += ../baseboard/spd +subdirs-y += ./spd -- To view, visit https://review.coreboot.org/c/coreboot/+/44947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae88ff9c8255f60544312f0eeadf1ce617437baf Gerrit-Change-Number: 44947 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/spd_tools: Support comments in mem_parts_used
by Rob Barnes (Code Review) 09 Sep '20

09 Sep '20

Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44950 ) Change subject: util/spd_tools: Support comments in mem_parts_used ...................................................................... util/spd_tools: Support comments in mem_parts_used Allow comments prefixed with '#' in mem_parts_used csv file. BUG=None TEST=Run gen_part_id with mem_parts_used file containing comments Change-Id: Ia9e274d45aa06dea7a3a5f8cd1c8ee2b23398876 Signed-off-by: Rob Barnes <robbarnes(a)google.com> --- M src/mainboard/google/zork/variants/berknip/spd/mem_parts_used.txt M src/mainboard/google/zork/variants/dalboz/spd/mem_parts_used.txt M src/mainboard/google/zork/variants/dirinboz/spd/mem_parts_used.txt M src/mainboard/google/zork/variants/ezkinil/spd/mem_parts_used.txt M src/mainboard/google/zork/variants/morphius/spd/mem_parts_used.txt M src/mainboard/google/zork/variants/trembyle/spd/mem_parts_used.txt M src/mainboard/google/zork/variants/vilboz/spd/mem_parts_used.txt M src/mainboard/google/zork/variants/woomax/spd/mem_parts_used.txt M util/spd_tools/ddr4/gen_part_id.go 9 files changed, 73 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/44950/1 diff --git a/src/mainboard/google/zork/variants/berknip/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/berknip/spd/mem_parts_used.txt index 69d65d2..a973238 100644 --- a/src/mainboard/google/zork/variants/berknip/spd/mem_parts_used.txt +++ b/src/mainboard/google/zork/variants/berknip/spd/mem_parts_used.txt @@ -1,3 +1,12 @@ +# This is a CSV file containg a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Each part must also be listed in util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/ddr4. +# See util/spd_tools/ddr4/README.md for more details and instructions. + +# Part Name, Fixed ID (optional) K4A8G165WC-BCTD, 0 MT40A512M16TB-062E:J, 2 H5AN8G6NDJR-XNC, 3 diff --git a/src/mainboard/google/zork/variants/dalboz/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/dalboz/spd/mem_parts_used.txt index f254851..f24e86b 100644 --- a/src/mainboard/google/zork/variants/dalboz/spd/mem_parts_used.txt +++ b/src/mainboard/google/zork/variants/dalboz/spd/mem_parts_used.txt @@ -1,3 +1,12 @@ +# This is a CSV file containg a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Each part must also be listed in util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/ddr4. +# See util/spd_tools/ddr4/README.md for more details and instructions. + +# Part Name, Fixed ID (optional) HMA851S6CJR6N-VK, 0 H5ANAG6NCMR-VKC, 1 K4A8G165WC-BCTD, 2 diff --git a/src/mainboard/google/zork/variants/dirinboz/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/dirinboz/spd/mem_parts_used.txt index 1d19915..5833b61 100644 --- a/src/mainboard/google/zork/variants/dirinboz/spd/mem_parts_used.txt +++ b/src/mainboard/google/zork/variants/dirinboz/spd/mem_parts_used.txt @@ -1,3 +1,12 @@ +# This is a CSV file containg a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Each part must also be listed in util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/ddr4. +# See util/spd_tools/ddr4/README.md for more details and instructions. + +# Part Name, Fixed ID (optional) K4A8G165WC-BCTD, 2 K4A8G165WC-BCWE, 4 H5AN8G6NDJR-XNC, 5 diff --git a/src/mainboard/google/zork/variants/ezkinil/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/ezkinil/spd/mem_parts_used.txt index 27fb51b..92d5fdc 100644 --- a/src/mainboard/google/zork/variants/ezkinil/spd/mem_parts_used.txt +++ b/src/mainboard/google/zork/variants/ezkinil/spd/mem_parts_used.txt @@ -1,3 +1,12 @@ +# This is a CSV file containg a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Each part must also be listed in util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/ddr4. +# See util/spd_tools/ddr4/README.md for more details and instructions. + +# Part Name, Fixed ID (optional) H5AN8G6NCJR-VKC,0 MT40A512M16TB-062E:J,2 MT40A1G16KNR-075:E, 3 diff --git a/src/mainboard/google/zork/variants/morphius/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/morphius/spd/mem_parts_used.txt index b56a6b4..cb9cfff 100644 --- a/src/mainboard/google/zork/variants/morphius/spd/mem_parts_used.txt +++ b/src/mainboard/google/zork/variants/morphius/spd/mem_parts_used.txt @@ -1,3 +1,12 @@ +# This is a CSV file containg a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Each part must also be listed in util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/ddr4. +# See util/spd_tools/ddr4/README.md for more details and instructions. + +# Part Name, Fixed ID (optional) K4AAG165WA-BCWE, 0 MT40A512M16TB-062E:J, 2 MT40A1G16KD-062E:E, 3 diff --git a/src/mainboard/google/zork/variants/trembyle/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/trembyle/spd/mem_parts_used.txt index f8a7229..bb33a61 100644 --- a/src/mainboard/google/zork/variants/trembyle/spd/mem_parts_used.txt +++ b/src/mainboard/google/zork/variants/trembyle/spd/mem_parts_used.txt @@ -1,2 +1,11 @@ +# This is a CSV file containg a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Each part must also be listed in util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/ddr4. +# See util/spd_tools/ddr4/README.md for more details and instructions. + +# Part Name, Fixed ID (optional) H5AN8G6NCJR-VKC, 0 H5ANAG6NCMR-VKC, 1 diff --git a/src/mainboard/google/zork/variants/vilboz/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/vilboz/spd/mem_parts_used.txt index ac7b794b..49c13cb 100644 --- a/src/mainboard/google/zork/variants/vilboz/spd/mem_parts_used.txt +++ b/src/mainboard/google/zork/variants/vilboz/spd/mem_parts_used.txt @@ -1,3 +1,12 @@ +# This is a CSV file containg a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Each part must also be listed in util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/ddr4. +# See util/spd_tools/ddr4/README.md for more details and instructions. + +# Part Name, Fixed ID (optional) H5AN8G6NCJR-VKC, 0 H5ANAG6NCMR-VKC, 1 K4A8G165WC-BCWE, 2 diff --git a/src/mainboard/google/zork/variants/woomax/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/woomax/spd/mem_parts_used.txt index fcee866..61a580a 100644 --- a/src/mainboard/google/zork/variants/woomax/spd/mem_parts_used.txt +++ b/src/mainboard/google/zork/variants/woomax/spd/mem_parts_used.txt @@ -1,3 +1,12 @@ +# This is a CSV file containg a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Each part must also be listed in util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/ddr4. +# See util/spd_tools/ddr4/README.md for more details and instructions. + +# Part Name, Fixed ID (optional) H5AN8G6NCJR-XNC, 1 MT40A512M16TB-062E:J, 8 H5AN8G6NCJR-XNC, 9 diff --git a/util/spd_tools/ddr4/gen_part_id.go b/util/spd_tools/ddr4/gen_part_id.go index c0098ab..135d5c8 100644 --- a/util/spd_tools/ddr4/gen_part_id.go +++ b/util/spd_tools/ddr4/gen_part_id.go @@ -68,6 +68,7 @@ r := csv.NewReader(f) r.FieldsPerRecord = -1 // Allow variable length records r.TrimLeadingSpace = true + r.Comment = '#' parts := []usedPart{} -- To view, visit https://review.coreboot.org/c/coreboot/+/44950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9e274d45aa06dea7a3a5f8cd1c8ee2b23398876 Gerrit-Change-Number: 44950 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newchange

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