coreboot-gerrit September 2020

coreboot-gerrit@coreboot.org

1 participants
2628 discussions

Change in coreboot[master]: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode
by Aamir Bohra (Code Review) 09 Sep '20

09 Sep '20

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43494 ) Change subject: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode ...................................................................... Patch Set 7: (3 comments) https://review.coreboot.org/c/coreboot/+/43494/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/43494/3//COMMIT_MSG@23 PS3, Line 23: mas > maps Done https://review.coreboot.org/c/coreboot/+/43494/3//COMMIT_MSG@20 PS3, Line 20: : Also the COS mask selection is mapped to bit 32:33 of MSR : IA32_PQR_ASSOC(0xC8F) and need to be updated in edx(maps 63:32) before : MSR write instead of eax(mas 31:0). This implementation corrects that : as well. > yes, MSR definition is not documented for TGL, CML, KBL. We can get it revised. Done https://review.coreboot.org/c/coreboot/+/43494/3/src/soc/intel/common/block… File src/soc/intel/common/block/cpu/car/cache_as_ram.S: PS3: > yes, we configure the mask2 with the RW data mapped ways configured for eviction and start filling i […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/43494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54e047161853bfc70516c1d607aa479e68836d04 Gerrit-Change-Number: 43494 Gerrit-PatchSet: 7 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Comment-Date: Wed, 09 Sep 2020 03:05:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode
by Aamir Bohra (Code Review) 09 Sep '20

09 Sep '20

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43494 ) Change subject: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode ...................................................................... Patch Set 7: (3 comments) https://review.coreboot.org/c/coreboot/+/43494/1/src/soc/intel/common/block… File src/soc/intel/common/block/cpu/car/cache_as_ram.S: https://review.coreboot.org/c/coreboot/+/43494/1/src/soc/intel/common/block… PS1, Line 371: * Data Size (RW) : Up to 256K > Yes..however way size depends on the total LLC and number of ways that a platform supports. […] Done https://review.coreboot.org/c/coreboot/+/43494/1/src/soc/intel/common/block… PS1, Line 429: movl $0x02, %edx > COS is mapped to 32:33 of the MSR 0xCF8 , that is why assigning it to EDX. Done https://review.coreboot.org/c/coreboot/+/43494/1/src/soc/intel/common/block… PS1, Line 445: movl $0x01, %edx > same above Done -- To view, visit https://review.coreboot.org/c/coreboot/+/43494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54e047161853bfc70516c1d607aa479e68836d04 Gerrit-Change-Number: 43494 Gerrit-PatchSet: 7 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Comment-Date: Wed, 09 Sep 2020 03:04:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/jasperlake: Disable PAVP UPD
by Ronak Kanabar (Code Review) 09 Sep '20

09 Sep '20

Ronak Kanabar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41763 ) Change subject: soc/intel/jasperlake: Disable PAVP UPD ...................................................................... soc/intel/jasperlake: Disable PAVP UPD This patch will disable PAVP UPD, which is by default enable in FSP. BUG=b:155595624 BRANCH=None TEST=Build, boot JSLRVP, Verified UPD values from FSP log Change-Id: I8e103ad11ae6ffa6b9efe4bf249bbe344bc10a30 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/soc/intel/jasperlake/fsp_params.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/41763/1 diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index 45162f9..311af3e 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -199,6 +199,9 @@ params->XdciEnable = 0; } + /* Disable Pavp */ + params->PavpEnable = 0 + /* Provide correct UART number for FSP debug logs */ params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; -- To view, visit https://review.coreboot.org/c/coreboot/+/41763 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e103ad11ae6ffa6b9efe4bf249bbe344bc10a30 Gerrit-Change-Number: 41763 Gerrit-PatchSet: 1 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: newchange

7 11

Change in coreboot[master]: mb/google/puff: Update DPTF parameters for faffy
by David Wu (Code Review) 09 Sep '20

09 Sep '20

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45169 ) Change subject: mb/google/puff: Update DPTF parameters for faffy ...................................................................... mb/google/puff: Update DPTF parameters for faffy Update critical and passive policy for TSR0. BUG=b:167477885 BRANCH=puff TEST=build and verify by thermal team Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I244e1b5cacabf5b73c47b4039ae150cd17fcd0fc --- M src/mainboard/google/hatch/variants/faffy/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/45169/1 diff --git a/src/mainboard/google/hatch/variants/faffy/overridetree.cb b/src/mainboard/google/hatch/variants/faffy/overridetree.cb index c1bd1e4..a05cb9d 100644 --- a/src/mainboard/google/hatch/variants/faffy/overridetree.cb +++ b/src/mainboard/google/hatch/variants/faffy/overridetree.cb @@ -281,11 +281,11 @@ chip drivers/intel/dptf ## Passive Policy register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)" - register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 63, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000)" ## Critical Policy register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" - register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 78, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN)" ## Power Limits Control # 10-15W PL1 in 200mW increments, avg over 28-32s interval -- To view, visit https://review.coreboot.org/c/coreboot/+/45169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I244e1b5cacabf5b73c47b4039ae150cd17fcd0fc Gerrit-Change-Number: 45169 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: trogdor: SoC makefile blob support
by Julius Werner (Code Review) 09 Sep '20

09 Sep '20

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35508 ) Change subject: trogdor: SoC makefile blob support ...................................................................... Patch Set 92: Ravi, can you please rebase the whole patch train once more (to pick up CB:45057)? With that, fingers crossed, Jenkins should hopefully set Verified+1 here. -- To view, visit https://review.coreboot.org/c/coreboot/+/35508 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85a20ef31ec91c6f22221d16fd4c3097c5cb97d1 Gerrit-Change-Number: 35508 Gerrit-PatchSet: 92 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: ashk(a)codeaurora.org Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Saurabh Gorecha <sgorecha(a)codeaurora.org> Gerrit-Comment-Date: Wed, 09 Sep 2020 00:03:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: 3rdparty/qc_blobs: Uprev to new HEAD (c564412)
by Julius Werner (Code Review) 09 Sep '20

09 Sep '20

Hello Patrick Georgi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45057 to review the following change. Change subject: 3rdparty/qc_blobs: Uprev to new HEAD (c564412) ...................................................................... 3rdparty/qc_blobs: Uprev to new HEAD (c564412) Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I2de0c13000e5b1e32e9c1a6de3daa09acf6c321b --- M 3rdparty/qc_blobs 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/45057/1 diff --git a/3rdparty/qc_blobs b/3rdparty/qc_blobs index 126fef6..c564412 160000 --- a/3rdparty/qc_blobs +++ b/3rdparty/qc_blobs @@ -1 +1 @@ -Subproject commit 126fef6b996237403039aa603945fc4caa75c8d6 +Subproject commit c56441253e7a6e3d74226aafdf307b8882484ebd -- To view, visit https://review.coreboot.org/c/coreboot/+/45057 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2de0c13000e5b1e32e9c1a6de3daa09acf6c321b Gerrit-Change-Number: 45057 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: vc/amd/fsp/picasso: Add a GUID for reporting NB IOAPIC base
by Marshall Dawson (Code Review) 08 Sep '20

08 Sep '20

Hello Jason Glenesk, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45114 to review the following change. Change subject: vc/amd/fsp/picasso: Add a GUID for reporting NB IOAPIC base ...................................................................... vc/amd/fsp/picasso: Add a GUID for reporting NB IOAPIC base The GUID will be used in an upcoming patch to identify a HOB. BUG=b:167421913, b:166519072 TEST=none BRANCH=zork Signed-off-by: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: I499e0ef801e4e98a63510a326d1134dd98305238 --- M src/vendorcode/amd/fsp/picasso/FspGuids.h 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/45114/1 diff --git a/src/vendorcode/amd/fsp/picasso/FspGuids.h b/src/vendorcode/amd/fsp/picasso/FspGuids.h index 70bbe74..277fce1 100644 --- a/src/vendorcode/amd/fsp/picasso/FspGuids.h +++ b/src/vendorcode/amd/fsp/picasso/FspGuids.h @@ -33,4 +33,8 @@ GUID_INIT(0xf2784616, 0xb9bf, 0x4e1e, \ 0x99, 0xe0, 0x96, 0x26, 0xda, 0x7e, 0xa5, 0xf5) +#define AMD_FSP_NB_IOAPIC_BASE_HOB_GUID \ + GUID_INIT(0xdd9738b3, 0x679e, 0x4e19, \ + 0x80, 0xd1, 0xe4, 0x99, 0xed, 0x0a, 0x6d, 0xa1) + #endif /* __FSP_GUIDS__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45114 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I499e0ef801e4e98a63510a326d1134dd98305238 Gerrit-Change-Number: 45114 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: soc/amd/picasso: Make IVRS GNB entry depend on APIC enabled
by Marshall Dawson (Code Review) 08 Sep '20

08 Sep '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45116 ) Change subject: soc/amd/picasso: Make IVRS GNB entry depend on APIC enabled ...................................................................... soc/amd/picasso: Make IVRS GNB entry depend on APIC enabled Check whether FSP has enabled the GNB IOAPIC before generating its entry in the IVRS table. BUG=b:167421913, b:166519072 TEST=Verify no difference in IVRS before/after BRANCH=Zork Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: I4caec158a252737cea5a1070fa4673faf3680b9f --- M src/soc/amd/picasso/agesa_acpi.c 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/45116/1 diff --git a/src/soc/amd/picasso/agesa_acpi.c b/src/soc/amd/picasso/agesa_acpi.c index c76e943..6cdb04c 100644 --- a/src/soc/amd/picasso/agesa_acpi.c +++ b/src/soc/amd/picasso/agesa_acpi.c @@ -12,6 +12,8 @@ #include <soc/pci_devs.h> #include <stdlib.h> #include <arch/mmio.h> +#include <fsp/util.h> +#include <FspGuids.h> struct amd_fsp_acpi_hob_info { uint32_t table_size_in_bytes; @@ -47,6 +49,9 @@ unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current) { + struct range_entry hob; + int status; + ivrs_ivhd_special_t *ivhd_ioapic = (ivrs_ivhd_special_t *)current; memset(ivhd_ioapic, 0, sizeof(*ivhd_ioapic)); @@ -59,6 +64,14 @@ ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC; current += sizeof(ivrs_ivhd_special_t); + /* FSP populates this generates this HOB if it initializes second IOAPIC */ + status = fsp_find_range_hob(&hob, AMD_FSP_NB_IOAPIC_BASE_HOB_GUID.b); + + if (status || !hob.begin) { + printk(BIOS_ERR, " NB_IOAPIC_BASE HOB was not found.\n"); + return current; + } + ivhd_ioapic = (ivrs_ivhd_special_t *)current; memset(ivhd_ioapic, 0, sizeof(*ivhd_ioapic)); -- To view, visit https://review.coreboot.org/c/coreboot/+/45116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4caec158a252737cea5a1070fa4673faf3680b9f Gerrit-Change-Number: 45116 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mb/google/dedede: Fix the SPD path
by Karthik Ramasubramanian (Code Review) 08 Sep '20

08 Sep '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45182 ) Change subject: mb/google/dedede: Fix the SPD path ...................................................................... mb/google/dedede: Fix the SPD path CB:44774 introduced the non-existent SPD path. This is preventing the device from booting up. BUG=b:168053219 TEST=Build and boot drawcia board to OS. Change-Id: I70ca5f4cf2c8e2e88ea5b1514b656caafb732743 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/spd/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/45182/1 diff --git a/src/mainboard/google/dedede/spd/Makefile.inc b/src/mainboard/google/dedede/spd/Makefile.inc index f73a3e4..ebc11e5 100644 --- a/src/mainboard/google/dedede/spd/Makefile.inc +++ b/src/mainboard/google/dedede/spd/Makefile.inc @@ -1,3 +1,3 @@ ## SPDX-License-Identifier: GPL-2.0-or-later -LIB_SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/soc/intel/jasperlake/spd/lp4x/$(f)) +LIB_SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/soc/intel/jasperlake/spd/$(f)) -- To view, visit https://review.coreboot.org/c/coreboot/+/45182 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70ca5f4cf2c8e2e88ea5b1514b656caafb732743 Gerrit-Change-Number: 45182 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode
by Tim Wawrzynczak (Code Review) 08 Sep '20

08 Sep '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43494 ) Change subject: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/43494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54e047161853bfc70516c1d607aa479e68836d04 Gerrit-Change-Number: 43494 Gerrit-PatchSet: 7 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Comment-Date: Tue, 08 Sep 2020 21:45:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit September 2020