coreboot-gerrit September 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/elkhartlake: Update SA & PM related variables
by Lean Sheng Tan (Code Review) 08 Sep '20

08 Sep '20

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45077 ) Change subject: soc/intel/elkhartlake: Update SA & PM related variables ...................................................................... soc/intel/elkhartlake: Update SA & PM related variables 1. Update SA base address & size 2. Update GBE control bit register value Signed-off-by: Tan, Lean Sheng <lean.sheng.tan(a)intel.com> Change-Id: I1f5036c9cd75682fcf239170bcb257ffaa002e7d --- M src/soc/intel/elkhartlake/include/soc/iomap.h M src/soc/intel/elkhartlake/include/soc/pm.h 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/45077/1 diff --git a/src/soc/intel/elkhartlake/include/soc/iomap.h b/src/soc/intel/elkhartlake/include/soc/iomap.h index 5ba40bc..0246673 100644 --- a/src/soc/intel/elkhartlake/include/soc/iomap.h +++ b/src/soc/intel/elkhartlake/include/soc/iomap.h @@ -47,8 +47,8 @@ #define VTD_BASE_ADDRESS 0xfed90000 #define VTD_BASE_SIZE 0x00004000 -#define MCH_BASE_ADDRESS 0xfea80000 -#define MCH_BASE_SIZE 0x8000 +#define MCH_BASE_ADDRESS 0xfec80000 +#define MCH_BASE_SIZE 0x80000 #define EARLY_GSPI_BASE_ADDRESS 0xfe011000 diff --git a/src/soc/intel/elkhartlake/include/soc/pm.h b/src/soc/intel/elkhartlake/include/soc/pm.h index 11d6663..6ebbbfa 100644 --- a/src/soc/intel/elkhartlake/include/soc/pm.h +++ b/src/soc/intel/elkhartlake/include/soc/pm.h @@ -65,7 +65,7 @@ #define SMI_ON_SLP_EN_STS_BIT 4 #define LEGACY_USB_STS_BIT 3 #define BIOS_STS_BIT 2 -#define GPE_CNTL 0x42 +#define GPE_CNTL 0x40 #define SWGPE_CTRL (1 << 1) #define DEVACT_STS 0x44 #define PM2_CNT 0x50 -- To view, visit https://review.coreboot.org/c/coreboot/+/45077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f5036c9cd75682fcf239170bcb257ffaa002e7d Gerrit-Change-Number: 45077 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3333
by Srinidhi N Kaushik (Code Review) 08 Sep '20

08 Sep '20

Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44912 ) Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3333 ...................................................................... vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3333 Update FSP headers for Tiger Lake platform generated based FSP version 3333. Previous version was 3313. Changes Include: 1. Update comments 2. Add new UPD for Gpio Override support BUG=b:166790597 BRANCH=none TEST=build and boot volteer proto2 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: Ie3f0688143eef532946c7a2141909c1ac173fc2f --- M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h 2 files changed, 15 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/44912/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h index 32b6a32..0b3fe7d 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h @@ -2487,7 +2487,18 @@ /** Offset 0x089F - Reserved **/ - UINT8 Reserved44[129]; + UINT8 Reserved44[124]; + +/** Offset 0x091B - GPIO Override + Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings + before moved to FSP. Available configurations 0: Disable;1: Level 1 - skips GpioSetNativePadByFunction;Level + 2 - skips GpioSetNativePadByFunction and GpioSetPadMode +**/ + UINT8 GpioOverride; + +/** Offset 0x091C - Reserved +**/ + UINT8 Reserved45[4]; } FSP_M_CONFIG; /** Fsp M UPD Configuration @@ -2508,7 +2519,7 @@ /** Offset 0x0920 **/ - UINT8 UnusedUpdSpace26[6]; + UINT8 UnusedUpdSpace25[6]; /** Offset 0x0926 **/ diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h index b0d9ca9..315a0a7 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h @@ -828,8 +828,8 @@ **/ UINT8 AmtKvmEnabled; -/** Offset 0x040E - KVM Switch - Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx. +/** Offset 0x040E - Force MEBX execution + Enable/Disable. 0: Disable, 1: enable, Force MEBX execution. $EN_DIS **/ UINT8 ForcMebxSyncUp; -- To view, visit https://review.coreboot.org/c/coreboot/+/44912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3f0688143eef532946c7a2141909c1ac173fc2f Gerrit-Change-Number: 44912 Gerrit-PatchSet: 1 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-MessageType: newchange

5 5

Change in coreboot[master]: soc/intel/elkhartlake/acpi: Copy acpi directory from jasperlake
by Lean Sheng Tan (Code Review) 08 Sep '20

08 Sep '20

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44812 ) Change subject: soc/intel/elkhartlake/acpi: Copy acpi directory from jasperlake ...................................................................... soc/intel/elkhartlake/acpi: Copy acpi directory from jasperlake Clone entirely from Jasperlake List of changes on top off initial jasperlake clone 1. Rename from jasperlake to elkhartlake 2. Remove irelevant devices asls (ipu,ish,camera clock) Signed-off-by: Tan, Lean Sheng <lean.sheng.tan(a)intel.com> Change-Id: I5e77081d1673cc0ca97edc63e9996c045ab6e9b0 --- A src/soc/intel/elkhartlake/acpi/gpio.asl A src/soc/intel/elkhartlake/acpi/gpio_op.asl A src/soc/intel/elkhartlake/acpi/pch_glan.asl A src/soc/intel/elkhartlake/acpi/pch_hda.asl A src/soc/intel/elkhartlake/acpi/pci_irqs.asl A src/soc/intel/elkhartlake/acpi/pcie.asl A src/soc/intel/elkhartlake/acpi/platform.asl A src/soc/intel/elkhartlake/acpi/pmc.asl A src/soc/intel/elkhartlake/acpi/scs.asl A src/soc/intel/elkhartlake/acpi/serialio.asl A src/soc/intel/elkhartlake/acpi/smbus.asl A src/soc/intel/elkhartlake/acpi/southbridge.asl A src/soc/intel/elkhartlake/acpi/xhci.asl 13 files changed, 1,177 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/44812/1 diff --git a/src/soc/intel/elkhartlake/acpi/gpio.asl b/src/soc/intel/elkhartlake/acpi/gpio.asl new file mode 100644 index 0000000..f8b180d --- /dev/null +++ b/src/soc/intel/elkhartlake/acpi/gpio.asl @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <intelblocks/gpio.h> +#include <soc/gpio_defs.h> +#include <soc/irq.h> +#include <soc/pcr_ids.h> +#include "gpio_op.asl" + +#include <soc/intel/common/acpi/gpio.asl> + +Device (GPIO) +{ + Name (_HID, CROS_GPIO_NAME) + Name (_UID, 0) + Name (_DDN, "GPIO Controller") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0, COM0) + Memory32Fixed (ReadWrite, 0, 0, COM1) + Memory32Fixed (ReadWrite, 0, 0, COM2) + Memory32Fixed (ReadWrite, 0, 0, COM4) + Memory32Fixed (ReadWrite, 0, 0, COM5) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) + { GPIO_IRQ14 } + }) + + Method (_CRS, 0, NotSerialized) + { + /* GPIO Community 0 */ + CreateDWordField (^RBUF, ^COM0._BAS, BAS0) + CreateDWordField (^RBUF, ^COM0._LEN, LEN0) + BAS0 = ^^PCRB (PID_GPIOCOM0) + LEN0 = GPIO_BASE_SIZE + + /* GPIO Community 1 */ + CreateDWordField (^RBUF, ^COM1._BAS, BAS1) + CreateDWordField (^RBUF, ^COM1._LEN, LEN1) + BAS1 = ^^PCRB (PID_GPIOCOM1) + LEN1 = GPIO_BASE_SIZE + + /* GPIO Community 2 */ + CreateDWordField (^RBUF, ^COM2._BAS, BAS2) + CreateDWordField (^RBUF, ^COM2._LEN, LEN2) + BAS2 = ^^PCRB (PID_GPIOCOM2) + LEN2 = GPIO_BASE_SIZE + + /* GPIO Community 4 */ + CreateDWordField (^RBUF, ^COM4._BAS, BAS4) + CreateDWordField (^RBUF, ^COM4._LEN, LEN4) + BAS4 = ^^PCRB (PID_GPIOCOM4) + LEN4 = GPIO_BASE_SIZE + + /* GPIO Community 5 */ + CreateDWordField (^RBUF, ^COM5._BAS, BAS5) + CreateDWordField (^RBUF, ^COM5._LEN, LEN5) + BAS5 = ^^PCRB (PID_GPIOCOM5) + LEN5 = GPIO_BASE_SIZE + + Return (RBUF) + } + + Method (_STA, 0, NotSerialized) + { + Return (0xF) + } +} +/* + * Get GPIO DW0 Address + * Arg0 - GPIO Number + */ +Method (GADD, 1, NotSerialized) +{ + /* GPIO Community 0 */ + If (Arg0 >= GPIO_COM0_START && Arg0 <= GPIO_COM0_END) + { + Local0 = PID_GPIOCOM0 + Local1 = Arg0 - GPIO_COM0_START + } + /* GPIO Community 1 */ + If (Arg0 >= GPIO_COM1_START && Arg0 <= GPIO_COM1_END) + { + Local0 = PID_GPIOCOM1 + Local1 = Arg0 - GPIO_COM1_START + } + /* GPIO Community 2 */ + If (Arg0 >= GPIO_COM2_START && Arg0 <= GPIO_COM2_END) + { + Local0 = PID_GPIOCOM2 + Local1 = Arg0 - GPIO_COM2_START + } + /* GPIO Community 4 */ + If (Arg0 >= GPIO_COM4_START && Arg0 <= GPIO_COM4_END) + { + Local0 = PID_GPIOCOM4 + Local1 = Arg0 - GPIO_COM4_START + } + /* GPIO Community 05*/ + If (Arg0 >= GPIO_COM5_START && Arg0 <= GPIO_COM5_END) + { + Local0 = PID_GPIOCOM5 + Local1 = Arg0 - GPIO_COM5_START + } + + Local2 = PCRB(Local0) + PAD_CFG_BASE + (Local1 * 16) + Return (Local2) +} + +/* + * Return PCR Port ID of GPIO Communities + * + * Arg0: GPIO Community (0-5) + */ +Method (GPID, 1, Serialized) +{ + Switch (ToInteger (Arg0)) + { + Case (COMM_0) { + Local0 = PID_GPIOCOM0 + } + Case (COMM_1) { + Local0 = PID_GPIOCOM1 + } + Case (COMM_2) { + Local0 = PID_GPIOCOM2 + } + Case (COMM_4) { + Local0 = PID_GPIOCOM4 + } + Case (COMM_5) { + Local0 = PID_GPIOCOM5 + } + Default { + Return (0) + } + } + + Return (Local0) +} diff --git a/src/soc/intel/elkhartlake/acpi/gpio_op.asl b/src/soc/intel/elkhartlake/acpi/gpio_op.asl new file mode 100644 index 0000000..683686f --- /dev/null +++ b/src/soc/intel/elkhartlake/acpi/gpio_op.asl @@ -0,0 +1,127 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * Get GPIO Value + * Arg0 - GPIO Number + */ +Method (GRXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + Local0 = PAD_CFG0_RX_STATE & (VAL0 >> PAD_CFG0_RX_STATE_BIT) + + Return (Local0) +} + +/* + * Get GPIO Tx Value + * Arg0 - GPIO Number + */ +Method (GTXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + Local0 = PAD_CFG0_TX_STATE & VAL0 + + Return (Local0) +} + +/* + * Set GPIO Tx Value + * Arg0 - GPIO Number + */ +Method (STXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + VAL0 = PAD_CFG0_TX_STATE | VAL0 +} + +/* + * Clear GPIO Tx Value + * Arg0 - GPIO Number + */ +Method (CTXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + VAL0 = ~PAD_CFG0_TX_STATE & VAL0 +} + +/* + * Set Pad mode + * Arg0 - GPIO Number + * Arg1 - Pad mode + * 0 = GPIO control pad + * 1 = Native Function 1 + * 2 = Native Function 2 + * 3 = Native Function 3 + */ +Method (GPMO, 2, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + Local0 = VAL0 + Local0 = ~PAD_CFG0_MODE_MASK & Local0 + Arg1 = (Arg1 <<= PAD_CFG0_MODE_SHIFT) & PAD_CFG0_MODE_MASK + VAL0 = Local0 | Arg1 +} + +/* + * Enable/Disable Tx buffer + * Arg0 - GPIO Number + * Arg1 - TxBuffer state + * 0 = Disable Tx Buffer + * 1 = Enable Tx Buffer + */ +Method (GTXE, 2, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + + If (Arg1 == 1) { + VAL0 = ~PAD_CFG0_TX_DISABLE & VAL0 + } ElseIf (Arg1 == 0){ + VAL0 = PAD_CFG0_TX_DISABLE | VAL0 + } +} + +/* + * Enable/Disable Rx buffer + * Arg0 - GPIO Number + * Arg1 - RxBuffer state + * 0 = Disable Rx Buffer + * 1 = Enable Rx Buffer + */ +Method (GRXE, 2, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + + If (Arg1 == 1) { + VAL0 = ~PAD_CFG0_RX_DISABLE & VAL0 + } ElseIf (Arg1 == 0){ + VAL0 = PAD_CFG0_RX_DISABLE | VAL0 + } +} diff --git a/src/soc/intel/elkhartlake/acpi/pch_glan.asl b/src/soc/intel/elkhartlake/acpi/pch_glan.asl new file mode 100644 index 0000000..97faf7a --- /dev/null +++ b/src/soc/intel/elkhartlake/acpi/pch_glan.asl @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Intel Gigabit Ethernet Controller 0:1f.6 */ + +Device (GLAN) +{ + Name (_ADR, 0x001f0006) + + Name (_S0W, 3) + + Name (_PRW, Package() {GPE0_PME_B0, 4}) + + Method (_DSW, 3) {} +} diff --git a/src/soc/intel/elkhartlake/acpi/pch_hda.asl b/src/soc/intel/elkhartlake/acpi/pch_hda.asl new file mode 100644 index 0000000..340c765 --- /dev/null +++ b/src/soc/intel/elkhartlake/acpi/pch_hda.asl @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Audio Controller - Device 31, Function 3 */ + +Device (HDAS) +{ + Name (_ADR, 0x001f0003) + Name (_DDN, "Audio Controller") + Name (UUID, ToUUID ("A69F886E-6CEB-4594-A41F-7B5DCE24C553")) + + /* Device is D3 wake capable */ + Name (_S0W, 3) + + /* NHLT Table Address populated from GNVS values */ + Name (NBUF, ResourceTemplate () { + QWordMemory (ResourceConsumer, PosDecode, MinFixed, + MaxFixed, NonCacheable, ReadOnly, + 0, 0, 0, 0, 1,,, NHLT, AddressRangeACPI) + }) + + /* + * Device Specific Method + * Arg0 - UUID + * Arg1 - Revision + * Arg2 - Function Index + */ + Method (_DSM, 4) + { + If (Arg0 == ^UUID) { + /* + * Function 0: Function Support Query + * Returns a bitmask of functions supported. + */ + If (Arg2 == Zero) { + /* + * NHLT Query only supported for revision 1 and + * if NHLT address and length are set in NVS. + */ + If ((Arg1 == One) && ((NHLA != Zero) && (NHLL != Zero))) { + Return (Buffer (One) { 0x03 }) + } Else { + Return (Buffer (One) { 0x01 }) + } + } + + /* + * Function 1: Query NHLT memory address used by + * Intel Offload Engine Driver to discover any non-HDA + * devices that are supported by the DSP. + * + * Returns a pointer to NHLT table in memory. + */ + If (Arg2 == One) { + CreateQWordField (NBUF, ^NHLT._MIN, NBAS) + CreateQWordField (NBUF, ^NHLT._MAX, NMAS) + CreateQWordField (NBUF, ^NHLT._LEN, NLEN) + + NBAS = NHLA + NMAS = NHLA + NLEN = NHLL + + Return (NBUF) + } + } + + Return (Buffer (One) { 0x00 }) + } +} diff --git a/src/soc/intel/elkhartlake/acpi/pci_irqs.asl b/src/soc/intel/elkhartlake/acpi/pci_irqs.asl new file mode 100644 index 0000000..aa494a7 --- /dev/null +++ b/src/soc/intel/elkhartlake/acpi/pci_irqs.asl @@ -0,0 +1,112 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <soc/irq.h> + +Name (PICP, Package () { + Package(){0x001FFFFF, 0, 0, PCH_IRQ_16 }, + Package(){0x001FFFFF, 1, 0, PCH_IRQ_17 }, + Package(){0x001FFFFF, 2, 0, PCH_IRQ_18 }, + Package(){0x001FFFFF, 3, 0, PCH_IRQ_19 }, + + Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ }, + Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ }, + Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ }, + Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ }, + + Package(){0x001CFFFF, 0, 0, PCH_IRQ_16 }, + Package(){0x001CFFFF, 1, 0, PCH_IRQ_17 }, + Package(){0x001CFFFF, 2, 0, PCH_IRQ_18 }, + Package(){0x001CFFFF, 3, 0, PCH_IRQ_19 }, + + Package(){0x001AFFFF, 0, 0, PCH_IRQ_16 }, + + Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ }, + Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ }, + Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ }, + + Package(){0x0017FFFF, 0, 0, PCH_IRQ_16 }, + + Package(){0x0016FFFF, 0, 0, PCH_IRQ_16 }, + Package(){0x0016FFFF, 1, 0, PCH_IRQ_17 }, + Package(){0x0016FFFF, 2, 0, PCH_IRQ_18 }, + Package(){0x0016FFFF, 3, 0, PCH_IRQ_19 }, + + Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ }, + Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ }, + Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ }, + Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ }, + + Package(){0x0014FFFF, 0, 0, PCH_IRQ_16 }, + Package(){0x0014FFFF, 1, 0, PCH_IRQ_17 }, + Package(){0x0014FFFF, 2, 0, PCH_IRQ_18 }, + Package(){0x0014FFFF, 3, 0, PCH_IRQ_19 }, + + Package(){0x0012FFFF, 1, 0, LPSS_SPI2_IRQ }, + /* SA GNA Device */ + Package(){0x0008FFFF, 0, 0, PCH_IRQ_16 }, + /* SA IPU Device */ + Package(){0x0005FFFF, 0, 0, PCH_IRQ_16 }, + /* SA Thermal Device */ + Package(){0x0004FFFF, 0, 0, PCH_IRQ_16 }, + /* SA IGFX Device */ + Package(){0x0002FFFF, 0, 0, PCH_IRQ_16 }, +}) + +Name (PICN, Package () { + Package () { 0x001FFFFF, 0, 0, PCH_IRQ11 }, + Package () { 0x001FFFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x001FFFFF, 2, 0, PCH_IRQ11 }, + Package () { 0x001FFFFF, 3, 0, PCH_IRQ11 }, + + Package () { 0x001EFFFF, 0, 0, PCH_IRQ11 }, + Package () { 0x001EFFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x001EFFFF, 2, 0, PCH_IRQ11 }, + Package () { 0x001EFFFF, 3, 0, PCH_IRQ11 }, + + Package () { 0x001CFFFF, 0, 0, PCH_IRQ11 }, + Package () { 0x001CFFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x001CFFFF, 2, 0, PCH_IRQ11 }, + Package () { 0x001CFFFF, 3, 0, PCH_IRQ11 }, + + Package () { 0x001AFFFF, 0, 0, PCH_IRQ11 }, + + Package () { 0x0019FFFF, 0, 0, PCH_IRQ11 }, + Package () { 0x0019FFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x0019FFFF, 2, 0, PCH_IRQ11 }, + + Package () { 0x0017FFFF, 0, 0, PCH_IRQ11 }, + + Package () { 0x0016FFFF, 0, 0, PCH_IRQ11 }, + Package () { 0x0016FFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x0016FFFF, 2, 0, PCH_IRQ11 }, + Package () { 0x0016FFFF, 3, 0, PCH_IRQ11 }, + + Package () { 0x0015FFFF, 0, 0, PCH_IRQ11 }, + Package () { 0x0015FFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x0015FFFF, 2, 0, PCH_IRQ11 }, + Package () { 0x0015FFFF, 3, 0, PCH_IRQ11 }, + + Package () { 0x0014FFFF, 0, 0, PCH_IRQ11 }, + Package () { 0x0014FFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x0014FFFF, 2, 0, PCH_IRQ11 }, + Package () { 0x0014FFFF, 3, 0, PCH_IRQ11 }, + + Package () { 0x0012FFFF, 1, 0, PCH_IRQ10 }, + /* SA GNA Device */ + Package () { 0x0008FFFF, 0, 0, PCH_IRQ11 }, + /* SA IPU Device */ + Package () { 0x0005FFFF, 0, 0, PCH_IRQ11 }, + /* SA Thermal Device */ + Package () { 0x0004FFFF, 0, 0, PCH_IRQ11 }, + /* SA IGFX Device */ + Package () { 0x0002FFFF, 0, 0, PCH_IRQ11 }, +}) + +Method (_PRT) +{ + If (PICM) { + Return (^PICP) + } Else { + Return (^PICN) + } +} diff --git a/src/soc/intel/elkhartlake/acpi/pcie.asl b/src/soc/intel/elkhartlake/acpi/pcie.asl new file mode 100644 index 0000000..a19feb7 --- /dev/null +++ b/src/soc/intel/elkhartlake/acpi/pcie.asl @@ -0,0 +1,301 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Intel PCH PCIe support */ + +Method (IRQM, 1, Serialized) { + + /* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */ + Name (IQAA, Package () { + Package () { 0x0000ffff, 0, 0, 16 }, + Package () { 0x0000ffff, 1, 0, 17 }, + Package () { 0x0000ffff, 2, 0, 18 }, + Package () { 0x0000ffff, 3, 0, 19 } }) + Name (IQAP, Package () { + Package () { 0x0000ffff, 0, 0, 11 }, + Package () { 0x0000ffff, 1, 0, 10 }, + Package () { 0x0000ffff, 2, 0, 11 }, + Package () { 0x0000ffff, 3, 0, 11 } }) + + /* Interrupt Map INTA->INTB, INTB->INTC, INTC->INTD, INTD->INTA */ + Name (IQBA, Package () { + Package () { 0x0000ffff, 0, 0, 17 }, + Package () { 0x0000ffff, 1, 0, 18 }, + Package () { 0x0000ffff, 2, 0, 19 }, + Package () { 0x0000ffff, 3, 0, 16 } }) + Name (IQBP, Package () { + Package () { 0x0000ffff, 0, 0, 10 }, + Package () { 0x0000ffff, 1, 0, 11 }, + Package () { 0x0000ffff, 2, 0, 11 }, + Package () { 0x0000ffff, 3, 0, 11 } }) + + /* Interrupt Map INTA->INTC, INTB->INTD, INTC->INTA, INTD->INTB */ + Name (IQCA, Package () { + Package () { 0x0000ffff, 0, 0, 18 }, + Package () { 0x0000ffff, 1, 0, 19 }, + Package () { 0x0000ffff, 2, 0, 16 }, + Package () { 0x0000ffff, 3, 0, 17 } }) + Name (IQCP, Package () { + Package () { 0x0000ffff, 0, 0, 11 }, + Package () { 0x0000ffff, 1, 0, 11 }, + Package () { 0x0000ffff, 2, 0, 11 }, + Package () { 0x0000ffff, 3, 0, 10 } }) + + /* Interrupt Map INTA->INTD, INTB->INTA, INTC->INTB, INTD->INTC */ + Name (IQDA, Package () { + Package () { 0x0000ffff, 0, 0, 19 }, + Package () { 0x0000ffff, 1, 0, 16 }, + Package () { 0x0000ffff, 2, 0, 17 }, + Package () { 0x0000ffff, 3, 0, 18 } }) + Name (IQDP, Package () { + Package () { 0x0000ffff, 0, 0, 11 }, + Package () { 0x0000ffff, 1, 0, 11 }, + Package () { 0x0000ffff, 2, 0, 10 }, + Package () { 0x0000ffff, 3, 0, 11 } }) + + Switch (ToInteger (Arg0)) + { + Case (Package () { 1, 5, 9, 13 }) { + If (PICM) { + Return (IQAA) + } Else { + Return (IQAP) + } + } + + Case (Package () { 2, 6, 10, 14 }) { + If (PICM) { + Return (IQBA) + } Else { + Return (IQBP) + } + } + + Case (Package () { 3, 7, 11, 15 }) { + If (PICM) { + Return (IQCA) + } Else { + Return (IQCP) + } + } + + Case (Package () { 4, 8, 12, 16 }) { + If (PICM) { + Return (IQDA) + } Else { + Return (IQDP) + } + } + + Default { + If (PICM) { + Return (IQDA) + } Else { + Return (IQDP) + } + } + } +} + +Device (RP01) +{ + Name (_ADR, 0x001C0000) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP02) +{ + Name (_ADR, 0x001C0001) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP03) +{ + Name (_ADR, 0x001C0002) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP04) +{ + Name (_ADR, 0x001C0003) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP05) +{ + Name (_ADR, 0x001C0004) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP06) +{ + Name (_ADR, 0x001C0005) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP07) +{ + Name (_ADR, 0x001C0006) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP08) +{ + Name (_ADR, 0x001C0007) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP09) +{ + Name (_ADR, 0x001D0000) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP10) +{ + Name (_ADR, 0x001D0001) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP11) +{ + Name (_ADR, 0x001D0002) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP12) +{ + Name (_ADR, 0x001D0003) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} diff --git a/src/soc/intel/elkhartlake/acpi/platform.asl b/src/soc/intel/elkhartlake/acpi/platform.asl new file mode 100644 index 0000000..4b01aeb --- /dev/null +++ b/src/soc/intel/elkhartlake/acpi/platform.asl @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Enable ACPI _SWS methods */ +#include <soc/intel/common/acpi/acpi_wake_source.asl> +/* Generic indicator for sleep state */ +#include <soc/intel/common/acpi/platform.asl> + +/* + * The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method (_PIC, 1) +{ + /* Remember the OS' IRQ routing choice. */ + PICM = Arg0 +} diff --git a/src/soc/intel/elkhartlake/acpi/pmc.asl b/src/soc/intel/elkhartlake/acpi/pmc.asl new file mode 100644 index 0000000..ea4134b --- /dev/null +++ b/src/soc/intel/elkhartlake/acpi/pmc.asl @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/iomap.h> + +Scope (\_SB.PCI0) { + + Device (PMC) + { + Name (_HID, "INTC1026") + Name (_DDN, "Intel(R) Elkhart Lake IPC Controller") + /* + * PCH preserved 32 MB MMIO range from 0xFC800000 to 0xFE7FFFFF. + * 64KB (0xFE000000 - 0xFE00FFFF) for PMC MBAR. + */ + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, PCH_PWRM_BASE_ADDRESS, 0x00010000) + }) + } +} diff --git a/src/soc/intel/elkhartlake/acpi/scs.asl b/src/soc/intel/elkhartlake/acpi/scs.asl new file mode 100644 index 0000000..b58608f --- /dev/null +++ b/src/soc/intel/elkhartlake/acpi/scs.asl @@ -0,0 +1,193 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/pcr_ids.h> + +Scope (\_SB.PCI0) { + + /* + * Clear register 0x1C20/0x4820 + * Arg0 - PCR Port ID + */ + Method(SCSC, 1, Serialized) + { + PCRA (Arg0, 0x1C20, 0x0) + PCRA (Arg0, 0x4820, 0x0) + } + + /* EMMC */ + Device(PEMC) { + Name(_ADR, 0x001A0000) + Name (_DDN, "eMMC Controller") + Name (TEMP, 0) + + OperationRegion(SCSR, PCI_Config, 0x00, 0x100) + Field(SCSR, WordAcc, NoLock, Preserve) { + Offset (0x84), /* PMECTRLSTATUS */ + PMCR, 16, + Offset (0xA2), /* PG_CONFIG */ + , 2, + PGEN, 1, /* PG_ENABLE */ + } + + Method(_INI) { + /* Clear register 0x1C20/0x4820 */ + SCSC (PID_EMMC) + } + + Method(_PS0, 0, Serialized) { + Stall (50) // Sleep 50 us + + PGEN = 0 // Disable PG + + /* Clear register 0x1C20/0x4820 */ + SCSC (PID_EMMC) + + /* Set Power State to D0 */ + PMCR = PMCR & 0xFFFC + TEMP = PMCR + } + + Method(_PS3, 0, Serialized) { + PGEN = 1 // Enable PG + + /* Set Power State to D3 */ + PMCR = PMCR | 0x0003 + TEMP = PMCR + } + + Device (CARD) + { + Name (_ADR, 0x00000008) + Method (_RMV, 0, NotSerialized) + { + Return (0) + } + } + } + + /* SD CARD */ + Device (SDXC) + { + Name (_ADR, 0x00140005) + Name (_DDN, "SD Controller") + Name (TEMP, 0) + Name (DSUU, ToUUID("f6c13ea5-65cd-461f-ab7a-29f7e8d5bd61")) + + OperationRegion (SDPC, PCI_Config, 0x00, 0x100) + Field (SDPC, WordAcc, NoLock, Preserve) + { + Offset (0x84), /* PMECTRLSTATUS */ + PMCR, 16, + Offset (0xA2), /* PG_CONFIG */ + , 2, + PGEN, 1, /* PG_ENABLE */ + } + + /* + * _DSM x86 Device Specific Method + * Arg0: UUID Unique function identifier + * Arg1: Integer Revision Level + * Arg2: Integer Function Index (0 = Return Supported Functions) + * Arg3: Package Parameters + */ + Method (_DSM, 4) + { + If (Arg0 == DSUU) { + /* Check the revision */ + If (Arg1 >= 0) { + /* + * Function Index 0 the return value is a buffer containing + * one bit for each function index, starting with zero. + * Bit 0 - Indicates whether there is support for any + * functions other than function 0. + * Bit 1 - Indicates support to clear power control register + * Bit 2 - Indicates support to set power control register + * Bit 3 - Indicates support to set 1.8V signalling + * Bit 4 - Indicates support to set 3.3V signalling + * Bit 5 - Indicates support for HS200 mode + * Bit 6 - Indicates support for HS400 mode + * Bit 9 - Indicates eMMC I/O Driver Strength + */ + /* + * For SD we have to support functions to + * set 1.8V signalling and 3.3V signalling [BIT4, BIT3] + */ + If (Arg2 == 0) { + Return (Buffer () { 0x19 }) + } + /* + * Function Index 3: Set 1.8v signalling. + * We put a sleep of 100ms in this method to + * work around a known issue with detecting + * UHS SD card on PCH. This is to compensate + * for the SD VR slowness. + */ + If (Arg2 == 3) { + Sleep (100) + Return(Buffer () { 0x00 }) + } + /* + * Function Index 4: Set 3.3v signalling. + * We put a sleep of 100ms in this method to + * work around a known issue with detecting + * UHS SD card on PCH. This is to compensate + * for the SD VR slowness. + */ + If (Arg2 == 4) { + Sleep (100) + Return(Buffer () { 0x00 }) + } + } + } + Return(Buffer() { 0x0 }) + } + + Method(_INI) + { + /* Clear register 0x1C20/0x4820 */ + SCSC (PID_SDX) + } + + Method (_PS0, 0, Serialized) + { + PGEN = 0 /* Disable PG */ + + /* Clear register 0x1C20/0x4820 */ + SCSC (PID_SDX) + + /* Set Power State to D0 */ + PMCR = PMCR & 0xFFFC + TEMP = PMCR + + /* Change pad mode to Native */ + GPMO(SD_PWR_EN_PIN, 0x1) + } + + Method (_PS3, 0, Serialized) + { + PGEN = 1 /* Enable PG */ + + /* Set Power State to D3 */ + PMCR = PMCR | 0x0003 + TEMP = PMCR + + /* Change pad mode to GPIO control */ + GPMO(SD_PWR_EN_PIN, 0x0) + + /* Enable Tx Buffer */ + GTXE(SD_PWR_EN_PIN, 0x1) + + /* Drive TX to zero */ + CTXS(SD_PWR_EN_PIN) + } + + Device (CARD) + { + Name (_ADR, 0x00000008) + Method (_RMV, 0, NotSerialized) + { + Return (1) + } + } + } /* Device (SDXC) */ +} diff --git a/src/soc/intel/elkhartlake/acpi/serialio.asl b/src/soc/intel/elkhartlake/acpi/serialio.asl new file mode 100644 index 0000000..f7bf452 --- /dev/null +++ b/src/soc/intel/elkhartlake/acpi/serialio.asl @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Intel Serial IO Devices */ + +Device (I2C0) +{ + Name (_ADR, 0x00150000) + Name (_DDN, "Serial IO I2C Controller 0") +} + +Device (I2C1) +{ + Name (_ADR, 0x00150001) + Name (_DDN, "Serial IO I2C Controller 1") +} + +Device (I2C2) +{ + Name (_ADR, 0x00150002) + Name (_DDN, "Serial IO I2C Controller 2") +} + +Device (I2C3) +{ + Name (_ADR, 0x00150003) + Name (_DDN, "Serial IO I2C Controller 3") +} + +Device (I2C4) +{ + Name (_ADR, 0x00190000) + Name (_DDN, "Serial IO I2C Controller 4") +} + +Device (I2C5) +{ + Name (_ADR, 0x00190001) + Name (_DDN, "Serial IO I2C Controller 5") +} + +Device (SPI0) +{ + Name (_ADR, 0x001e0002) + Name (_DDN, "Serial IO SPI Controller 0") +} + +Device (SPI1) +{ + Name (_ADR, 0x001e0003) + Name (_DDN, "Serial IO SPI Controller 1") +} + +Device (SPI2) +{ + Name (_ADR, 0x00120006) + Name (_DDN, "Serial IO SPI Controller 2") +} + +Device (SPI3) +{ + Name (_ADR, 0x00130000) + Name (_DDN, "Serial IO SPI Controller 3") +} + +Device (UAR0) +{ + Name (_ADR, 0x001e0000) + Name (_DDN, "Serial IO UART Controller 0") +} + +Device (UAR1) +{ + Name (_ADR, 0x001e0001) + Name (_DDN, "Serial IO UART Controller 1") +} + +Device (UAR2) +{ + Name (_ADR, 0x00190002) + Name (_DDN, "Serial IO UART Controller 2") +} diff --git a/src/soc/intel/elkhartlake/acpi/smbus.asl b/src/soc/intel/elkhartlake/acpi/smbus.asl new file mode 100644 index 0000000..6705f22 --- /dev/null +++ b/src/soc/intel/elkhartlake/acpi/smbus.asl @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Intel SMBus Controller 0:1f.4 */ + +Device (SBUS) +{ + Name (_ADR, 0x001f0004) +} diff --git a/src/soc/intel/elkhartlake/acpi/southbridge.asl b/src/soc/intel/elkhartlake/acpi/southbridge.asl new file mode 100644 index 0000000..fd87469 --- /dev/null +++ b/src/soc/intel/elkhartlake/acpi/southbridge.asl @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <intelblocks/itss.h> +#include <intelblocks/pcr.h> +#include <soc/itss.h> +#include <soc/pcr_ids.h> + +/* PCI IRQ assignment */ +#include "pci_irqs.asl" + +/* PCR access */ +#include <soc/intel/common/acpi/pcr.asl> + +/* GPIO controller */ +#include "gpio.asl" + +/* ESPI 0:1f.0 */ +#include <soc/intel/common/block/acpi/acpi/lpc.asl> + +/* PCH HDA */ +#include "pch_hda.asl" + +/* PCIE Ports */ +#include "pcie.asl" + +/* pmc 0:1f.2 */ +#include "pmc.asl" + +/* Serial IO */ +#include "serialio.asl" + +/* SMBus 0:1f.4 */ +#include "smbus.asl" + +/* USB XHCI 0:14.0 */ +#include "xhci.asl" + +/* PCI _OSC */ +#include <soc/intel/common/acpi/pci_osc.asl> + +/* PMC Core*/ +#include <soc/intel/common/block/acpi/acpi/pmc.asl> + +/* EMMC/SD card */ +#include "scs.asl" diff --git a/src/soc/intel/elkhartlake/acpi/xhci.asl b/src/soc/intel/elkhartlake/acpi/xhci.asl new file mode 100644 index 0000000..445c7db --- /dev/null +++ b/src/soc/intel/elkhartlake/acpi/xhci.asl @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/gpe.h> + +/* XHCI Controller 0:14.0 */ + +Device (XHCI) +{ + Name (_ADR, 0x00140000) + + Name (_PRW, Package () { GPE0_PME_B0, 3 }) + + Name (_S3D, 3) /* D3 supported in S3 */ + Name (_S0W, 3) /* D3 can wake device in S0 */ + Name (_S3W, 3) /* D3 can wake system from S3 */ + + Method (_PS0, 0, Serialized) + { + + } + + Method (_PS3, 0, Serialized) + { + + } + + /* Root Hub for Elkhartlake PCH */ + Device (RHUB) + { + Name (_ADR, Zero) + + /* USB2 */ + Device (HS01) { Name (_ADR, 1) } + Device (HS02) { Name (_ADR, 2) } + Device (HS03) { Name (_ADR, 3) } + Device (HS04) { Name (_ADR, 4) } + Device (HS05) { Name (_ADR, 5) } + Device (HS06) { Name (_ADR, 6) } + Device (HS07) { Name (_ADR, 7) } + Device (HS08) { Name (_ADR, 8) } + + /* USB3 */ + Device (SS01) { Name (_ADR, 9) } + Device (SS02) { Name (_ADR, 10) } + Device (SS03) { Name (_ADR, 11) } + Device (SS04) { Name (_ADR, 12) } + Device (SS05) { Name (_ADR, 13) } + Device (SS06) { Name (_ADR, 14) } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/44812 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e77081d1673cc0ca97edc63e9996c045ab6e9b0 Gerrit-Change-Number: 44812 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-MessageType: newchange

5 11

Change in coreboot[master]: nb/intel/sandybridge: Use an enum for `gpu_panel_port_select`
by Angel Pons (Code Review) 08 Sep '20

08 Sep '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45035 ) Change subject: nb/intel/sandybridge: Use an enum for `gpu_panel_port_select` ...................................................................... nb/intel/sandybridge: Use an enum for `gpu_panel_port_select` All boards currently have backlight on either LVDS or eDP. Change-Id: I878bc7f1ff75a2b82b9556e855aff1d4d03e0268 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/apple/macbookair4_2/devicetree.cb M src/mainboard/asrock/b75pro3-m/devicetree.cb M src/mainboard/google/butterfly/devicetree.cb M src/mainboard/google/link/devicetree.cb M src/mainboard/google/parrot/devicetree.cb M src/mainboard/google/stout/devicetree.cb M src/mainboard/hp/snb_ivb_laptops/devicetree.cb M src/mainboard/lenovo/l520/devicetree.cb M src/mainboard/lenovo/s230u/devicetree.cb M src/mainboard/lenovo/t420/devicetree.cb M src/mainboard/lenovo/t420s/devicetree.cb M src/mainboard/lenovo/t430/devicetree.cb M src/mainboard/lenovo/t430s/devicetree.cb M src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb M src/mainboard/lenovo/t520/devicetree.cb M src/mainboard/lenovo/t530/devicetree.cb M src/mainboard/lenovo/x131e/devicetree.cb M src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb M src/mainboard/lenovo/x220/devicetree.cb M src/mainboard/lenovo/x230/devicetree.cb M src/mainboard/lenovo/x230/variants/x230s/overridetree.cb M src/mainboard/roda/rv11/variants/rv11/devicetree.cb M src/mainboard/roda/rv11/variants/rw11/devicetree.cb M src/mainboard/samsung/lumpy/devicetree.cb M src/northbridge/intel/sandybridge/chip.h 25 files changed, 31 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/45035/1 diff --git a/src/mainboard/apple/macbookair4_2/devicetree.cb b/src/mainboard/apple/macbookair4_2/devicetree.cb index 6e99b63..f6b0176 100644 --- a/src/mainboard/apple/macbookair4_2/devicetree.cb +++ b/src/mainboard/apple/macbookair4_2/devicetree.cb @@ -6,7 +6,7 @@ register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" - register "gpu_panel_port_select" = "1" + register "gpu_panel_port_select" = "PANEL_PORT_DP_A" register "gpu_panel_power_backlight_off_delay" = "2000" register "gpu_panel_power_backlight_on_delay" = "10" register "gpu_panel_power_cycle_delay" = "6" diff --git a/src/mainboard/asrock/b75pro3-m/devicetree.cb b/src/mainboard/asrock/b75pro3-m/devicetree.cb index 678c48b..2fc7c88 100644 --- a/src/mainboard/asrock/b75pro3-m/devicetree.cb +++ b/src/mainboard/asrock/b75pro3-m/devicetree.cb @@ -6,7 +6,7 @@ register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" - register "gpu_panel_port_select" = "0" + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_backlight_off_delay" = "0" register "gpu_panel_power_backlight_on_delay" = "0" register "gpu_panel_power_cycle_delay" = "4" diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index 0c63305..94e5a21 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -7,7 +7,7 @@ # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb index 477cd47..6ce51a3 100644 --- a/src/mainboard/google/link/devicetree.cb +++ b/src/mainboard/google/link/devicetree.cb @@ -6,7 +6,7 @@ register "gpu_dp_d_hotplug" = "0x06" # Enable Panel as eDP and configure power delays - register "gpu_panel_port_select" = "1" # eDP_A + register "gpu_panel_port_select" = "PANEL_PORT_DP_A" register "gpu_panel_power_cycle_delay" = "6" # 500ms register "gpu_panel_power_up_delay" = "2000" # 200ms register "gpu_panel_power_down_delay" = "500" # 50ms diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index c39a399..61e51d0 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -6,7 +6,7 @@ register "gpu_dp_b_hotplug" = "0x06" # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "5" # 400ms register "gpu_panel_power_up_delay" = "500" # 50ms register "gpu_panel_power_down_delay" = "150" # 15ms diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index a03a0a6..bd91506 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -6,7 +6,7 @@ register "gpu_dp_d_hotplug" = "0x06" # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "5" # T4: 400ms register "gpu_panel_power_up_delay" = "400" # T1+T2: 40ms register "gpu_panel_power_down_delay" = "150" # T3: 15ms diff --git a/src/mainboard/hp/snb_ivb_laptops/devicetree.cb b/src/mainboard/hp/snb_ivb_laptops/devicetree.cb index ae99b61..acdd4b3 100644 --- a/src/mainboard/hp/snb_ivb_laptops/devicetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/devicetree.cb @@ -8,7 +8,7 @@ register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" - register "gpu_panel_port_select" = "0" + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_backlight_off_delay" = "2000" register "gpu_panel_power_backlight_on_delay" = "2000" register "gpu_panel_power_cycle_delay" = "5" diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb index 93390c9..bab1d54 100644 --- a/src/mainboard/lenovo/l520/devicetree.cb +++ b/src/mainboard/lenovo/l520/devicetree.cb @@ -4,7 +4,7 @@ register "gpu_dp_b_hotplug" = "0" register "gpu_dp_c_hotplug" = "0" register "gpu_dp_d_hotplug" = "0" - register "gpu_panel_port_select" = "0" + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_backlight_off_delay" = "0" register "gpu_panel_power_backlight_on_delay" = "0" register "gpu_panel_power_cycle_delay" = "0" diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb index 6f4e608..f3b8c27 100644 --- a/src/mainboard/lenovo/s230u/devicetree.cb +++ b/src/mainboard/lenovo/s230u/devicetree.cb @@ -4,7 +4,7 @@ register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" - register "gpu_panel_port_select" = "0" + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_backlight_off_delay" = "2000" register "gpu_panel_power_backlight_on_delay" = "2000" register "gpu_panel_power_cycle_delay" = "5" diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index 5ac9cf5..ef40fc4 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -6,7 +6,7 @@ register "gpu_dp_d_hotplug" = "0x06" # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "1" register "gpu_panel_power_up_delay" = "300" # T1+T2: 30ms register "gpu_panel_power_down_delay" = "300" # T5+T6: 30ms diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index b3399c3..71068d0 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -6,7 +6,7 @@ register "gpu_dp_d_hotplug" = "0x06" # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "1" register "gpu_panel_power_up_delay" = "300" # T1+T2: 30ms register "gpu_panel_power_down_delay" = "300" # T5+T6: 30ms diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index 95eaa99..f3524cd 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -5,7 +5,7 @@ register "gpu_dp_d_hotplug" = "0x06" # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index 40c706e..4bdb923 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -5,7 +5,7 @@ register "gpu_dp_d_hotplug" = "0x06" # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms diff --git a/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb b/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb index ae95e6c..41bef2f 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb +++ b/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb @@ -5,7 +5,7 @@ register "gpu_dp_d_hotplug" = "4" # Enable Panel as eDP and configure power delays - register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_port_select" = "PANEL_PORT_DP_A" register "gpu_panel_power_up_delay" = "2000" # 200ms register "gpu_panel_power_down_delay" = "500" # 50ms register "gpu_panel_power_backlight_on_delay" = "1" # 0.1ms diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index 5128d06..cc1e7f2 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -6,7 +6,7 @@ register "gpu_dp_d_hotplug" = "0x06" # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "5" register "gpu_panel_power_up_delay" = "300" # T1+T2: 30ms register "gpu_panel_power_down_delay" = "300" # T5+T6: 30ms diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index 1b16ca3..e4655b2 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -6,7 +6,7 @@ register "gpu_dp_d_hotplug" = "0x06" # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index c84d7ea..ddbfd98 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -5,7 +5,7 @@ register "gpu_dp_d_hotplug" = "0x04" # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "4" register "gpu_panel_power_up_delay" = "100" register "gpu_panel_power_down_delay" = "100" diff --git a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb index b3c11ea..34eaa75 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb +++ b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb @@ -4,7 +4,7 @@ register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" - register "gpu_panel_port_select" = "0" + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_backlight_off_delay" = "2000" register "gpu_panel_power_backlight_on_delay" = "3000" register "gpu_panel_power_cycle_delay" = "6" diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index bfb9da3..609036d 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -6,7 +6,7 @@ register "gpu_dp_d_hotplug" = "0x06" # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "5" register "gpu_panel_power_up_delay" = "300" # T1+T2: 30ms register "gpu_panel_power_down_delay" = "300" # T5+T6: 30ms diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 085b4e1..27d42b6 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -6,7 +6,7 @@ register "gpu_dp_d_hotplug" = "0x06" # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms diff --git a/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb b/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb index 9e9d956..b2d0cf2 100644 --- a/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb +++ b/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb @@ -5,7 +5,7 @@ register "gpu_dp_d_hotplug" = "4" # Enable Panel as eDP and configure power delays - register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_port_select" = "PANEL_PORT_DP_A" register "gpu_panel_power_backlight_off_delay" = "1" # 0.1ms register "gpu_panel_power_backlight_on_delay" = "1" # 0.1ms register "gpu_panel_power_down_delay" = "500" # 50ms diff --git a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb index 0a96edf..f3108db 100644 --- a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb @@ -6,7 +6,7 @@ register "gfx.did" = "{ 0x80000400, 0x80000300, 0x80000100, }" # Enable Panel as eDP and configure power delays - register "gpu_panel_port_select" = "1" # eDP_A + register "gpu_panel_port_select" = "PANEL_PORT_DP_A" register "gpu_panel_power_cycle_delay" = "6" # 500ms register "gpu_panel_power_up_delay" = "2000" # 200ms register "gpu_panel_power_down_delay" = "500" # 50ms diff --git a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb index 988c2a6..a1edcaa3 100644 --- a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb @@ -6,7 +6,7 @@ register "gfx.did" = "{ 0x80000400, 0x80000300, 0x80000301, 0x80000100, }" # Enable Panel as eDP and configure power delays - register "gpu_panel_port_select" = "1" # eDP_A + register "gpu_panel_port_select" = "PANEL_PORT_DP_A" register "gpu_panel_power_cycle_delay" = "6" # 500ms register "gpu_panel_power_up_delay" = "2000" # 200ms register "gpu_panel_power_down_delay" = "500" # 50ms diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index 15bff4b..06efaf8 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -6,7 +6,7 @@ register "gpu_dp_d_hotplug" = "0x06" # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "5" # T4: 400ms register "gpu_panel_power_up_delay" = "400" # T1+T2: 40ms register "gpu_panel_power_down_delay" = "150" # T3: 15ms diff --git a/src/northbridge/intel/sandybridge/chip.h b/src/northbridge/intel/sandybridge/chip.h index 98baaa2..824af3e 100644 --- a/src/northbridge/intel/sandybridge/chip.h +++ b/src/northbridge/intel/sandybridge/chip.h @@ -19,7 +19,13 @@ u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */ u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */ - u8 gpu_panel_port_select; /* 0=LVDS 1=DP_B 2=DP_C 3=DP_D */ + enum { + PANEL_PORT_LVDS = 0, + PANEL_PORT_DP_A = 1, /* Also known as eDP */ + PANEL_PORT_DP_C = 2, + PANEL_PORT_DP_D = 3, + } gpu_panel_port_select; + u8 gpu_panel_power_cycle_delay; /* T4 time sequence */ u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */ u16 gpu_panel_power_down_delay; /* T3 time sequence */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45035 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I878bc7f1ff75a2b82b9556e855aff1d4d03e0268 Gerrit-Change-Number: 45035 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: nb/intel/ironlake: Use an enum for `gpu_panel_port_select`
by Angel Pons (Code Review) 08 Sep '20

08 Sep '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45036 ) Change subject: nb/intel/ironlake: Use an enum for `gpu_panel_port_select` ...................................................................... nb/intel/ironlake: Use an enum for `gpu_panel_port_select` The PRM does not describe the relevant bits, but Linux's i915 driver handles these bits the same way for both Ironlake and Sandy Bridge. Change-Id: Ice7412e335752bd7e297ad50f685effcefbd41d2 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/lenovo/t410/devicetree.cb M src/mainboard/lenovo/x201/devicetree.cb M src/mainboard/packardbell/ms2290/devicetree.cb M src/northbridge/intel/ironlake/chip.h 4 files changed, 10 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/45036/1 diff --git a/src/mainboard/lenovo/t410/devicetree.cb b/src/mainboard/lenovo/t410/devicetree.cb index 2de774d..af770dc 100644 --- a/src/mainboard/lenovo/t410/devicetree.cb +++ b/src/mainboard/lenovo/t410/devicetree.cb @@ -8,7 +8,7 @@ register "gpu_dp_d_hotplug" = "0x06" # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "1" register "gpu_panel_power_up_delay" = "1" register "gpu_panel_power_down_delay" = "600" diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index d374cec..6b6543d 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -9,7 +9,7 @@ register "gpu_dp_d_hotplug" = "0x06" # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "3" register "gpu_panel_power_up_delay" = "250" register "gpu_panel_power_down_delay" = "250" diff --git a/src/mainboard/packardbell/ms2290/devicetree.cb b/src/mainboard/packardbell/ms2290/devicetree.cb index 50e648f..b57b3fe 100644 --- a/src/mainboard/packardbell/ms2290/devicetree.cb +++ b/src/mainboard/packardbell/ms2290/devicetree.cb @@ -9,7 +9,7 @@ register "gpu_dp_d_hotplug" = "0x04" # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "6" register "gpu_panel_power_up_delay" = "300" register "gpu_panel_power_down_delay" = "300" diff --git a/src/northbridge/intel/ironlake/chip.h b/src/northbridge/intel/ironlake/chip.h index c437b72..b2976bc 100644 --- a/src/northbridge/intel/ironlake/chip.h +++ b/src/northbridge/intel/ironlake/chip.h @@ -17,7 +17,13 @@ u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */ u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */ - u8 gpu_panel_port_select; /* 0=LVDS 1=DP_B 2=DP_C 3=DP_D */ + enum { + PANEL_PORT_LVDS = 0, + PANEL_PORT_DP_A = 1, /* Also known as eDP */ + PANEL_PORT_DP_C = 2, + PANEL_PORT_DP_D = 3, + } gpu_panel_port_select; + u8 gpu_panel_power_cycle_delay; /* T4 time sequence */ u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */ u16 gpu_panel_power_down_delay; /* T3 time sequence */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45036 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice7412e335752bd7e297ad50f685effcefbd41d2 Gerrit-Change-Number: 45036 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: cpu/x86: Add definition for SMRR_PHYS_MASK_LOCK
by Tim Wawrzynczak (Code Review) 08 Sep '20

08 Sep '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44991 ) Change subject: cpu/x86: Add definition for SMRR_PHYS_MASK_LOCK ...................................................................... cpu/x86: Add definition for SMRR_PHYS_MASK_LOCK The IA32_SMRR_PHYS_MASK MSR contains a 'Lock' bit, which will cause the core to generate a #GP if the SMRR_BASE or SMRR_MASK registers are written to after the Lock bit is set; this is helpful with securing SMM. BUG=b:164489598 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I784d1d1abec0a0fe0ee267118d084ac594a51647 --- M src/include/cpu/x86/mtrr.h 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/44991/1 diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 42964b0..6e30199 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -30,6 +30,7 @@ #define IA32_SMRR_PHYS_BASE 0x1f2 #define IA32_SMRR_PHYS_MASK 0x1f3 +#define SMRR_PHYS_MASK_LOCK (1 << 10) /* Specific to model_6fx and model_1067x */ #define MSR_SMRR_PHYS_BASE 0xa0 -- To view, visit https://review.coreboot.org/c/coreboot/+/44991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I784d1d1abec0a0fe0ee267118d084ac594a51647 Gerrit-Change-Number: 44991 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

6 5

Change in coreboot[master]: soc/intel/broadwell: Drop `gpu_panel_port_select`
by Angel Pons (Code Review) 08 Sep '20

08 Sep '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45033 ) Change subject: soc/intel/broadwell: Drop `gpu_panel_port_select` ...................................................................... soc/intel/broadwell: Drop `gpu_panel_port_select` The corresponding bits in PP_ON_DELAYS are reserved MBZ. Change-Id: I9789a7d50c4bce2ccad0bf476f877db25e3ff82e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/auron/variants/auron_paine/overridetree.cb M src/mainboard/google/auron/variants/auron_yuna/overridetree.cb M src/mainboard/google/auron/variants/buddy/overridetree.cb M src/mainboard/google/auron/variants/gandof/overridetree.cb M src/mainboard/google/auron/variants/lulu/overridetree.cb M src/mainboard/google/auron/variants/samus/overridetree.cb M src/mainboard/purism/librem_bdw/devicetree.cb M src/soc/intel/broadwell/chip.h M src/soc/intel/broadwell/igd.c 9 files changed, 7 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/45033/1 diff --git a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb index 70b1ebd..60aef30 100644 --- a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb +++ b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb @@ -1,7 +1,6 @@ chip soc/intel/broadwell - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP + # Set panel power delays register "gpu_panel_power_cycle_delay" = "5" # 400ms register "gpu_panel_power_up_delay" = "400" # 40ms register "gpu_panel_power_down_delay" = "150" # 15ms diff --git a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb index 67b9131..da80fec 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb +++ b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb @@ -1,7 +1,6 @@ chip soc/intel/broadwell - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP + # Set panel power delays register "gpu_panel_power_cycle_delay" = "5" # 400ms register "gpu_panel_power_up_delay" = "400" # 40ms register "gpu_panel_power_down_delay" = "150" # 15ms diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb index f814280..f148964 100644 --- a/src/mainboard/google/auron/variants/buddy/overridetree.cb +++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb @@ -1,7 +1,6 @@ chip soc/intel/broadwell - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP + # Set panel power delays register "gpu_panel_power_cycle_delay" = "5" # 400ms register "gpu_panel_power_up_delay" = "400" # 40ms register "gpu_panel_power_down_delay" = "150" # 15ms diff --git a/src/mainboard/google/auron/variants/gandof/overridetree.cb b/src/mainboard/google/auron/variants/gandof/overridetree.cb index e35d3a5..75c202d 100644 --- a/src/mainboard/google/auron/variants/gandof/overridetree.cb +++ b/src/mainboard/google/auron/variants/gandof/overridetree.cb @@ -1,7 +1,6 @@ chip soc/intel/broadwell - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP + # Set panel power delays register "gpu_panel_power_cycle_delay" = "5" # 400ms register "gpu_panel_power_up_delay" = "400" # 40ms register "gpu_panel_power_down_delay" = "150" # 15ms diff --git a/src/mainboard/google/auron/variants/lulu/overridetree.cb b/src/mainboard/google/auron/variants/lulu/overridetree.cb index 70b1ebd..60aef30 100644 --- a/src/mainboard/google/auron/variants/lulu/overridetree.cb +++ b/src/mainboard/google/auron/variants/lulu/overridetree.cb @@ -1,7 +1,6 @@ chip soc/intel/broadwell - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP + # Set panel power delays register "gpu_panel_power_cycle_delay" = "5" # 400ms register "gpu_panel_power_up_delay" = "400" # 40ms register "gpu_panel_power_down_delay" = "150" # 15ms diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb index 93e96ca..c5d2747 100644 --- a/src/mainboard/google/auron/variants/samus/overridetree.cb +++ b/src/mainboard/google/auron/variants/samus/overridetree.cb @@ -3,8 +3,7 @@ # Enable DDI2 Hotplug with 6ms pulse register "gpu_dp_c_hotplug" = "0x06" - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP + # Set panel power delays register "gpu_panel_power_cycle_delay" = "6" # 500ms register "gpu_panel_power_up_delay" = "2000" # 200ms register "gpu_panel_power_down_delay" = "500" # 50ms diff --git a/src/mainboard/purism/librem_bdw/devicetree.cb b/src/mainboard/purism/librem_bdw/devicetree.cb index 0d44cd7..b7c6fe5 100644 --- a/src/mainboard/purism/librem_bdw/devicetree.cb +++ b/src/mainboard/purism/librem_bdw/devicetree.cb @@ -9,8 +9,7 @@ # Set backlight PWM value for eDP register "gpu_pch_backlight_pwm_hz" = "200" - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP + # Set panel power delays register "gpu_panel_power_cycle_delay" = "6" # 500ms register "gpu_panel_power_up_delay" = "2000" # 200ms register "gpu_panel_power_down_delay" = "500" # 50ms diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h index 5543998..f559410 100644 --- a/src/soc/intel/broadwell/chip.h +++ b/src/soc/intel/broadwell/chip.h @@ -84,7 +84,6 @@ u8 gpu_dp_d_hotplug; /* Panel power sequence timings */ - u8 gpu_panel_port_select; u8 gpu_panel_power_cycle_delay; u16 gpu_panel_power_up_delay; u16 gpu_panel_power_down_delay; diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index 41167b1..ba453cdb2 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -298,7 +298,6 @@ /* Setup Panel Power On Delays */ reg32 = gtt_read(PCH_PP_ON_DELAYS); if (!reg32) { - reg32 = (conf->gpu_panel_port_select & 0x3) << 30; reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16; reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); gtt_write(PCH_PP_ON_DELAYS, reg32); -- To view, visit https://review.coreboot.org/c/coreboot/+/45033 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9789a7d50c4bce2ccad0bf476f877db25e3ff82e Gerrit-Change-Number: 45033 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: sandybridge/northbridge.c: Add FIXME for unused tolud
by HAOUAS Elyes (Code Review) 08 Sep '20

08 Sep '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45166 ) Change subject: sandybridge/northbridge.c: Add FIXME for unused tolud ...................................................................... sandybridge/northbridge.c: Add FIXME for unused tolud "tolud" is incremented but not used. Change-Id: If1e3f55b34ea1213d38c55effa96644e3acefa7e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/sandybridge/northbridge.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/45166/1 diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index e670c09..c3e8465 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -201,6 +201,7 @@ /* ME is from MEBASE-TOM */ uma_size = (tom - me_base) >> 10; /* Increment TOLUD to account for ME as RAM */ + /* FIXME: tolud is not used */ tolud += uma_size << 10; /* UMA starts at old TOLUD */ uma_memory_base = tomk * 1024ULL; -- To view, visit https://review.coreboot.org/c/coreboot/+/45166 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1e3f55b34ea1213d38c55effa96644e3acefa7e Gerrit-Change-Number: 45166 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/google/volteer: config QS silicon devices for CSE LITE
by Mark Hsieh (Code Review) 08 Sep '20

08 Sep '20

Mark Hsieh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45018 ) Change subject: mb/google/volteer: config QS silicon devices for CSE LITE ...................................................................... mb/google/volteer: config QS silicon devices for CSE LITE Configure eldrid to use CSE Lite. BUG=b:158140797 TEST=cd to volteer's asset_generation folder, execute "./gen_all_variant_images.sh" and verify that all variant images are produced. Signed-off-by: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Change-Id: I357abdac4102f358d3aa1cb50f600312039ef140 --- M src/mainboard/google/volteer/Kconfig.name 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/45018/1 diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index 1d9a3db..1980dd5 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -8,6 +8,7 @@ config BOARD_GOOGLE_ELDRID bool "-> Eldrid" select BOARD_GOOGLE_BASEBOARD_VOLTEER + select SOC_INTEL_CSE_LITE_SKU config BOARD_GOOGLE_HALVOR bool "-> Halvor" -- To view, visit https://review.coreboot.org/c/coreboot/+/45018 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I357abdac4102f358d3aa1cb50f600312039ef140 Gerrit-Change-Number: 45018 Gerrit-PatchSet: 1 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

5 5

Change in coreboot[master]: mb/../Kconfig: Correct the maximum number of cpu cores for APL platform
by Mario Scheithauer (Code Review) 08 Sep '20

08 Sep '20

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45063 ) Change subject: mb/../Kconfig: Correct the maximum number of cpu cores for APL platform ...................................................................... mb/../Kconfig: Correct the maximum number of cpu cores for APL platform With reference to abandoned patch 43818: [WIP] soc/intel/apollolake: Drop select SMP | https://review.coreboot.org/c/coreboot/+/43818, the maximum number of cores for APL platform is herewith fixed. Change-Id: I555ab72520ab9c174b1656c463a5112eb05a236d Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/google/reef/Kconfig M src/mainboard/intel/apollolake_rvp/Kconfig M src/mainboard/intel/leafhill/Kconfig M src/mainboard/intel/minnow3/Kconfig M src/mainboard/siemens/mc_apl1/Kconfig 5 files changed, 15 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/45063/1 diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index df1d8c4..de4df62 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -83,7 +83,7 @@ config MAX_CPUS int - default 8 + default 4 config UART_FOR_CONSOLE int diff --git a/src/mainboard/intel/apollolake_rvp/Kconfig b/src/mainboard/intel/apollolake_rvp/Kconfig index dfd86eb..93f5e94 100644 --- a/src/mainboard/intel/apollolake_rvp/Kconfig +++ b/src/mainboard/intel/apollolake_rvp/Kconfig @@ -17,4 +17,9 @@ config UART_FOR_CONSOLE default 2 + +config MAX_CPUS + int + default 4 + endif diff --git a/src/mainboard/intel/leafhill/Kconfig b/src/mainboard/intel/leafhill/Kconfig index 652a659..ce8f0da 100644 --- a/src/mainboard/intel/leafhill/Kconfig +++ b/src/mainboard/intel/leafhill/Kconfig @@ -69,4 +69,8 @@ string default "fspm.bin" +config MAX_CPUS + int + default 4 + endif # BOARD_INTEL_LEAFHILL diff --git a/src/mainboard/intel/minnow3/Kconfig b/src/mainboard/intel/minnow3/Kconfig index 0c86df6..6c202e0 100644 --- a/src/mainboard/intel/minnow3/Kconfig +++ b/src/mainboard/intel/minnow3/Kconfig @@ -69,4 +69,8 @@ string default "fspm.bin" +config MAX_CPUS + int + default 4 + endif # BOARD_INTEL_MINNOW3 diff --git a/src/mainboard/siemens/mc_apl1/Kconfig b/src/mainboard/siemens/mc_apl1/Kconfig index 0fe4a25..705351f 100644 --- a/src/mainboard/siemens/mc_apl1/Kconfig +++ b/src/mainboard/siemens/mc_apl1/Kconfig @@ -42,6 +42,6 @@ config MAX_CPUS int - default 8 + default 4 endif # BOARD_SIEMENS_BASEBOARD_MC_APL1 -- To view, visit https://review.coreboot.org/c/coreboot/+/45063 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I555ab72520ab9c174b1656c463a5112eb05a236d Gerrit-Change-Number: 45063 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: newchange

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