coreboot-gerrit September 2020

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Change in coreboot[master]: mainboard/google/volteer: Enable long cr50 ready pulses
by Jes Klinke (Code Review) 08 Sep '20

08 Sep '20

Hello Jes Klinke, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44359 to review the following change. Change subject: mainboard/google/volteer: Enable long cr50 ready pulses ...................................................................... mainboard/google/volteer: Enable long cr50 ready pulses For Volteer (and future Tiger Lake boards) we can enable mode S0i3.4 only if we know that the Cr50 is generating 100us interrupt pulses. We have to do so, because the SoC is not guaranteed to detect pulses shorter than 100us in S0i3.4 substate. A new Kconfig setting CR50_USE_LONG_INTERRUPT_PULSES controls new code running in verstage, which will program a new Cr50 register, provided that Cr50 firmware is new enough to support the register. Change-Id: Idef1fffd410a345678da4b3c8aea46ac74a01470 Signed-off-by: Jes Bodi Klinke <jbk(a)chromium.org> Bug: b:154333137 --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/chromeos.c M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 3 files changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/44359/1 diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 82edb82..8eedca1 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -58,6 +58,10 @@ config DRIVER_TPM_SPI_BUS default 0x1 +config CR50_USE_LONG_INTERRUPT_PULSES + bool + default y + config MAINBOARD_DIR string default "google/volteer" diff --git a/src/mainboard/google/volteer/chromeos.c b/src/mainboard/google/volteer/chromeos.c index abd50c5..8f43071 100644 --- a/src/mainboard/google/volteer/chromeos.c +++ b/src/mainboard/google/volteer/chromeos.c @@ -2,7 +2,10 @@ #include <baseboard/variants.h> #include <boot/coreboot_tables.h> +#include <drivers/spi/tpm/tpm.h> #include <gpio.h> +#include <security/tpm/tss.h> +#include <soc/ramstage.h> #include <variant/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -32,3 +35,18 @@ gpios = variant_cros_gpios(&num); chromeos_acpi_gpio_generate(gpios, num); } + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + tlcl_lib_init(); + if (get_cr50_board_cfg() & 0x01) { + printk(BIOS_INFO, "Enabling S0i3.4\n"); + } else { + /* Disable S03.4, preventing the GPIO block from switching to + * slow clock. */ + printk(BIOS_INFO, "Not enabling S0i3.4\n"); + params->LpmStateEnableMask &= ~0x80; + } +} + + diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 53bbe5a..6004c1d 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -203,6 +203,7 @@ # Enable S0ix register "s0ix_enable" = "1" + register "LpmStateEnableMask" = "0xFF" # Enable DPTF register "dptf_enable" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/44359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idef1fffd410a345678da4b3c8aea46ac74a01470 Gerrit-Change-Number: 44359 Gerrit-PatchSet: 1 Gerrit-Owner: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Jes Klinke <jbk(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib/Kconfig: Drop obsolete help text from GENERIC_SPD_BIN
by Patrick Georgi (Code Review) 08 Sep '20

08 Sep '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45145 ) Change subject: lib/Kconfig: Drop obsolete help text from GENERIC_SPD_BIN ...................................................................... lib/Kconfig: Drop obsolete help text from GENERIC_SPD_BIN SMBus code is linked unconditionally since commit 0e3c59e. This change drops that obsolete part from the help text. Change-Id: I603ab012760684021be1b5eca5d0ddff69463b79 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45145 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/lib/Kconfig 1 file changed, 1 insertion(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/lib/Kconfig b/src/lib/Kconfig index a6fb1f1..d91ec58 100644 --- a/src/lib/Kconfig +++ b/src/lib/Kconfig @@ -34,8 +34,7 @@ bool help If enabled, add support for adding spd.hex files in cbfs as spd.bin - and locating it runtime to load SPD. Additionally provide provision to - fetch SPD over SMBus. + and locating it runtime to load SPD. config DIMM_MAX int -- To view, visit https://review.coreboot.org/c/coreboot/+/45145 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I603ab012760684021be1b5eca5d0ddff69463b79 Gerrit-Change-Number: 45145 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: util/spd_tools: output binaries instead of hexdumps
by Patrick Georgi (Code Review) 08 Sep '20

08 Sep '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44878 ) Change subject: util/spd_tools: output binaries instead of hexdumps ...................................................................... util/spd_tools: output binaries instead of hexdumps Instead of generating hexdumps, output binary SPD files since we plan to convert all hex SPD files to binary. Also adjust the file extension where needed. Test: compared generated binaries with converted binaries from hex files Change-Id: Ie99d108ca90758d09dbefad20fe6c9f7fc263ef1 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44878 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/spd_tools/ddr4/README.md M util/spd_tools/ddr4/gen_part_id.go M util/spd_tools/ddr4/gen_spd.go M util/spd_tools/lp4x/README.md M util/spd_tools/lp4x/gen_spd.go 5 files changed, 39 insertions(+), 47 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/util/spd_tools/ddr4/README.md b/util/spd_tools/ddr4/README.md index 7527544..c78b06f 100644 --- a/util/spd_tools/ddr4/README.md +++ b/util/spd_tools/ddr4/README.md @@ -171,7 +171,7 @@ This tool generates the following files using the global list of memory parts in JSON format as described above: * De-duplicated SPDs required for the different memory parts. These - SPD files are named (ddr4-spd-1.hex, ddr4-spd-2.hex, and so on) + SPD files are named (ddr4-spd-1.bin, ddr4-spd-2.bin, and so on) and placed in the directory provided as an input to the tool. * CSV file representing which of the deduplicated SPD files is used by which memory part. This file is named as @@ -179,11 +179,11 @@ as an input to the tool along with the generated SPD files. Example CSV file: ``` - MEMORY_PART_A, ddr4-spd-1.hex - MEMORY_PART_B, ddr4-spd-2.hex - MEMORY_PART_C, ddr4-spd-3.hex - MEMORY_PART_D, ddr4-spd-2.hex - MEMORY_PART_E, ddr4-spd-2.hex + MEMORY_PART_A, ddr4-spd-1.bin + MEMORY_PART_B, ddr4-spd-2.bin + MEMORY_PART_C, ddr4-spd-3.bin + MEMORY_PART_D, ddr4-spd-2.bin + MEMORY_PART_E, ddr4-spd-2.bin ``` ## Tool 2 - gen_part_id.go @@ -242,10 +242,10 @@ ## This is an auto-generated file. Do not edit!! SPD_SOURCES = -SPD_SOURCES += ddr4-spd-1.hex # ID = 0(0b0000) Parts = MEMORY_PART_A -SPD_SOURCES += ddr4-spd-2.hex # ID = 1(0b0001) Parts = MEMORY_PART_B, MEMORY_PART_D -SPD_SOURCES += ddr4-spd-empty.hex # ID = 2(0b0010) -SPD_SOURCES += ddr4-spd-3.hex # ID = 2(0b0010) Parts = MEMORY_PART_C +SPD_SOURCES += ddr4-spd-1.bin # ID = 0(0b0000) Parts = MEMORY_PART_A +SPD_SOURCES += ddr4-spd-2.bin # ID = 1(0b0001) Parts = MEMORY_PART_B, MEMORY_PART_D +SPD_SOURCES += ddr4-spd-empty.bin # ID = 2(0b0010) +SPD_SOURCES += ddr4-spd-3.bin # ID = 2(0b0010) Parts = MEMORY_PART_C ``` NOTE: Empty entries may be required if there is a gap created by a memory part with a fixed id. diff --git a/util/spd_tools/ddr4/gen_part_id.go b/util/spd_tools/ddr4/gen_part_id.go index c0098ab..29b91fa 100644 --- a/util/spd_tools/ddr4/gen_part_id.go +++ b/util/spd_tools/ddr4/gen_part_id.go @@ -265,7 +265,7 @@ for i := 0; i < len(partIdList); i++ { if partIdList[i].SPDFileName == "" { - s += fmt.Sprintf("SPD_SOURCES += %s ", "ddr4-spd-empty.hex") + s += fmt.Sprintf("SPD_SOURCES += %s ", "ddr4-spd-empty.bin") s += fmt.Sprintf(" # ID = %d(0b%04b)\n", i, int64(i)) } else { s += fmt.Sprintf("SPD_SOURCES += %s ", partIdList[i].SPDFileName) diff --git a/util/spd_tools/ddr4/gen_spd.go b/util/spd_tools/ddr4/gen_spd.go index 3c8f71a..b60ab03 100644 --- a/util/spd_tools/ddr4/gen_spd.go +++ b/util/spd_tools/ddr4/gen_spd.go @@ -3,6 +3,7 @@ package main import ( + "bytes" "encoding/json" "fmt" "io/ioutil" @@ -968,8 +969,8 @@ return e.constVal } -func createSPD(memAttribs *memAttributes) string { - var s string +func createSPD(memAttribs *memAttributes) bytes.Buffer { + var spd bytes.Buffer for i := 0; i < 512; i++ { var b byte = 0 @@ -977,14 +978,10 @@ b = getSPDByte(i, memAttribs) } - if (i + 1) % 16 == 0 { - s += fmt.Sprintf("%02X\n", b) - } else { - s += fmt.Sprintf("%02X ", b) - } + spd.WriteByte(b) } - return s + return spd } func dedupeMemoryPart(dedupedParts []*memPart, memPart *memPart) bool { @@ -999,16 +996,16 @@ } func generateSPD(memPart *memPart, SPDId int, SPDDirName string) { - s := createSPD(&memPart.Attribs) - memPart.SPDFileName = fmt.Sprintf("ddr4-spd-%d.hex", SPDId) - ioutil.WriteFile(filepath.Join(SPDDirName, memPart.SPDFileName), []byte(s), 0644) + spd := createSPD(&memPart.Attribs) + memPart.SPDFileName = fmt.Sprintf("ddr4-spd-%d.bin", SPDId) + ioutil.WriteFile(filepath.Join(SPDDirName, memPart.SPDFileName), spd.Bytes(), 0644) } func generateEmptySPD(SPDDirName string) { - s := createSPD(nil) - SPDFileName := "ddr4-spd-empty.hex" - ioutil.WriteFile(filepath.Join(SPDDirName, SPDFileName), []byte(s), 0644) + spd := createSPD(nil) + SPDFileName := "ddr4-spd-empty.bin" + ioutil.WriteFile(filepath.Join(SPDDirName, SPDFileName), spd.Bytes(), 0644) } func readMemoryParts(memParts *memParts, memPartsFileName string) error { diff --git a/util/spd_tools/lp4x/README.md b/util/spd_tools/lp4x/README.md index e614f25..0c49dad 100644 --- a/util/spd_tools/lp4x/README.md +++ b/util/spd_tools/lp4x/README.md @@ -168,7 +168,7 @@ This tool generates the following files using the global list of memory parts in JSON format as described above: * De-duplicated SPDs required for the different memory parts. These - SPD files are named (spd_1.hex, spd_2.hex, spd_3.hex and so on) + SPD files are named (spd_1.bin, spd_2.bin, spd_3.bin and so on) and placed in the directory provided as an input to the tool. * CSV file representing which of the deduplicated SPD files is used by which memory part. This file is named as @@ -176,11 +176,11 @@ as an input to the tool along with the generated SPD files. Example CSV file: ``` - MEMORY_PART_A, spd_1.hex - MEMORY_PART_B, spd_2.hex - MEMORY_PART_C, spd_3.hex - MEMORY_PART_D, spd_2.hex - MEMORY_PART_E, spd_2.hex + MEMORY_PART_A, spd_1.bin + MEMORY_PART_B, spd_2.bin + MEMORY_PART_C, spd_3.bin + MEMORY_PART_D, spd_2.bin + MEMORY_PART_E, spd_2.bin ``` ## Tool 2 - gen_part_id.go @@ -222,9 +222,9 @@ ## This is an auto-generated file. Do not edit!! SPD_SOURCES = -SPD_SOURCES += spd_1.hex # ID = 0(0b0000) Parts = MEMORY_PART_A -SPD_SOURCES += spd_2.hex # ID = 1(0b0001) Parts = MEMORY_PART_B, MEMORY_PART_D -SPD_SOURCES += spd_3.hex # ID = 2(0b0010) Parts = MEMORY_PART_C +SPD_SOURCES += spd_1.bin # ID = 0(0b0000) Parts = MEMORY_PART_A +SPD_SOURCES += spd_2.bin # ID = 1(0b0001) Parts = MEMORY_PART_B, MEMORY_PART_D +SPD_SOURCES += spd_3.bin # ID = 2(0b0010) Parts = MEMORY_PART_C ``` ### Note of caution diff --git a/util/spd_tools/lp4x/gen_spd.go b/util/spd_tools/lp4x/gen_spd.go index e63ca8d..1738833 100644 --- a/util/spd_tools/lp4x/gen_spd.go +++ b/util/spd_tools/lp4x/gen_spd.go @@ -3,6 +3,7 @@ package main import ( + "bytes" "encoding/json" "fmt" "io/ioutil" @@ -637,20 +638,14 @@ return e.constVal } -func createSPD(memAttribs *memAttributes) string { - var s string +func createSPD(memAttribs *memAttributes) bytes.Buffer { + var spd bytes.Buffer for i := 0; i < 512; i++ { - b := getSPDByte(i, memAttribs) - - if (i + 1) % 16 == 0 { - s += fmt.Sprintf("%02X\n", b) - } else { - s += fmt.Sprintf("%02X ", b) - } + spd.WriteByte(getSPDByte(i, memAttribs)) } - return s + return spd } func dedupeMemoryPart(dedupedParts []*memPart, memPart *memPart) bool { @@ -665,9 +660,9 @@ } func generateSPD(memPart *memPart, SPDId int, SPDDirName string) { - s := createSPD(&memPart.Attribs) - memPart.SPDFileName = fmt.Sprintf("lp4x-spd-%d.hex", SPDId) - ioutil.WriteFile(filepath.Join(SPDDirName, memPart.SPDFileName), []byte(s), 0644) + spd := createSPD(&memPart.Attribs) + memPart.SPDFileName = fmt.Sprintf("lp4x-spd-%d.bin", SPDId) + ioutil.WriteFile(filepath.Join(SPDDirName, memPart.SPDFileName), spd.Bytes(), 0644) } func readMemoryParts(memParts *memParts, memPartsFileName string) error { -- To view, visit https://review.coreboot.org/c/coreboot/+/44878 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie99d108ca90758d09dbefad20fe6c9f7fc263ef1 Gerrit-Change-Number: 44878 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: util/spd_tools: output binaries instead of hexdumps
by Patrick Georgi (Code Review) 08 Sep '20

08 Sep '20

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44878 ) Change subject: util/spd_tools: output binaries instead of hexdumps ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/44878 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie99d108ca90758d09dbefad20fe6c9f7fc263ef1 Gerrit-Change-Number: 44878 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 08 Sep 2020 05:46:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/apcb_edit: fix handling of binary SPD files
by Patrick Georgi (Code Review) 08 Sep '20

08 Sep '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44778 ) Change subject: util/apcb_edit: fix handling of binary SPD files ...................................................................... util/apcb_edit: fix handling of binary SPD files Passing binary SPD files to apcb_edit can lead to an encoding error, since the files were read in text mode. To fix this, read SPD files always in binary mode and only decode them, when `--hex` is set. Tested by comparing output files from the same SPDs in both, binary and hex mode. Change-Id: I6b75a9e1234e71667bdc8cb4eb10daf8c0ac3c17 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44778 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Rob Barnes <robbarnes(a)google.com> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M util/apcb/apcb_edit.py 1 file changed, 5 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Nico Huber: Looks good to me, but someone else must approve Angel Pons: Looks good to me, but someone else must approve Rob Barnes: Looks good to me, but someone else must approve diff --git a/util/apcb/apcb_edit.py b/util/apcb/apcb_edit.py index 388b18a..599ef35 100755 --- a/util/apcb/apcb_edit.py +++ b/util/apcb/apcb_edit.py @@ -40,19 +40,19 @@ help='APCB output file') parser.add_argument( '--spd_0_0', - type=argparse.FileType('r'), + type=argparse.FileType('rb'), help='SPD input file for channel 0, dimm 0') parser.add_argument( '--spd_0_1', - type=argparse.FileType('r'), + type=argparse.FileType('rb'), help='SPD input file for channel 0, dimm 1') parser.add_argument( '--spd_1_0', - type=argparse.FileType('r'), + type=argparse.FileType('rb'), help='SPD input file for channel 1, dimm 0') parser.add_argument( '--spd_1_1', - type=argparse.FileType('r'), + type=argparse.FileType('rb'), help='SPD input file for channel 1, dimm 1') parser.add_argument( '--hex', @@ -150,11 +150,10 @@ if spd: if args.hex: + spd = spd.decode() spd = re.sub(r'#.*', '', spd) spd = re.sub(r'\s+', '', spd) spd = bytes.fromhex(spd) - else: - spd = spd.encode() assert len(spd) == 512, \ "Expected SPD to be 512 bytes, got %d" % len(spd) -- To view, visit https://review.coreboot.org/c/coreboot/+/44778 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b75a9e1234e71667bdc8cb4eb10daf8c0ac3c17 Gerrit-Change-Number: 44778 Gerrit-PatchSet: 11 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: util/apcb_edit: fix handling of binary SPD files
by Patrick Georgi (Code Review) 08 Sep '20

08 Sep '20

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44778 ) Change subject: util/apcb_edit: fix handling of binary SPD files ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/44778 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b75a9e1234e71667bdc8cb4eb10daf8c0ac3c17 Gerrit-Change-Number: 44778 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 08 Sep 2020 05:44:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/ocp/deltalake: Add SMBIOS OEM string for SPD register vendor ID
by Patrick Georgi (Code Review) 08 Sep '20

08 Sep '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44545 ) Change subject: mb/ocp/deltalake: Add SMBIOS OEM string for SPD register vendor ID ...................................................................... mb/ocp/deltalake: Add SMBIOS OEM string for SPD register vendor ID Tested=On OCP Delta Lake, with FSP WW36 dmidecode -t 11 can see the SPD register vendor ID String 7: b300 0000 b300 0000 b300 0000 b300 0000 b300 0000 b300 0000 Change-Id: I15ab9b4c709eb97a03d6e08fe0bcdcb7f8607db0 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44545 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/ocp/deltalake/ramstage.c 1 file changed, 27 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index 89d466b..e00f1c3 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <assert.h> #include <console/console.h> #include <bootstate.h> #include <drivers/ipmi/ipmi_ops.h> @@ -7,6 +8,7 @@ #include <gpio.h> #include <soc/lewisburg_pch_gpio_defs.h> #include <soc/ramstage.h> +#include <soc/soc_util.h> #include <stdio.h> #include <string.h> #include <smbios.h> @@ -14,6 +16,7 @@ #include <device/pci_ops.h> #include <soc/util.h> #include <hob_iiouds.h> +#include <hob_memmap.h> #include <cpxsp_dl_gpio.h> #include "ipmi.h" @@ -67,15 +70,37 @@ {PSTACK2, SlotTypePciExpressGen3X16, SlotDataBusWidth16X, 0x00, "Mezz Card(Class-2)"}, }; +#define SPD_REGVID_LEN 6 +/* A 4-digit long number plus a space */ +static void write_oem_word(uint16_t val, char *str) +{ + snprintf(str, SPD_REGVID_LEN, "%04x ", val); +} + static void dl_oem_smbios_strings(struct device *dev, struct smbios_type11 *t) { uint8_t pcie_config = 0; + const struct SystemMemoryMapHob *hob; + char spd_reg_vid[SPD_REGVID_LEN]; + char empty[1] = ""; + char *oem_str7 = empty; /* OEM string 1 to 6 */ ocp_oem_smbios_strings(dev, t); - /* TODO: Add real OEM string 7, add TBF for now */ - t->count = smbios_add_oem_string(t->eos, TBF); + /* OEM string 7 is the register vendor ID in SPD for each DIMM strung together */ + hob = get_system_memory_map(); + assert(hob != NULL); + /* There are at most 6 channels and 2 DIMMs per channel, but Delta Lake has 6 DIMMs, + e.g. b300 0000 b300 0000 b300 0000 b300 0000 b300 0000 b300 0000 */ + for (int ch = 0; ch < MAX_CH; ch++) { + for (int dimm = 0; dimm < MAX_IMC; dimm++) { + write_oem_word(hob->Socket[0].ChannelInfo[ch].DimmInfo[dimm].SPDRegVen, + spd_reg_vid); + oem_str7 = strconcat(oem_str7, spd_reg_vid); + } + } + t->count = smbios_add_oem_string(t->eos, oem_str7); /* Add OEM string 8 */ if (ipmi_get_pcie_config(&pcie_config) == CB_SUCCESS) { -- To view, visit https://review.coreboot.org/c/coreboot/+/44545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15ab9b4c709eb97a03d6e08fe0bcdcb7f8607db0 Gerrit-Change-Number: 44545 Gerrit-PatchSet: 9 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek/mt8192: Add SPI flash controller dual read function
by CK HU (Code Review) 08 Sep '20

08 Sep '20

CK HU has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44852 ) Change subject: soc/mediatek/mt8192: Add SPI flash controller dual read function ...................................................................... soc/mediatek/mt8192: Add SPI flash controller dual read function Support SPI flash dual read funciton which change spi mode (1-1-1) to dual mode (1-1-2). Signed-off-by: CK Hu <ck.hu(a)mediatek.com> Change-Id: Iabd3668fc4bc42137b7743144fc1cced4fe72737 --- M src/soc/mediatek/mt8192/flash_controller.c M src/soc/mediatek/mt8192/include/soc/flash_controller.h 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/44852/1 diff --git a/src/soc/mediatek/mt8192/flash_controller.c b/src/soc/mediatek/mt8192/flash_controller.c index 0c37ae5..d1e5acb 100644 --- a/src/soc/mediatek/mt8192/flash_controller.c +++ b/src/soc/mediatek/mt8192/flash_controller.c @@ -144,6 +144,9 @@ size_t dma_buf_len = REGION_SIZE(dma_coherent); u32 next; + setbits8(&mt8192_nor->read_dual, SFLASH_READ_DUAL_EN); + write8(&mt8192_nor->prgdata[3], SFLASH_1_1_2_READ); + if (!IS_ALIGNED((uintptr_t)addr, SFLASH_DMA_ALIGN)) { next = MIN(ALIGN_UP((uintptr_t)addr, SFLASH_DMA_ALIGN) - (uintptr_t)addr, len); diff --git a/src/soc/mediatek/mt8192/include/soc/flash_controller.h b/src/soc/mediatek/mt8192/include/soc/flash_controller.h index 5655a9c..16e1c31 100644 --- a/src/soc/mediatek/mt8192/include/soc/flash_controller.h +++ b/src/soc/mediatek/mt8192/include/soc/flash_controller.h @@ -7,6 +7,9 @@ #include <stdint.h> #include <soc/addressmap.h> +#define SFLASH_READ_DUAL_EN 0x1 +#define SFLASH_1_1_2_READ 0x3B + enum { SFLASH_POLLINGREG_US = 500000, SFLASH_WRBUF_SIZE = 128, -- To view, visit https://review.coreboot.org/c/coreboot/+/44852 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabd3668fc4bc42137b7743144fc1cced4fe72737 Gerrit-Change-Number: 44852 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: vendorcode/intel/FSP2_0/CPX-SP: update to ww36
by Jonathan Zhang (Code Review) 08 Sep '20

08 Sep '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45100 ) Change subject: vendorcode/intel/FSP2_0/CPX-SP: update to ww36 ...................................................................... vendorcode/intel/FSP2_0/CPX-SP: update to ww36 Intel CPX-SP FSP ww36 release has following changes: * Updates FSP header version to change among FSP releases. * Added SPDRegVen field in memory map HOB, to facilitate SMBIOS type 11 (OEM strings) generation. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: I7a8dab3987c2f8f471b40f7b3b9ced0c2909271d --- M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h 2 files changed, 11 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/45100/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h index 02bab70..d892c9a 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h @@ -370,16 +370,18 @@ **/ UINT32 mmiohBase; -/** Offset 0x0098 - High Gap +/** Offset 0x0098 - CPU Physical Address Limit + CPU Physical Address Limit + 0:Disable, 1:Enable +**/ + UINT8 CpuPaLimit; + +/** Offset 0x0099 - High Gap Enable or Disable High Gap $EN_DIS **/ UINT8 highGap; -/** Offset 0x0099 -**/ - UINT8 UnusedUpdSpace0; - /** Offset 0x009A - MMIO High Size MMIO High Size, Number of 1GB contiguous regions to be assigned for MMIOH space per CPU. Range 1-1024 @@ -400,7 +402,7 @@ /** Offset 0x009E **/ - UINT8 UnusedUpdSpace1[2]; + UINT8 UnusedUpdSpace0[2]; /** Offset 0x00A0 - } TYPE:{Combo Enable or Disable @@ -723,7 +725,7 @@ /** Offset 0x015C **/ - UINT8 UnusedUpdSpace2[2]; + UINT8 UnusedUpdSpace1[2]; /** Offset 0x015E **/ diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h index 79c4162..1230fd0 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h @@ -45,6 +45,7 @@ #define MAX_IMC 2 #define MAX_CH 6 #define MC_MAX_NODE (MAX_SOCKET * MAX_IMC) +#define MAX_CHA_MAP 4 // Maximum KTI PORTS to be used in structure definition #if (MAX_SOCKET == 1) @@ -147,7 +148,7 @@ uint16_t M2PciePresentBitmap; uint8_t TotM3Kti; uint8_t TotCha; - uint32_t ChaList; + uint32_t ChaList[MAX_CHA_MAP]; uint32_t SocId; QPI_PEER_DATA PeerInfo[MAX_FW_KTI_PORTS]; // QPI LEP info } QPI_CPU_DATA; -- To view, visit https://review.coreboot.org/c/coreboot/+/45100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a8dab3987c2f8f471b40f7b3b9ced0c2909271d Gerrit-Change-Number: 45100 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/system76/lemp9: update HDA pin config
by Jeremy Soller (Code Review) 08 Sep '20

08 Sep '20

Jeremy Soller has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43631 ) Change subject: mb/system76/lemp9: update HDA pin config ...................................................................... mb/system76/lemp9: update HDA pin config To minimize the quirks the kernel has to apply, the headset mic is set to its correct value in coreboot. Tested on lemp9, audio is functional Signed-off-by: Jeremy Soller <jeremy(a)system76.com> Change-Id: I6b59de95f01360a5f7779f87f39edeb75dedc215 --- M src/mainboard/system76/lemp9/hda_verb.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/43631/1 diff --git a/src/mainboard/system76/lemp9/hda_verb.c b/src/mainboard/system76/lemp9/hda_verb.c index 3f77dc2..7bb0736 100644 --- a/src/mainboard/system76/lemp9/hda_verb.c +++ b/src/mainboard/system76/lemp9/hda_verb.c @@ -15,7 +15,7 @@ AZALIA_PIN_CFG(0, 0x16, 0x411111f0), AZALIA_PIN_CFG(0, 0x18, 0x411111f0), AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x01a1913c), AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), AZALIA_PIN_CFG(0, 0x1d, 0x41748245), AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), -- To view, visit https://review.coreboot.org/c/coreboot/+/43631 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b59de95f01360a5f7779f87f39edeb75dedc215 Gerrit-Change-Number: 43631 Gerrit-PatchSet: 1 Gerrit-Owner: Jeremy Soller <jeremy(a)system76.com> Gerrit-MessageType: newchange

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