coreboot-gerrit September 2020

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Change in coreboot[master]: mb/siemens/chili: Add Chili variant
by build bot (Jenkins) (Code Review) 08 Sep '20

08 Sep '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39995 ) Change subject: mb/siemens/chili: Add Chili variant ...................................................................... Patch Set 14: (4 comments) https://review.coreboot.org/c/coreboot/+/39995/14/src/mainboard/siemens/chi… File src/mainboard/siemens/chili/romstage.c: https://review.coreboot.org/c/coreboot/+/39995/14/src/mainboard/siemens/chi… PS14, Line 46: __weak void variant_romstage_params(FSPM_UPD *const mupd) need consistent spacing around '*' (ctx:WxV) https://review.coreboot.org/c/coreboot/+/39995/14/src/mainboard/siemens/chi… File src/mainboard/siemens/chili/variants/chili/gpio.c: https://review.coreboot.org/c/coreboot/+/39995/14/src/mainboard/siemens/chi… PS14, Line 44: /* GPP_G3 GPIO 0x0000006f40880102 */ PAD_CFG_GPI_APIC(GPP_G3, NONE, DEEP, LEVEL, INVERT), line over 96 characters https://review.coreboot.org/c/coreboot/+/39995/14/src/mainboard/siemens/chi… PS14, Line 49: /* GPD7 GPIO 0x0000006704000200 */ PAD_NC(GPD7, DN_20K), /* unused, formerly USB always on */ line over 96 characters https://review.coreboot.org/c/coreboot/+/39995/14/src/mainboard/siemens/chi… PS14, Line 95: /* GPP_F18 GPIO 0x0000004240880102 */ PAD_CFG_GPI_APIC(GPP_F18, NONE, DEEP, LEVEL, INVERT), line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/39995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7a5dccbb0d5b7bceb154fb050cf991254475f7b Gerrit-Change-Number: 39995 Gerrit-PatchSet: 14 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 08 Sep 2020 15:17:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/siemens/chili: Add Chili variant
by Felix Singer (Code Review) 08 Sep '20

08 Sep '20

Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39995 to look at the new patch set (#14). Change subject: mb/siemens/chili: Add Chili variant ...................................................................... mb/siemens/chili: Add Chili variant * Update GMA Port_List for Chili variant * Comment Chili-variant devicetree * Add option to disable `ethernet1` * Implement preliminary fan config for Chili * Slightly adjust fan control of Chili * Set HWM limits and tune fan config of Chili * Revise Chili's PCI devices Mention onboard PCI devices explicitly, disable unused `debug` PCIe root port and reorder other root ports according to coalescing rules. * Add bx26rom support for Chili * Configure EC device enablement Individual bits are based on observation of the original BIOS. For the Chili variant, add a Kconfig option to enable the debug USB port. * Add HDA verbs for Chili * Move mainboard_init() (GPIO config) to romstage * Update devicetrees wrt. SlotImplemented * Update Chili's fan config * Ignore mic presence on Chili Change-Id: Ic7a5dccbb0d5b7bceb154fb050cf991254475f7b Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Signed-off-by: Felix Singer <felix.singer(a)secunet.com> --- M src/mainboard/siemens/chili/Kconfig M src/mainboard/siemens/chili/Kconfig.name M src/mainboard/siemens/chili/mainboard.c M src/mainboard/siemens/chili/romstage.c M src/mainboard/siemens/chili/variant.h A src/mainboard/siemens/chili/variants/chili/Makefile.inc A src/mainboard/siemens/chili/variants/chili/board_info.txt A src/mainboard/siemens/chili/variants/chili/boxer26_eeprom.h A src/mainboard/siemens/chili/variants/chili/data.vbt A src/mainboard/siemens/chili/variants/chili/devicetree.cb A src/mainboard/siemens/chili/variants/chili/gma-mainboard.ads A src/mainboard/siemens/chili/variants/chili/gpio.c A src/mainboard/siemens/chili/variants/chili/hda_verb.c A src/mainboard/siemens/chili/variants/chili/romstage.c A src/mainboard/siemens/chili/variants/chili/smbios.c 15 files changed, 672 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/39995/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/39995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7a5dccbb0d5b7bceb154fb050cf991254475f7b Gerrit-Change-Number: 39995 Gerrit-PatchSet: 14 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/ifdtool: Add NULL check for pointer fpsba
by Subrata Banik (Code Review) 08 Sep '20

08 Sep '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45130 ) Change subject: util/ifdtool: Add NULL check for pointer fpsba ...................................................................... util/ifdtool: Add NULL check for pointer fpsba This patch adds NULL check inside get_ifd_version_from_fcba() function to fix Klocwork issue. BUG=b:153888802 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Change-Id: I525054376b36c658b93760b185ef6dd170f5aea9 --- M util/ifdtool/ifdtool.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/45130/1 diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index e2fd0ab..fab034a 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -265,7 +265,7 @@ const fcba_t *fcba = find_fcba(image, size); const fdbar_t *fdb = find_fd(image, size); const fpsba_t *fpsba = find_fpsba(image, size); - if (!fcba || !fdb) + if (!fcba || !fdb || !fpsba) exit(EXIT_FAILURE); chipset = guess_ich_chipset(fdb, fpsba); -- To view, visit https://review.coreboot.org/c/coreboot/+/45130 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I525054376b36c658b93760b185ef6dd170f5aea9 Gerrit-Change-Number: 45130 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: Add DIMM definition in SystemMemoryMapHob
by Johnny Lin (Code Review) 08 Sep '20

08 Sep '20

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44847 ) Change subject: soc/intel/xeon_sp/cpx: Add DIMM definition in SystemMemoryMapHob ...................................................................... soc/intel/xeon_sp/cpx: Add DIMM definition in SystemMemoryMapHob Most of them are needed for SMBIOS type 17 creation. Tested=With FSP WW34 added with SPDRegVen DIMM member, verified the printed hob values match with FSP hob data. Change-Id: I02f4600f1be39e2576d7c84a5a6b6672ebb7034b Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h 1 file changed, 48 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/44847/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h index f85c4ff..50ead77 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h @@ -58,6 +58,9 @@ #define MEM_TYPE_RESERVED (1 << 8) #define MEM_ADDR_64MB_SHIFT_BITS 26 +#define NGN_MAX_SERIALNUMBER_STRLEN 4 +#define NGN_MAX_PARTNUMBER_STRLEN 20 +#define NGN_FW_VER_LEN 4 // // System Memory Map HOB information // @@ -85,6 +88,46 @@ UINT32 ElementSize; } SYSTEM_MEMORY_MAP_ELEMENT; +typedef struct DimmDevice { + UINT8 reserved1[2]; + UINT8 DcpmmPresent; + UINT8 reserved2[1]; + UINT8 NumRanks; + UINT8 reserved3[1]; + UINT8 actKeyByte2; + UINT8 reserved4[4]; + UINT16 nonVolCap; + UINT16 DimmSize; + UINT8 reserved5[4]; + UINT16 SPDMMfgId; // Module Mfg Id from SPD + UINT16 VendorID; + UINT16 DeviceID; + UINT8 reserved6[22]; + UINT8 serialNumber[NGN_MAX_SERIALNUMBER_STRLEN]; // Serial Number + UINT8 PartNumber[NGN_MAX_PARTNUMBER_STRLEN]; // Part Number + UINT8 FirmwareVersionStr[NGN_FW_VER_LEN]; // Used to update the SMBIOS TYPE 17 + UINT8 reserved7[23]; + UINT16 SubsystemVendorID; + UINT16 SubsystemDeviceID; + UINT8 reserved8[4]; + UINT8 DimmSku; // Dimm SKU info + UINT8 reserved9[3]; + INT32 commonTck; + UINT8 EnergyType; + UINT8 reserved10[1]; + UINT16 SPDRegVen; // Register Vendor ID in SPD +} MEMMAP_DIMM_DEVICE_INFO_STRUCT; + +struct ChannelDevice { + UINT8 reserved1[15]; + MEMMAP_DIMM_DEVICE_INFO_STRUCT DimmInfo[MAX_IMC]; +}; + +typedef struct socket { + UINT8 reserved1[1110]; + struct ChannelDevice ChannelInfo[MAX_CH]; +} MEMMAP_SOCKET; + /* NOTE - Reserved sizes need to be calibrated if any of the above #define values change */ typedef struct SystemMemoryMapHob { UINT8 reserved1[61]; @@ -101,16 +144,17 @@ UINT8 NumChPerMC; UINT8 numberEntries; // Number of Memory Map Elements SYSTEM_MEMORY_MAP_ELEMENT Element[(MAX_SOCKET * MAX_DRAM_CLUSTERS * MAX_SAD_RULES) + MAX_FPGA_REMOTE_SAD_RULES]; - - UINT8 reserved3[24551]; + UINT8 reserved3[2212]; + MEMMAP_SOCKET Socket[MAX_SOCKET]; + UINT8 reserved4[1603]; UINT16 BiosFisVersion; // Firmware Interface Specification version currently supported by BIOS - UINT8 reserved4[24]; + UINT8 reserved5[24]; UINT32 MmiohBase; // MMIOH base in 64MB granularity - UINT8 reserved5[2]; + UINT8 reserved6[2]; } SYSTEM_MEMORY_MAP_HOB; -- To view, visit https://review.coreboot.org/c/coreboot/+/44847 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02f4600f1be39e2576d7c84a5a6b6672ebb7034b Gerrit-Change-Number: 44847 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: pci_ids: Add ADL DTT PCI IDs
by Subrata Banik (Code Review) 08 Sep '20

08 Sep '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45140 ) Change subject: pci_ids: Add ADL DTT PCI IDs ...................................................................... pci_ids: Add ADL DTT PCI IDs Add PCI IDs for Intel's Dynamic Tuning Technology (DTT) for ADL Change-Id: If25b1f562567a833683b0b8796bd1d6cac0bd490 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/dtt/dtt.c 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/45140/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index dd0df54..675775f 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3972,6 +3972,7 @@ #define PCI_DEVICE_ID_INTEL_CML_DTT 0x1903 #define PCI_DEVICE_ID_INTEL_TGL_DTT 0x9A03 #define PCI_DEVICE_ID_INTEL_JSL_DTT 0x4E03 +#define PCI_DEVICE_ID_INTEL_ADL_DTT 0x461d #define PCI_VENDOR_ID_COMPUTONE 0x8e0e #define PCI_DEVICE_ID_COMPUTONE_IP2EX 0x0291 diff --git a/src/soc/intel/common/block/dtt/dtt.c b/src/soc/intel/common/block/dtt/dtt.c index d92eb15..58afd74 100644 --- a/src/soc/intel/common/block/dtt/dtt.c +++ b/src/soc/intel/common/block/dtt/dtt.c @@ -8,6 +8,8 @@ PCI_DEVICE_ID_INTEL_CML_DTT, PCI_DEVICE_ID_INTEL_TGL_DTT, PCI_DEVICE_ID_INTEL_JSL_DTT, + PCI_DEVICE_ID_INTEL_ADL_DTT, + 0 }; static struct device_operations dptf_dev_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/45140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If25b1f562567a833683b0b8796bd1d6cac0bd490 Gerrit-Change-Number: 45140 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: pci_ids: Add ADL IPU PCI IDs
by Subrata Banik (Code Review) 08 Sep '20

08 Sep '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45139 ) Change subject: pci_ids: Add ADL IPU PCI IDs ...................................................................... pci_ids: Add ADL IPU PCI IDs Add PCI IDs for Intel's Image Processing Unit (IPU) for ADL Change-Id: I327828d676422fc6162fadffd9b39529ecb89ace Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/ipu/ipu.c 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/45139/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 5aaf7b3..dd0df54 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3966,6 +3966,7 @@ #define PCI_DEVICE_ID_INTEL_TGL_IPU 0x9a19 #define PCI_DEVICE_ID_INTEL_JSL_IPU 0x4e19 +#define PCI_DEVICE_ID_INTEL_ADL_IPU 0x465d /* Intel Dynamic Tuning Technology Device */ #define PCI_DEVICE_ID_INTEL_CML_DTT 0x1903 diff --git a/src/soc/intel/common/block/ipu/ipu.c b/src/soc/intel/common/block/ipu/ipu.c index f7b01aa..844d88e 100644 --- a/src/soc/intel/common/block/ipu/ipu.c +++ b/src/soc/intel/common/block/ipu/ipu.c @@ -14,6 +14,8 @@ static const uint16_t pci_device_ids[] = { PCI_DEVICE_ID_INTEL_TGL_IPU, PCI_DEVICE_ID_INTEL_JSL_IPU, + PCI_DEVICE_ID_INTEL_ADL_IPU, + 0 }; static const struct pci_driver intel_ipu __pci_driver = { -- To view, visit https://review.coreboot.org/c/coreboot/+/45139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I327828d676422fc6162fadffd9b39529ecb89ace Gerrit-Change-Number: 45139 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/system76/lemp9: enable eDP in Fsp
by Michael Niewöhner (Code Review) 08 Sep '20

08 Sep '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45126 ) Change subject: mb/system76/lemp9: enable eDP in Fsp ...................................................................... Patch Set 6: Code-Review-1 I found a better way... more info soon :P -- To view, visit https://review.coreboot.org/c/coreboot/+/45126 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice5f55e07ea9e028a0b6a904511eb59830351738 Gerrit-Change-Number: 45126 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 08 Sep 2020 12:17:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/Kconfig: Fix path to "c_start.S"
by HAOUAS Elyes (Code Review) 08 Sep '20

08 Sep '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45152 ) Change subject: src/Kconfig: Fix path to "c_start.S" ...................................................................... src/Kconfig: Fix path to "c_start.S" commit 6cb3a59f renamed arch/x86/lib/c_start.S to arch/x86/c_start.S Change-Id: Ib92fb9b73ee85835e40d30ba8573ea5fd13a09e4 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/45152/1 diff --git a/src/Kconfig b/src/Kconfig index d6b703b..6739867 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -808,7 +808,7 @@ depends on DRIVERS_UART help If enabled, you will be able to set breakpoints for gdb debugging. - See src/arch/x86/lib/c_start.S for details. + See src/arch/x86/c_start.S for details. config GDB_WAIT bool "Wait for a GDB connection in the ramstage" -- To view, visit https://review.coreboot.org/c/coreboot/+/45152 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib92fb9b73ee85835e40d30ba8573ea5fd13a09e4 Gerrit-Change-Number: 45152 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/system76/lemp9: enable eDP in Fsp
by Paul Menzel (Code Review) 08 Sep '20

08 Sep '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45126 ) Change subject: mb/system76/lemp9: enable eDP in Fsp ...................................................................... Patch Set 6: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/45126/6//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45126/6//COMMIT_MSG@7 PS6, Line 7: Fsp FSP -- To view, visit https://review.coreboot.org/c/coreboot/+/45126 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice5f55e07ea9e028a0b6a904511eb59830351738 Gerrit-Change-Number: 45126 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 08 Sep 2020 10:49:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Update SA & PM related variables
by Lean Sheng Tan (Code Review) 08 Sep '20

08 Sep '20

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45077 ) Change subject: soc/intel/elkhartlake: Update SA & PM related variables ...................................................................... soc/intel/elkhartlake: Update SA & PM related variables 1. Update SA base address & size 2. Update GBE control bit register value Signed-off-by: Tan, Lean Sheng <lean.sheng.tan(a)intel.com> Change-Id: I1f5036c9cd75682fcf239170bcb257ffaa002e7d --- M src/soc/intel/elkhartlake/include/soc/iomap.h M src/soc/intel/elkhartlake/include/soc/pm.h 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/45077/1 diff --git a/src/soc/intel/elkhartlake/include/soc/iomap.h b/src/soc/intel/elkhartlake/include/soc/iomap.h index 5ba40bc..0246673 100644 --- a/src/soc/intel/elkhartlake/include/soc/iomap.h +++ b/src/soc/intel/elkhartlake/include/soc/iomap.h @@ -47,8 +47,8 @@ #define VTD_BASE_ADDRESS 0xfed90000 #define VTD_BASE_SIZE 0x00004000 -#define MCH_BASE_ADDRESS 0xfea80000 -#define MCH_BASE_SIZE 0x8000 +#define MCH_BASE_ADDRESS 0xfec80000 +#define MCH_BASE_SIZE 0x80000 #define EARLY_GSPI_BASE_ADDRESS 0xfe011000 diff --git a/src/soc/intel/elkhartlake/include/soc/pm.h b/src/soc/intel/elkhartlake/include/soc/pm.h index 11d6663..6ebbbfa 100644 --- a/src/soc/intel/elkhartlake/include/soc/pm.h +++ b/src/soc/intel/elkhartlake/include/soc/pm.h @@ -65,7 +65,7 @@ #define SMI_ON_SLP_EN_STS_BIT 4 #define LEGACY_USB_STS_BIT 3 #define BIOS_STS_BIT 2 -#define GPE_CNTL 0x42 +#define GPE_CNTL 0x40 #define SWGPE_CTRL (1 << 1) #define DEVACT_STS 0x44 #define PM2_CNT 0x50 -- To view, visit https://review.coreboot.org/c/coreboot/+/45077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f5036c9cd75682fcf239170bcb257ffaa002e7d Gerrit-Change-Number: 45077 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit September 2020