coreboot-gerrit September 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/baytrail: Add missing GSM size definitions
by Angel Pons (Code Review) 08 Sep '20

08 Sep '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44935 ) Change subject: soc/intel/baytrail: Add missing GSM size definitions ...................................................................... soc/intel/baytrail: Add missing GSM size definitions Change-Id: I456591f63f463c5cec1cbf3c1633bdb61be92d29 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/baytrail/include/soc/gfx.h 1 file changed, 16 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/44935/1 diff --git a/src/soc/intel/baytrail/include/soc/gfx.h b/src/soc/intel/baytrail/include/soc/gfx.h index e809631..c3a362b 100644 --- a/src/soc/intel/baytrail/include/soc/gfx.h +++ b/src/soc/intel/baytrail/include/soc/gfx.h @@ -14,10 +14,22 @@ # define GGC_GTT_SIZE_1MB (1 << 8) # define GGC_GTT_SIZE_2MB (2 << 8) # define GGC_GSM_SIZE_MASK (0x1f << 3) -# define GGC_GSM_SIZE_0MB (0 << 3) -# define GGC_GSM_SIZE_32MB (1 << 3) -# define GGC_GSM_SIZE_64MB (2 << 3) -# define GGC_GSM_SIZE_128MB (4 << 3) +# define GGC_GSM_SIZE_0MB (0 << 3) +# define GGC_GSM_SIZE_32MB (1 << 3) +# define GGC_GSM_SIZE_64MB (2 << 3) +# define GGC_GSM_SIZE_96MB (3 << 3) +# define GGC_GSM_SIZE_128MB (4 << 3) +# define GGC_GSM_SIZE_160MB (5 << 3) +# define GGC_GSM_SIZE_192MB (6 << 3) +# define GGC_GSM_SIZE_224MB (7 << 3) +# define GGC_GSM_SIZE_256MB (8 << 3) +# define GGC_GSM_SIZE_288MB (9 << 3) +# define GGC_GSM_SIZE_320MB (10 << 3) +# define GGC_GSM_SIZE_352MB (11 << 3) +# define GGC_GSM_SIZE_384MB (12 << 3) +# define GGC_GSM_SIZE_416MB (13 << 3) +# define GGC_GSM_SIZE_448MB (14 << 3) +# define GGC_GSM_SIZE_480MB (15 << 3) #define GSM_BASE 0x5c #define GTT_BASE 0x70 -- To view, visit https://review.coreboot.org/c/coreboot/+/44935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I456591f63f463c5cec1cbf3c1633bdb61be92d29 Gerrit-Change-Number: 44935 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/denverton_ns/Kconfig: Drop unused 'IQAT_MEMORY_REGION_SIZE'
by HAOUAS Elyes (Code Review) 08 Sep '20

08 Sep '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45069 ) Change subject: soc/intel/denverton_ns/Kconfig: Drop unused 'IQAT_MEMORY_REGION_SIZE' ...................................................................... soc/intel/denverton_ns/Kconfig: Drop unused 'IQAT_MEMORY_REGION_SIZE' Change-Id: I25cfc61b7a25b68dd22573a88933e03931a755ef Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/denverton_ns/Kconfig 1 file changed, 0 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/45069/1 diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 3fce223..33635b3 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -120,13 +120,6 @@ bool "Enable IQAT" default y -config IQAT_MEMORY_REGION_SIZE - depends on IQAT_ENABLE - hex - default 0x100000 - help - Do not change this value - config HSUART_DEV hex default 0x1a -- To view, visit https://review.coreboot.org/c/coreboot/+/45069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25cfc61b7a25b68dd22573a88933e03931a755ef Gerrit-Change-Number: 45069 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: mb/asus/a88xm-e/Kconfig: Correct 'HUDSON_XHCI_ENABLE' symbol
by HAOUAS Elyes (Code Review) 08 Sep '20

08 Sep '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45068 ) Change subject: mb/asus/a88xm-e/Kconfig: Correct 'HUDSON_XHCI_ENABLE' symbol ...................................................................... mb/asus/a88xm-e/Kconfig: Correct 'HUDSON_XHCI_ENABLE' symbol Change-Id: Ibe8844db74b43009e7c49df78882ed76b0bbebae Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/asus/a88xm-e/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/45068/1 diff --git a/src/mainboard/asus/a88xm-e/Kconfig b/src/mainboard/asus/a88xm-e/Kconfig index 6874e9e..17fbe28 100644 --- a/src/mainboard/asus/a88xm-e/Kconfig +++ b/src/mainboard/asus/a88xm-e/Kconfig @@ -48,7 +48,7 @@ string default "1002,990e" -config CONFIG_HUDSON_XHCI_ENABLE +config HUDSON_XHCI_ENABLE bool default n -- To view, visit https://review.coreboot.org/c/coreboot/+/45068 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe8844db74b43009e7c49df78882ed76b0bbebae Gerrit-Change-Number: 45068 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/opencellular/elgon/Kconfig: Drop unused 'MAINBOARD_FIT_DTS'
by HAOUAS Elyes (Code Review) 08 Sep '20

08 Sep '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45067 ) Change subject: mb/opencellular/elgon/Kconfig: Drop unused 'MAINBOARD_FIT_DTS' ...................................................................... mb/opencellular/elgon/Kconfig: Drop unused 'MAINBOARD_FIT_DTS' Change-Id: Ie084f93998dc16450bb3db99d7240905bed3d50e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/opencellular/elgon/Kconfig 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/45067/1 diff --git a/src/mainboard/opencellular/elgon/Kconfig b/src/mainboard/opencellular/elgon/Kconfig index 94d677b..06c2a49 100644 --- a/src/mainboard/opencellular/elgon/Kconfig +++ b/src/mainboard/opencellular/elgon/Kconfig @@ -72,8 +72,4 @@ string default "Elgon" -config MAINBOARD_FIT_DTS - string - default "gbcv2.dts" - endif -- To view, visit https://review.coreboot.org/c/coreboot/+/45067 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie084f93998dc16450bb3db99d7240905bed3d50e Gerrit-Change-Number: 45067 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: fsp/fsp2_0/cooperlake_sp: Set correct PSTACK number for IOU3
by Johnny Lin (Code Review) 08 Sep '20

08 Sep '20

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45022 ) Change subject: fsp/fsp2_0/cooperlake_sp: Set correct PSTACK number for IOU3 ...................................................................... fsp/fsp2_0/cooperlake_sp: Set correct PSTACK number for IOU3 CPX FSP PSTACK2 (IOU3) is stack number 4. Change-Id: I1c9e49bbc9a00de82d1fc67b3b4ed47e03eacdda Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h 1 file changed, 10 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/45022/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h index 79c4162..0f5b33f 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h @@ -111,13 +111,20 @@ } PCIE_PORTS; /** - IIO Stacks - **/ + * IIO Stacks + * + * Ports Stack Stack(HOB) IioConfigIou + * ================================================= + * 0 CSTACK stack 0 IOU0 + * 1A..1D PSTACK0 stack 1 IOU1 + * 2A..2D PSTACK1 stack 2 IOU2 + * 3A..3D PSTACK2 stack 4 IOU3 + */ typedef enum { CSTACK = 0, PSTACK0, PSTACK1, - PSTACK2, + PSTACK2 = 4, MAX_STACKS } IIO_STACKS; -- To view, visit https://review.coreboot.org/c/coreboot/+/45022 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c9e49bbc9a00de82d1fc67b3b4ed47e03eacdda Gerrit-Change-Number: 45022 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/drawcia: Configure I2C high and low time
by Karthik Ramasubramanian (Code Review) 08 Sep '20

08 Sep '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45084 ) Change subject: mb/google/dedede/var/drawcia: Configure I2C high and low time ...................................................................... mb/google/dedede/var/drawcia: Configure I2C high and low time Configure the I2C bus high and low time for all enabled I2C buses. BUG=b:162232776 TEST=Measured the I2C bus frequency as 389 KHz, high time as 870 ns and low time as 1580 ns. Change-Id: I67d2725a7fc8d83e3fa8a56cfa86540c4e6f0971 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 1 file changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/45084/1 diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index faded0e..395dee3 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -24,18 +24,36 @@ }, .i2c[0] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, .i2c[1] = { .speed = I2C_SPEED_FAST, }, .i2c[2] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, .i2c[3] = { .speed = I2C_SPEED_FAST, }, .i2c[4] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, }" -- To view, visit https://review.coreboot.org/c/coreboot/+/45084 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67d2725a7fc8d83e3fa8a56cfa86540c4e6f0971 Gerrit-Change-Number: 45084 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: mb/google/dedede/var/waddledee: Configure I2C high and low time
by Karthik Ramasubramanian (Code Review) 08 Sep '20

08 Sep '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45083 ) Change subject: mb/google/dedede/var/waddledee: Configure I2C high and low time ...................................................................... mb/google/dedede/var/waddledee: Configure I2C high and low time Configure the I2C bus high and low time for all enabled I2C buses. BUG=b:163743035 TEST=Measured the I2C bus frequency as 384 KHz, high time as 924 ns and low time as 1680 ns. Change-Id: I60a5f6814fb9818c724f6b6fe465ea49d0de0f97 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/variants/waddledee/overridetree.cb 1 file changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/45083/1 diff --git a/src/mainboard/google/dedede/variants/waddledee/overridetree.cb b/src/mainboard/google/dedede/variants/waddledee/overridetree.cb index a538ecc..a525a0f 100644 --- a/src/mainboard/google/dedede/variants/waddledee/overridetree.cb +++ b/src/mainboard/google/dedede/variants/waddledee/overridetree.cb @@ -21,18 +21,36 @@ }, .i2c[0] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, .i2c[1] = { .speed = I2C_SPEED_FAST, }, .i2c[2] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, .i2c[3] = { .speed = I2C_SPEED_FAST, }, .i2c[4] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, }" -- To view, visit https://review.coreboot.org/c/coreboot/+/45083 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60a5f6814fb9818c724f6b6fe465ea49d0de0f97 Gerrit-Change-Number: 45083 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Skip Gpio configuration from FSP
by Srinidhi N Kaushik (Code Review) 08 Sep '20

08 Sep '20

Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44913 ) Change subject: soc/intel/tigerlake: Skip Gpio configuration from FSP ...................................................................... soc/intel/tigerlake: Skip Gpio configuration from FSP FSP v3333 or later, provides a new UPD to Skip configuring Gpio settings from FSP. Coreboot should provide all the required Gpio configuration for the platform when this UPD is set. BUG=b:166790597, 146390704 BRANCH=none TEST=build and boot volteer proto2 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: If32f35a188d510db8e4d8973cae78297d49a9240 --- M src/soc/intel/tigerlake/romstage/fsp_params.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/44913/1 diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 2ba276d..4b68cb6 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -87,6 +87,9 @@ dev = pcidev_path_on_root(PCH_DEVFN_ISH); m_cfg->PchIshEnable = is_dev_enabled(dev); + /* Skip GPIO configuration from FSP */ + m_cfg->GpioOverride = 0x1; + /* DP port config */ m_cfg->DdiPortAConfig = config->DdiPortAConfig; m_cfg->DdiPortBConfig = config->DdiPortBConfig; -- To view, visit https://review.coreboot.org/c/coreboot/+/44913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If32f35a188d510db8e4d8973cae78297d49a9240 Gerrit-Change-Number: 44913 Gerrit-PatchSet: 1 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/elkhartlake: Update PMC related registers value
by Lean Sheng Tan (Code Review) 08 Sep '20

08 Sep '20

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45075 ) Change subject: soc/intel/elkhartlake: Update PMC related registers value ...................................................................... soc/intel/elkhartlake: Update PMC related registers value Update ABase, PMC GPIO value sets and PMC register base address. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan(a)intel.com> Change-Id: Iba43b791cab0665ddebfbed68b7e2d15406ad206 --- M src/soc/intel/elkhartlake/bootblock/pch.c M src/soc/intel/elkhartlake/include/soc/pmc.h 2 files changed, 17 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/45075/1 diff --git a/src/soc/intel/elkhartlake/bootblock/pch.c b/src/soc/intel/elkhartlake/bootblock/pch.c index 3988cab..9224c48 100644 --- a/src/soc/intel/elkhartlake/bootblock/pch.c +++ b/src/soc/intel/elkhartlake/bootblock/pch.c @@ -21,7 +21,7 @@ #include <soc/pcr_ids.h> #include <soc/pm.h> -#define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0xA00 +#define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x0C00 #define PCR_PSFX_TO_SHDW_BAR0 0 #define PCR_PSFX_TO_SHDW_BAR1 0x4 diff --git a/src/soc/intel/elkhartlake/include/soc/pmc.h b/src/soc/intel/elkhartlake/include/soc/pmc.h index 59bee8f..9e6d22f 100644 --- a/src/soc/intel/elkhartlake/include/soc/pmc.h +++ b/src/soc/intel/elkhartlake/include/soc/pmc.h @@ -5,7 +5,7 @@ /* PCI Configuration Space (D31:F2): PMC */ #define PWRMBASE 0x10 -#define ABASE 0x20 +#define ABASE 0x40 /* Memory mapped IO registers in PMC */ #define GEN_PMCON_A 0x1020 @@ -102,17 +102,21 @@ #define GPE0_DWX_MASK 0xf #define GPE0_DW_SHIFT(x) (4*(x)) -#define PMC_GPP_G 0x0 -#define PMC_GPP_B 0x1 -#define PMC_GPP_A 0x2 -#define PMC_GPP_R 0x3 -#define PMC_GPP_S 0x4 -#define PMC_GPD 0x5 -#define PMC_GPP_H 0x6 -#define PMC_GPP_D 0x7 -#define PMC_GPP_F 0x8 -#define PMC_GPP_C 0xA -#define PMC_GPP_E 0xB +#define PMC_GPP_B 0x0 +#define PMC_GPP_T 0x1 +#define PMC_GPP_D 0x2 +#define PMC_GPP_A 0x3 +#define PMC_GPP_R 0x4 +#define PMC_GPP_V 0x5 +#define PMC_GPD 0x6 +#define PMC_GPP_H 0x7 +#define PMC_GPP_U 0x8 +#define PMC_VGPIO 0x9 +#define PMC_GPP_F 0xA +#define PMC_GPP_C 0xB +#define PMC_GPP_E 0xC +#define PMC_GPP_G 0xD +#define PMC_GPP_S 0xE #define GBLRST_CAUSE0 0x1924 #define GBLRST_CAUSE0_THERMTRIP (1 << 5) -- To view, visit https://review.coreboot.org/c/coreboot/+/45075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba43b791cab0665ddebfbed68b7e2d15406ad206 Gerrit-Change-Number: 45075 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/elkhartlake: Add CPU, SA, PCH & IGD DIDs Table
by Lean Sheng Tan (Code Review) 08 Sep '20

08 Sep '20

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45074 ) Change subject: soc/intel/elkhartlake: Add CPU, SA, PCH & IGD DIDs Table ...................................................................... soc/intel/elkhartlake: Add CPU, SA, PCH & IGD DIDs Table 1. Add CPU, SA, PCH & IGD DIDs table into report_platform.c 2. Add additional EHL SA DID in pci_ids.h Signed-off-by: Tan, Lean Sheng <lean.sheng.tan(a)intel.com> Change-Id: I5c98089873b17f82560eba13c7de3353b6d3e249 --- M src/include/device/pci_ids.h M src/soc/intel/elkhartlake/bootblock/report_platform.c 2 files changed, 51 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/45074/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 5aaf7b3..9ef6f0a 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3725,6 +3725,7 @@ #define PCI_DEVICE_ID_INTEL_EHL_ID_10 0x452C #define PCI_DEVICE_ID_INTEL_EHL_ID_11 0x452E #define PCI_DEVICE_ID_INTEL_EHL_ID_12 0x4518 +#define PCI_DEVICE_ID_INTEL_EHL_ID_13 0x451A #define PCI_DEVICE_ID_INTEL_JSL_ID_1 0x4e22 #define PCI_DEVICE_ID_INTEL_JSL_ID_2 0x4e26 #define PCI_DEVICE_ID_INTEL_JSL_ID_3 0x4e12 diff --git a/src/soc/intel/elkhartlake/bootblock/report_platform.c b/src/soc/intel/elkhartlake/bootblock/report_platform.c index 82b2ba1..b1b7fe8 100644 --- a/src/soc/intel/elkhartlake/bootblock/report_platform.c +++ b/src/soc/intel/elkhartlake/bootblock/report_platform.c @@ -14,9 +14,56 @@ #include <soc/pci_devs.h> #include <string.h> -/* - * TODO: Add EHL specific CPU/SA/PCH/IGD IDs here - */ +static struct { + uint32_t cpuid; + const char *name; +} cpu_table[] = { + { CPUID_ELKHARTLAKE_A0, "Elkhartlake A0" }, + { CPUID_ELKHARTLAKE_B0, "Elkhartlake B0" }, +}; + +static struct { + u16 mchid; + const char *name; +} mch_table[] = { + { PCI_DEVICE_ID_INTEL_EHL_ID_1, "Elkhartlake SKU-0" }, + { PCI_DEVICE_ID_INTEL_EHL_ID_2, "Elkhartlake SKU-1" }, + { PCI_DEVICE_ID_INTEL_EHL_ID_3, "Elkhartlake SKU-2" }, + { PCI_DEVICE_ID_INTEL_EHL_ID_4, "Elkhartlake SKU-3" }, + { PCI_DEVICE_ID_INTEL_EHL_ID_5, "Elkhartlake SKU-4" }, + { PCI_DEVICE_ID_INTEL_EHL_ID_6, "Elkhartlake SKU-5" }, + { PCI_DEVICE_ID_INTEL_EHL_ID_7, "Elkhartlake SKU-6" }, + { PCI_DEVICE_ID_INTEL_EHL_ID_8, "Elkhartlake SKU-7" }, + { PCI_DEVICE_ID_INTEL_EHL_ID_9, "Elkhartlake SKU-8" }, + { PCI_DEVICE_ID_INTEL_EHL_ID_10, "Elkhartlake SKU-9" }, + { PCI_DEVICE_ID_INTEL_EHL_ID_11, "Elkhartlake SKU-10" }, + { PCI_DEVICE_ID_INTEL_JSL_EHL, "Elkhartlake SKU-11" }, + { PCI_DEVICE_ID_INTEL_EHL_ID_12, "Elkhartlake SKU-12" }, + { PCI_DEVICE_ID_INTEL_EHL_ID_13, "Elkhartlake SKU-13" }, +}; + +static struct { + u16 espiid; + const char *name; +} pch_table[] = { + { PCI_DEVICE_ID_INTEL_MCC_ESPI_0, "Elkhartlake-0" }, + { PCI_DEVICE_ID_INTEL_MCC_ESPI_1, "Elkhartlake-1" }, + { PCI_DEVICE_ID_INTEL_MCC_BASE_ESPI, "Elkhartlake Base" }, + { PCI_DEVICE_ID_INTEL_MCC_PREMIUM_ESPI, "Elkhartlake Premium" }, + { PCI_DEVICE_ID_INTEL_MCC_SUPER_ESPI, "Elkhartlake Super" }, +}; + +static struct { + u16 igdid; + const char *name; +} igd_table[] = { + { PCI_DEVICE_ID_INTEL_EHL_GT1_1, "Elkhartlake GT1-1" }, + { PCI_DEVICE_ID_INTEL_EHL_GT2_1, "Elkhartlake GT2-1" }, + { PCI_DEVICE_ID_INTEL_EHL_GT1_2, "Elkhartlake GT1-2" }, + { PCI_DEVICE_ID_INTEL_EHL_GT2_2, "Elkhartlake GT2-2" }, + { PCI_DEVICE_ID_INTEL_EHL_GT1_3, "Elkhartlake GT1-3" }, + { PCI_DEVICE_ID_INTEL_EHL_GT2_3, "Elkhartlake GT2-3" }, +}; static inline uint8_t get_dev_revision(pci_devfn_t dev) { -- To view, visit https://review.coreboot.org/c/coreboot/+/45074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c98089873b17f82560eba13c7de3353b6d3e249 Gerrit-Change-Number: 45074 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit September 2020