coreboot-gerrit September 2020

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Change in coreboot[master]: mb/google/zork: update TS power control for dirinboz
by Kevin Chiu (Code Review) 08 Sep '20

08 Sep '20

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45061 ) Change subject: mb/google/zork: update TS power control for dirinboz ...................................................................... mb/google/zork: update TS power control for dirinboz 3.6 schematic will separate TS power from eDP PP3300 to AGPIO32 for power control. BUG=b:161579679 BRANCH=master TEST=emerge-zork coreboot Change-Id: Ieef67e1d04201c5d9e1dc625c519e6d0307c55f0 Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> --- M src/mainboard/google/zork/variants/dirinboz/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/45061/1 diff --git a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb index 0e35d99..05c5110 100644 --- a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb @@ -52,7 +52,7 @@ register "desc" = ""ELAN Touchscreen"" register "probed" = "1" register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_90)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_32)" register "enable_delay_ms" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" register "reset_delay_ms" = "20" @@ -67,7 +67,7 @@ register "generic.desc" = ""G2TOUCH Touchscreen"" register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" register "generic.probed" = "1" - register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_90)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_32)" register "generic.enable_delay_ms" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" register "generic.reset_delay_ms" = "50" -- To view, visit https://review.coreboot.org/c/coreboot/+/45061 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieef67e1d04201c5d9e1dc625c519e6d0307c55f0 Gerrit-Change-Number: 45061 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/system76/lemp: Move PCIe root port config into devicetree
by Felix Singer (Code Review) 08 Sep '20

08 Sep '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45109 ) Change subject: mb/system76/lemp: Move PCIe root port config into devicetree ...................................................................... mb/system76/lemp: Move PCIe root port config into devicetree Change-Id: Idd38ab530fd8a0c16231f3499eac393c333a9a92 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/system76/lemp9/devicetree.cb 1 file changed, 22 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/45109/1 diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb index d3353b7..e648428 100644 --- a/src/mainboard/system76/lemp9/devicetree.cb +++ b/src/mainboard/system76/lemp9/devicetree.cb @@ -48,30 +48,6 @@ register "PchHdaAudioLinkSndw3" = "0" register "PchHdaAudioLinkSndw4" = "0" - # PCI Express root port #6 x1, Clock 3 (card reader) - register "PcieRpEnable[5]" = "1" - register "PcieRpLtrEnable[5]" = "1" - register "PcieClkSrcUsage[3]" = "5" - register "PcieClkSrcClkReq[3]" = "3" - - # PCI Express root port #8 x1, Clock 2 (WLAN) - register "PcieRpEnable[7]" = "1" - register "PcieRpLtrEnable[7]" = "1" - register "PcieClkSrcUsage[2]" = "7" - register "PcieClkSrcClkReq[2]" = "2" - - # PCI Express root port #9 x4, Clock 4 (SSD2) - register "PcieRpEnable[8]" = "1" - register "PcieRpLtrEnable[8]" = "1" - register "PcieClkSrcUsage[4]" = "8" - register "PcieClkSrcClkReq[4]" = "4" - - # PCI Express root port #13 x4, Clock 5 (SSD1) - register "PcieRpEnable[12]" = "1" - register "PcieRpLtrEnable[12]" = "1" - register "PcieClkSrcUsage[5]" = "12" - register "PcieClkSrcClkReq[5]" = "5" - # Misc register "AcousticNoiseMitigation" = "1" #register "dmipwroptimize" = "1" @@ -177,22 +153,42 @@ device pci 1c.3 off end # PCI Express Port 4 device pci 1c.4 off end # PCI Express Port 5 device pci 1c.5 on # PCI Express Port 6 + device pci 00.0 on end # x1 Card reader + register "PcieRpEnable[5]" = "1" + register "PcieRpLtrEnable[5]" = "1" + register "PcieClkSrcUsage[3]" = "5" + register "PcieClkSrcClkReq[3]" = "3" register "PcieRpSlotImplemented[5]" = "1" end device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 on # PCI Express Port 8 - chip drivers/intel/wifi # PCIe wifi + device pci 00.0 on end # x1 M.2/E 2230 (WLAN) + register "PcieRpEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "1" + register "PcieClkSrcUsage[2]" = "7" + register "PcieClkSrcClkReq[2]" = "2" + register "PcieRpSlotImplemented[7]" = "1" + chip drivers/intel/wifi device pci 00.0 on end end - register "PcieRpSlotImplemented[7]" = "1" end device pci 1d.0 on # PCI Express Port 9 + device pci 00.0 on end # x4 M.2/M 2280 + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieClkSrcUsage[4]" = "8" + register "PcieClkSrcClkReq[4]" = "4" register "PcieRpSlotImplemented[8]" = "1" end device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 device pci 1d.4 on # PCI Express Port 13 + device pci 00.0 on end # x4 M.2/M 2280 + register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" + register "PcieClkSrcUsage[5]" = "12" + register "PcieClkSrcClkReq[5]" = "5" register "PcieRpSlotImplemented[12]" = "1" end device pci 1d.5 off end # PCI Express Port 14 -- To view, visit https://review.coreboot.org/c/coreboot/+/45109 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd38ab530fd8a0c16231f3499eac393c333a9a92 Gerrit-Change-Number: 45109 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/system76/lemp9: enable eDP in Fsp
by Michael Niewöhner (Code Review) 08 Sep '20

08 Sep '20

Hello Felix Singer, build bot (Jenkins), Jeremy Soller, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45126 to look at the new patch set (#6). Change subject: mb/system76/lemp9: enable eDP in Fsp ...................................................................... mb/system76/lemp9: enable eDP in Fsp This sets DdiPortEdp=1 to make Fsp configure VDDEN, BKLTEN and BKLTCTL to make eDP work with libgfxinit. Change-Id: Ice5f55e07ea9e028a0b6a904511eb59830351738 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/system76/lemp9/devicetree.cb 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/45126/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/45126 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice5f55e07ea9e028a0b6a904511eb59830351738 Gerrit-Change-Number: 45126 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/system76/lemp9: gpio: convert gpio.h to a cleaner format
by Michael Niewöhner (Code Review) 08 Sep '20

08 Sep '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Patrick Georgi, Jeremy Soller, Paul Menzel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/43652 to look at the new patch set (#28). Change subject: mb/system76/lemp9: gpio: convert gpio.h to a cleaner format ...................................................................... mb/system76/lemp9: gpio: convert gpio.h to a cleaner format This converts gpio.h to a compacter, cleaner format by keeping gpios in a single line, where possible. Test: images built with TIMELESS do not differ. Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: I9054274dc4c8942935b6a4789bfc1547dd3d4017 --- M src/mainboard/system76/lemp9/gpio.h 1 file changed, 213 insertions(+), 512 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/43652/28 -- To view, visit https://review.coreboot.org/c/coreboot/+/43652 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9054274dc4c8942935b6a4789bfc1547dd3d4017 Gerrit-Change-Number: 43652 Gerrit-PatchSet: 28 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/system76/lemp9: gpio: convert the remaining raw pads to macros
by Michael Niewöhner (Code Review) 08 Sep '20

08 Sep '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Patrick Georgi, Jeremy Soller, Paul Menzel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/43648 to look at the new patch set (#28). Change subject: mb/system76/lemp9: gpio: convert the remaining raw pads to macros ...................................................................... mb/system76/lemp9: gpio: convert the remaining raw pads to macros Convert the EC and touchpad interrupt pads from raw to macros. Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: I79d2cca0f300e6daf1c1923a1882e4cc1ffc3c8b --- M src/mainboard/system76/lemp9/gpio.h 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/43648/28 -- To view, visit https://review.coreboot.org/c/coreboot/+/43648 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79d2cca0f300e6daf1c1923a1882e4cc1ffc3c8b Gerrit-Change-Number: 43648 Gerrit-PatchSet: 28 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/system76/lemp9: move HDA options into devicetree
by Michael Niewöhner (Code Review) 08 Sep '20

08 Sep '20

Hello Felix Singer, build bot (Jenkins), Jeremy Soller, Paul Menzel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45132 to look at the new patch set (#2). Change subject: mb/system76/lemp9: move HDA options into devicetree ...................................................................... mb/system76/lemp9: move HDA options into devicetree Change-Id: Id4fc12896f89739d0ee2a47a42173693921da14e Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/system76/lemp9/devicetree.cb 1 file changed, 13 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/45132/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4fc12896f89739d0ee2a47a42173693921da14e Gerrit-Change-Number: 45132 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/system76/lemp9: Add SMBIOS descriptions to root ports
by Felix Singer (Code Review) 08 Sep '20

08 Sep '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45110 ) Change subject: mb/system76/lemp9: Add SMBIOS descriptions to root ports ...................................................................... mb/system76/lemp9: Add SMBIOS descriptions to root ports Change-Id: Ie663d424edbbeeb8f5691b00f3977f7501e9ab45 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/system76/lemp9/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/45110/1 diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb index e648428..514f012 100644 --- a/src/mainboard/system76/lemp9/devicetree.cb +++ b/src/mainboard/system76/lemp9/devicetree.cb @@ -171,6 +171,7 @@ chip drivers/intel/wifi device pci 00.0 on end end + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X" end device pci 1d.0 on # PCI Express Port 9 device pci 00.0 on end # x4 M.2/M 2280 @@ -179,6 +180,7 @@ register "PcieClkSrcUsage[4]" = "8" register "PcieClkSrcClkReq[4]" = "4" register "PcieRpSlotImplemented[8]" = "1" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" end device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 @@ -190,6 +192,7 @@ register "PcieClkSrcUsage[5]" = "12" register "PcieClkSrcClkReq[5]" = "5" register "PcieRpSlotImplemented[12]" = "1" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" end device pci 1d.5 off end # PCI Express Port 14 device pci 1d.6 off end # PCI Express Port 15 -- To view, visit https://review.coreboot.org/c/coreboot/+/45110 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie663d424edbbeeb8f5691b00f3977f7501e9ab45 Gerrit-Change-Number: 45110 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib/Makefile.inc: fail build when SPD would be empty
by Paul Fagerburg (Code Review) 08 Sep '20

08 Sep '20

Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45131 ) Change subject: lib/Makefile.inc: fail build when SPD would be empty ...................................................................... Patch Set 8: > Patch Set 6: > > > Patch Set 6: > > > > > Patch Set 6: > > > > > > Does anyone know which kind of memory (slotted or memory-down) Google Sushi and Google Trondo use? > > > > Sushi was a test platform, and won't actually be built. But if you need to specify something, then memory-down. > > Right, thanks for the insight. If Sushi won't actually be built, we might as well drop it then? Treating it like a memory-down platform would require adding an invalid SPD binary to it, which wouldn't work. I'll look at what's involved besides just removing it from coreboot. -- To view, visit https://review.coreboot.org/c/coreboot/+/45131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6db1dbe5fed5f242e408bcad4f36dda1b1fa1b4 Gerrit-Change-Number: 45131 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 07 Sep 2020 22:19:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: ec/system76: Add console support
by Jeremy Soller (Code Review) 07 Sep '20

07 Sep '20

Jeremy Soller has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43718 ) Change subject: ec/system76: Add console support ...................................................................... ec/system76: Add console support This adds support for line-buffered console output to System76 EC firmware. Tested on system76/lemp9 with CONSOLE_SYSTEM76_EC enabled. Signed-off-by: Jeremy Soller <jeremy(a)system76.com> Change-Id: I861bf3e22f40dd6c3ec7ba1d73711b399358e332 --- M src/console/Kconfig M src/console/console.c A src/ec/system76/ec/Makefile.inc A src/ec/system76/ec/system76_ec.c A src/include/console/system76_ec.h 5 files changed, 102 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/43718/1 diff --git a/src/console/Kconfig b/src/console/Kconfig index 7c6e9bc..bad6c56 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -302,6 +302,13 @@ This is currently working only in ramstage due to how the spi drivers are written. +config CONSOLE_SYSTEM76_EC + bool "System76 EC console output" + default n + depends on EC_SYSTEM76_EC + help + Send coreboot debug output to a System76 embedded controller. + config CONSOLE_OVERRIDE_LOGLEVEL bool help diff --git a/src/console/console.c b/src/console/console.c index bc9d918..2f544a8 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -9,6 +9,7 @@ #include <console/usb.h> #include <console/spi.h> #include <console/flash.h> +#include <console/system76_ec.h> void console_hw_init(void) { @@ -21,6 +22,7 @@ __usbdebug_init(); __spiconsole_init(); __flashconsole_init(); + __system76_ec_init(); } void console_tx_byte(unsigned char byte) @@ -42,6 +44,7 @@ __usb_tx_byte(byte); __spiconsole_tx_byte(byte); __flashconsole_tx_byte(byte); + __system76_ec_tx_byte(byte); } void console_tx_flush(void) @@ -50,6 +53,7 @@ __ne2k_tx_flush(); __usb_tx_flush(); __flashconsole_tx_flush(); + __system76_ec_tx_flush(); } void console_write_line(uint8_t *buffer, size_t number_of_bytes) diff --git a/src/ec/system76/ec/Makefile.inc b/src/ec/system76/ec/Makefile.inc new file mode 100644 index 0000000..382daa6 --- /dev/null +++ b/src/ec/system76/ec/Makefile.inc @@ -0,0 +1,6 @@ +ifeq ($(CONFIG_EC_SYSTEM76_EC),y) + +all-y += system76_ec.c +smm-$(CONFIG_DEBUG_SMI) += system76_ec.c + +endif diff --git a/src/ec/system76/ec/system76_ec.c b/src/ec/system76/ec/system76_ec.c new file mode 100644 index 0000000..238e630 --- /dev/null +++ b/src/ec/system76/ec/system76_ec.c @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/io.h> +#include <console/system76_ec.h> +#include <timer.h> + +#define SYSTEM76_EC_BASE 0x0E00 + +static inline uint8_t system76_ec_read(uint8_t addr) +{ + return inb(SYSTEM76_EC_BASE + (uint16_t)addr); +} + +static inline void system76_ec_write(uint8_t addr, uint8_t data) +{ + outb(data, SYSTEM76_EC_BASE + (uint16_t)addr); +} + +void system76_ec_init(void) +{ + // Clear entire command region + for (int i = 0; i < 256; i++) + system76_ec_write((uint8_t)i, 0); +} + +void system76_ec_flush(void) +{ + // Send command + system76_ec_write(0, 4); + + // Wait for command completion, for up to 10 milliseconds + wait_us(10000, system76_ec_read(0) == 0); + + // Clear length + system76_ec_write(3, 0); +} + +void system76_ec_print(uint8_t byte) +{ + // Read length + uint8_t len = system76_ec_read(3); + // Write data at offset + system76_ec_write(len + 4, byte); + // Update length + system76_ec_write(3, len + 1); + + // If we hit the end of the buffer, or were given a newline, flush + if (byte == '\n' || len >= 128) + system76_ec_flush(); +} diff --git a/src/include/console/system76_ec.h b/src/include/console/system76_ec.h new file mode 100644 index 0000000..616e46f --- /dev/null +++ b/src/include/console/system76_ec.h @@ -0,0 +1,35 @@ +#ifndef CONSOLE_SYSTEM76_EC_H +#define CONSOLE_SYSTEM76_EC_H 1 + +#include <stddef.h> +#include <stdint.h> + +void system76_ec_init(void); +void system76_ec_flush(void); +void system76_ec_print(uint8_t byte); + +#define __CONSOLE_SYSTEM76_EC_ENABLE__ (CONFIG(CONSOLE_SYSTEM76_EC) && \ + (ENV_BOOTBLOCK || ENV_ROMSTAGE || ENV_RAMSTAGE \ + || ENV_SEPARATE_VERSTAGE || ENV_POSTCAR \ + || (ENV_SMM && CONFIG(DEBUG_SMI)))) + +#if __CONSOLE_SYSTEM76_EC_ENABLE__ +static inline void __system76_ec_init(void) +{ + system76_ec_init(); +} +static inline void __system76_ec_tx_flush(void) +{ + system76_ec_flush(); +} +static inline void __system76_ec_tx_byte(unsigned char byte) +{ + system76_ec_print(byte); +} +#else +static inline void __system76_ec_init(void) {} +static inline void __system76_ec_tx_flush(void) {} +static inline void __system76_ec_tx_byte(unsigned char byte) {} +#endif + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/43718 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I861bf3e22f40dd6c3ec7ba1d73711b399358e332 Gerrit-Change-Number: 43718 Gerrit-PatchSet: 1 Gerrit-Owner: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/system76/lemp9: move HDA options into devicetree
by Felix Singer (Code Review) 07 Sep '20

07 Sep '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45132 ) Change subject: mb/system76/lemp9: move HDA options into devicetree ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4fc12896f89739d0ee2a47a42173693921da14e Gerrit-Change-Number: 45132 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 07 Sep 2020 21:31:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit September 2020