coreboot-gerrit September 2020

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Change in coreboot[master]: soc/intel/apollolake: Hook up ENABLE_VMX
by Angel Pons (Code Review) 08 Sep '20

08 Sep '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45039 ) Change subject: soc/intel/apollolake: Hook up ENABLE_VMX ...................................................................... soc/intel/apollolake: Hook up ENABLE_VMX Unlike other platforms, Apollo and Gemini Lake have VmxEnable on FSP-S. Note that this will enable VMX by default on both of these platforms. Change-Id: I6a4470e0e64b10f07edfcf270bb02c7cd6a8fa1a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/apollolake/chip.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/45039/1 diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index d6e6187..22791d9 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -692,6 +692,8 @@ dev->enabled = 0; silconfig->UsbOtg = dev->enabled; + silconfig->VmxEnable = CONFIG(ENABLE_VMX); + /* Set VTD feature according to devicetree */ silconfig->VtdEnable = cfg->enable_vtd; -- To view, visit https://review.coreboot.org/c/coreboot/+/45039 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a4470e0e64b10f07edfcf270bb02c7cd6a8fa1a Gerrit-Change-Number: 45039 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/apollolake: Select CPU_INTEL_COMMON
by Angel Pons (Code Review) 08 Sep '20

08 Sep '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45038 ) Change subject: soc/intel/apollolake: Select CPU_INTEL_COMMON ...................................................................... soc/intel/apollolake: Select CPU_INTEL_COMMON This is an intermediate step to have SOC_INTEL_COMMON_BLOCK_CPU select CPU_INTEL_COMMON directly, to avoid dependency problems. Tested with BUILD_TIMELESS=1, UP Squared does not change. Gemini Lake already selects this through SOC_INTEL_COMMON_BLOCK_SGX. Change-Id: If737fa6d8700f435c8692c80244f0e71657c2236 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/apollolake/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/45038/1 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 964e7d4..96808cf 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -28,6 +28,7 @@ select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES # CPU specific options + select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select IOAPIC select PCR_COMMON_IOSF_1_0 -- To view, visit https://review.coreboot.org/c/coreboot/+/45038 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If737fa6d8700f435c8692c80244f0e71657c2236 Gerrit-Change-Number: 45038 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/haswell: Drop `gpu_panel_port_select`
by Angel Pons (Code Review) 08 Sep '20

08 Sep '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45034 ) Change subject: nb/intel/haswell: Drop `gpu_panel_port_select` ...................................................................... nb/intel/haswell: Drop `gpu_panel_port_select` The corresponding bits in PP_ON_DELAYS are reserved MBZ. Change-Id: Icd2554c928a5908dfb354b81d3e6c5b5f242f1d1 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/slippy/variants/falco/overridetree.cb M src/mainboard/google/slippy/variants/leon/overridetree.cb M src/mainboard/google/slippy/variants/peppy/overridetree.cb M src/mainboard/google/slippy/variants/wolf/overridetree.cb M src/mainboard/lenovo/t440p/devicetree.cb M src/northbridge/intel/haswell/chip.h M src/northbridge/intel/haswell/gma.c 7 files changed, 4 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/45034/1 diff --git a/src/mainboard/google/slippy/variants/falco/overridetree.cb b/src/mainboard/google/slippy/variants/falco/overridetree.cb index c163202..7df0ca1 100644 --- a/src/mainboard/google/slippy/variants/falco/overridetree.cb +++ b/src/mainboard/google/slippy/variants/falco/overridetree.cb @@ -1,7 +1,6 @@ chip northbridge/intel/haswell - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP + # Set panel power delays register "gpu_panel_power_cycle_delay" = "5" # 400ms (T4) register "gpu_panel_power_up_delay" = "600" # 60ms (T1+T2) register "gpu_panel_power_down_delay" = "600" # 60ms (T3+T7) diff --git a/src/mainboard/google/slippy/variants/leon/overridetree.cb b/src/mainboard/google/slippy/variants/leon/overridetree.cb index f3b5c4a..6dee38e 100644 --- a/src/mainboard/google/slippy/variants/leon/overridetree.cb +++ b/src/mainboard/google/slippy/variants/leon/overridetree.cb @@ -1,7 +1,6 @@ chip northbridge/intel/haswell - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP + # Set panel power delays register "gpu_panel_power_cycle_delay" = "5" # 400ms register "gpu_panel_power_up_delay" = "400" # 40ms register "gpu_panel_power_down_delay" = "150" # 15ms diff --git a/src/mainboard/google/slippy/variants/peppy/overridetree.cb b/src/mainboard/google/slippy/variants/peppy/overridetree.cb index cd6a0df..689fee4 100644 --- a/src/mainboard/google/slippy/variants/peppy/overridetree.cb +++ b/src/mainboard/google/slippy/variants/peppy/overridetree.cb @@ -1,7 +1,6 @@ chip northbridge/intel/haswell - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP + # Set panel power delays register "gpu_panel_power_cycle_delay" = "5" # 400ms register "gpu_panel_power_up_delay" = "400" # 40ms register "gpu_panel_power_down_delay" = "150" # 15ms diff --git a/src/mainboard/google/slippy/variants/wolf/overridetree.cb b/src/mainboard/google/slippy/variants/wolf/overridetree.cb index 5ccca1d..de61839 100644 --- a/src/mainboard/google/slippy/variants/wolf/overridetree.cb +++ b/src/mainboard/google/slippy/variants/wolf/overridetree.cb @@ -1,7 +1,6 @@ chip northbridge/intel/haswell - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP + # Set panel power delays register "gpu_panel_power_cycle_delay" = "6" # 500ms (T11+T12) register "gpu_panel_power_up_delay" = "2000" # 200ms (T3) register "gpu_panel_power_down_delay" = "500" # 50ms (T10) diff --git a/src/mainboard/lenovo/t440p/devicetree.cb b/src/mainboard/lenovo/t440p/devicetree.cb index 60728c4..8c35681 100644 --- a/src/mainboard/lenovo/t440p/devicetree.cb +++ b/src/mainboard/lenovo/t440p/devicetree.cb @@ -4,7 +4,6 @@ register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" - register "gpu_panel_port_select" = "0" register "gpu_panel_power_backlight_off_delay" = "1" register "gpu_panel_power_backlight_on_delay" = "1" register "gpu_panel_power_cycle_delay" = "6" diff --git a/src/northbridge/intel/haswell/chip.h b/src/northbridge/intel/haswell/chip.h index 28c0828..73375d7 100644 --- a/src/northbridge/intel/haswell/chip.h +++ b/src/northbridge/intel/haswell/chip.h @@ -17,7 +17,6 @@ u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */ u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */ - u8 gpu_panel_port_select; /* 0=LVDS 1=DP_B 2=DP_C 3=DP_D */ u8 gpu_panel_power_cycle_delay; /* T4 time sequence */ u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */ u16 gpu_panel_power_down_delay; /* T3 time sequence */ diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index c466c09..5a6bb8e 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -304,7 +304,6 @@ /* Setup Panel Power On Delays */ reg32 = gtt_read(PCH_PP_ON_DELAYS); if (!reg32) { - reg32 = (conf->gpu_panel_port_select & 0x3) << 30; reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16; reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); gtt_write(PCH_PP_ON_DELAYS, reg32); -- To view, visit https://review.coreboot.org/c/coreboot/+/45034 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd2554c928a5908dfb354b81d3e6c5b5f242f1d1 Gerrit-Change-Number: 45034 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Add SMRR Locking support
by Tim Wawrzynczak (Code Review) 08 Sep '20

08 Sep '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45013 ) Change subject: soc/intel/tigerlake: Add SMRR Locking support ...................................................................... soc/intel/tigerlake: Add SMRR Locking support The SMRR MSRs can be locked, so that a further write to them will cause a #GP. This patch adds that functionality, but since the MSR is a core-level register, it must only be done once per core; if the SoC has hyperthreading enabled, then attempting to write the SMRR Lock bit on the primary thread will cause a #GP when the secondary (sibling) thread attempts to also write to this MSR. BUG=b:164489598 TEST=Boot into OS, verify using `iotools rdmsr` that all threads have the Lock bit set. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I4ae7c7f703bdf090144637d071eb810617d9e309 --- M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/smmrelocate.c 2 files changed, 9 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/45013/1 diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 8718f97..eb0cb77 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -16,6 +16,7 @@ select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON + select CPU_INTEL_COMMON_HYPERTHREADING select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select FSP_COMPRESS_FSP_S_LZ4 select FSP_M_XIP diff --git a/src/soc/intel/tigerlake/smmrelocate.c b/src/soc/intel/tigerlake/smmrelocate.c index bbdcb68..3dada3e 100644 --- a/src/soc/intel/tigerlake/smmrelocate.c +++ b/src/soc/intel/tigerlake/smmrelocate.c @@ -9,6 +9,7 @@ #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> +#include <cpu/intel/common/common.h> #include <cpu/intel/em64t101_save_state.h> #include <cpu/intel/smm_reloc.h> #include <console/console.h> @@ -139,7 +140,13 @@ /* Write SMRR MSRs based on indicated support. */ mtrr_cap = rdmsr(MTRR_CAP_MSR); - if (mtrr_cap.lo & SMRR_SUPPORTED) + + /* Set Lock bit if supported */ + if (mtrr_cap.lo & SMRR_LOCK_SUPPORTED) + relo_params->mask.lo |= SMRR_PHYS_MASK_LOCK; + + /* Write SMRRs (if supported) on each *core* only */ + if ((mtrr_cap.lo & SMRR_SUPPORTED) && !intel_ht_sibling()) write_smrr(relo_params); } -- To view, visit https://review.coreboot.org/c/coreboot/+/45013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ae7c7f703bdf090144637d071eb810617d9e309 Gerrit-Change-Number: 45013 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: Add SMRR Lock Supported bit definition for MTRR_CAP
by Tim Wawrzynczak (Code Review) 08 Sep '20

08 Sep '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45012 ) Change subject: soc/intel/common: Add SMRR Lock Supported bit definition for MTRR_CAP ...................................................................... soc/intel/common: Add SMRR Lock Supported bit definition for MTRR_CAP The IA32_MTRR_CAP register has a bit which indicates that the SMRR MSRs can be "locked" and this patch adds the definition for that. BUG=b:164489598 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I1254fb40c790f2a83dd11c2aabcf9bdf922b9395 --- M src/soc/intel/common/block/include/intelblocks/msr.h 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/45012/1 diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index 82874f9..4aa069e 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -106,8 +106,9 @@ #define MSR_L2_QOS_MASK(reg) (0xd10 + reg) /* MTRR_CAP_MSR bits */ -#define SMRR_SUPPORTED (1<<11) -#define PRMRR_SUPPORTED (1<<12) +#define SMRR_SUPPORTED (1<<11) +#define PRMRR_SUPPORTED (1<<12) +#define SMRR_LOCK_SUPPORTED (1<<14) #define SGX_SUPPORTED (1<<2) /* Intel SDM: Table 36-6. -- To view, visit https://review.coreboot.org/c/coreboot/+/45012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1254fb40c790f2a83dd11c2aabcf9bdf922b9395 Gerrit-Change-Number: 45012 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/jasperlake_rvp: Add DTT support for jslrvp
by Sumeet R Pawnikar (Code Review) 08 Sep '20

08 Sep '20

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44942 ) Change subject: mb/intel/jasperlake_rvp: Add DTT support for jslrvp ...................................................................... mb/intel/jasperlake_rvp: Add DTT support for jslrvp Add DTT (Dynamic Tuning Technology) support for Jasper Lake based rvp board. Set power limits and CPU sensor thresholds for DTT based thermal control. BRANCH=None BUG=Noe TEST=Build and boot on jslrvp board Change-Id: I41409c70d8472c54ca452fc98d5ee9edf3ccd307 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/intel/jasperlake_rvp/Kconfig M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb 2 files changed, 30 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/44942/1 diff --git a/src/mainboard/intel/jasperlake_rvp/Kconfig b/src/mainboard/intel/jasperlake_rvp/Kconfig index d6fbe81..91ce0a8 100644 --- a/src/mainboard/intel/jasperlake_rvp/Kconfig +++ b/src/mainboard/intel/jasperlake_rvp/Kconfig @@ -3,8 +3,10 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_16384 + select DPTF_USE_EISA_HID select DRIVERS_I2C_DA7219 select DRIVERS_I2C_HID + select DRIVERS_INTEL_DPTF select DRIVERS_I2C_GENERIC select DRIVERS_I2C_MAX98373 select DRIVERS_INTEL_MIPI_CAMERA @@ -17,6 +19,7 @@ select MAINBOARD_HAS_CHROMEOS select SOC_INTEL_COMMON_BLOCK_IPU select SOC_INTEL_JASPERLAKE + select SOC_INTEL_COMMON_BLOCK_DTT select SOC_INTEL_CSE_LITE_SKU config MAINBOARD_DIR diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 268d239..c624b55 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -128,6 +128,12 @@ # Enable DPTF register "dptf_enable" = "1" + # Add PL1 and PL2 values + register "power_limits_config" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 20, + }" + # Enable S0ix register "s0ix_enable" = "1" @@ -171,7 +177,27 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 off end # SA Thermal device + device pci 04.0 on + chip drivers/intel/dptf + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 10000)" + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 119, SHUTDOWN)" + + register "controls.power_limits.pl1" = "{ + .min_power = 3000, + .max_power = 6000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 6000, + .max_power = 20000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 1000,}" + device generic 0 on end + end + end # SA Thermal device + device pci 05.0 on chip drivers/intel/mipi_camera register "acpi_uid" = "0x50000" -- To view, visit https://review.coreboot.org/c/coreboot/+/44942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41409c70d8472c54ca452fc98d5ee9edf3ccd307 Gerrit-Change-Number: 44942 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8192: Add SPI flash controller DMA read function
by CK HU (Code Review) 08 Sep '20

08 Sep '20

CK HU has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44851 ) Change subject: soc/mediatek/mt8192: Add SPI flash controller DMA read function ...................................................................... soc/mediatek/mt8192: Add SPI flash controller DMA read function To speed up SPI flash read, enable DMA read function. Signed-off-by: CK Hu <ck.hu(a)mediatek.com> Change-Id: Ic1679ef7940258350feeadac50ad8ea407fd7b90 --- M src/soc/mediatek/mt8192/flash_controller.c 1 file changed, 55 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/44851/1 diff --git a/src/soc/mediatek/mt8192/flash_controller.c b/src/soc/mediatek/mt8192/flash_controller.c index 304e4c3..0c37ae5 100644 --- a/src/soc/mediatek/mt8192/flash_controller.c +++ b/src/soc/mediatek/mt8192/flash_controller.c @@ -8,6 +8,7 @@ #include <spi-generic.h> #include <stdint.h> #include <string.h> +#include <symbols.h> #include <timer.h> #include <types.h> @@ -91,6 +92,37 @@ return 0; } +static int dma_read(u32 addr, u8 *buf, u32 len, uintptr_t dma_buf, + size_t dma_buf_len) +{ + struct stopwatch sw; + + assert(IS_ALIGNED((uintptr_t)addr, SFLASH_DMA_ALIGN) && + IS_ALIGNED(len, SFLASH_DMA_ALIGN) && + len <= dma_buf_len); + + /* do dma reset */ + write32(&mt8192_nor->fdma_ctl, SFLASH_DMA_SW_RESET); + write32(&mt8192_nor->fdma_ctl, SFLASH_DMA_WDLE_EN); + /* flash source address and dram dest address */ + write32(&mt8192_nor->fdma_fadr, addr); + write32(&mt8192_nor->fdma_dadr, dma_buf); + write32(&mt8192_nor->fdma_end_dadr, (dma_buf + len)); + /* start dma */ + write32(&mt8192_nor->fdma_ctl, SFLASH_DMA_TRIGGER | SFLASH_DMA_WDLE_EN); + + stopwatch_init_usecs_expire(&sw, SFLASH_POLLINGREG_US); + while ((read32(&mt8192_nor->fdma_ctl) & SFLASH_DMA_TRIGGER) != 0) { + if (stopwatch_expired(&sw)) { + printk(BIOS_WARNING, "dma read timeout!\n"); + return -1; + } + } + + memcpy(buf, (const void *)dma_buf, len); + return 0; +} + static int pio_read(u32 addr, u8 *buf, u32 len) { set_sfpaddr(addr); @@ -107,7 +139,29 @@ static int nor_read(const struct spi_flash *flash, u32 addr, size_t len, void *buf) { - if (pio_read(addr, buf, len)) + size_t done = 0; + uintptr_t dma_buf = (uintptr_t)_dma_coherent; + size_t dma_buf_len = REGION_SIZE(dma_coherent); + u32 next; + + if (!IS_ALIGNED((uintptr_t)addr, SFLASH_DMA_ALIGN)) { + next = MIN(ALIGN_UP((uintptr_t)addr, SFLASH_DMA_ALIGN) - + (uintptr_t)addr, len); + if (pio_read(addr, buf, next)) + return -1; + done += next; + } + + while (len - done >= SFLASH_DMA_ALIGN) { + next = MIN(dma_buf_len, ALIGN_DOWN(len - done, + SFLASH_DMA_ALIGN)); + if (dma_read(addr + done, buf + done, next, dma_buf, + dma_buf_len)) + return -1; + done += next; + } + next = len - done; + if (next > 0 && pio_read(addr + done, buf + done, next)) return -1; return 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/44851 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1679ef7940258350feeadac50ad8ea407fd7b90 Gerrit-Change-Number: 44851 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/kukui: Add LPDDR4X Samsung K4UBE3D4AA-MGCR 4GB support
by Kevin Chiu (Code Review) 08 Sep '20

08 Sep '20

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45101 ) Change subject: mb/google/kukui: Add LPDDR4X Samsung K4UBE3D4AA-MGCR 4GB support ...................................................................... mb/google/kukui: Add LPDDR4X Samsung K4UBE3D4AA-MGCR 4GB support Support 4GB Samsung K4UBE3D4AA-MGCR discrete DDR bootup. BUG=b:162379736 BRANCH=master TEST=emerge-jacuzzi coreboot Change-Id: I2f4f084ece067e9884c23004506b450a281a77a6 Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> --- M src/mainboard/google/kukui/sdram_configs.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/45101/1 diff --git a/src/mainboard/google/kukui/sdram_configs.c b/src/mainboard/google/kukui/sdram_configs.c index 1f9e6bb..5239587 100644 --- a/src/mainboard/google/kukui/sdram_configs.c +++ b/src/mainboard/google/kukui/sdram_configs.c @@ -12,6 +12,7 @@ */ static const char *const sdram_configs[] = { /* Standard table. */ + [0x00] = "sdram-lpddr4x-K4UBE3D4AA-MGCR-4GB", [0x01] = "sdram-lpddr4x-H9HCNNNCPMALHR-4GB", [0x02] = "sdram-lpddr4x-MT53E1G32D4NQ-4GB", [0x03] = "sdram-lpddr4x-KMDH6001DA-B422-4GB", -- To view, visit https://review.coreboot.org/c/coreboot/+/45101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f4f084ece067e9884c23004506b450a281a77a6 Gerrit-Change-Number: 45101 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/ocp/deltalake: Add SMBIOS OEM string for SPD register vendor ID
by Johnny Lin (Code Review) 08 Sep '20

08 Sep '20

Hello build bot (Jenkins), Patrick Rudolph, Jonathan Zhang, Jingle Hsu, Angel Pons, Morgan Jang, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/44545 to look at the new patch set (#8). Change subject: mb/ocp/deltalake: Add SMBIOS OEM string for SPD register vendor ID ...................................................................... mb/ocp/deltalake: Add SMBIOS OEM string for SPD register vendor ID Tested=On OCP Delta Lake, with FSP WW36 dmidecode -t 11 can see the SPD register vendor ID String 7: b300 0000 b300 0000 b300 0000 b300 0000 b300 0000 b300 0000 Change-Id: I15ab9b4c709eb97a03d6e08fe0bcdcb7f8607db0 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/mainboard/ocp/deltalake/ramstage.c 1 file changed, 27 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/44545/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/44545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15ab9b4c709eb97a03d6e08fe0bcdcb7f8607db0 Gerrit-Change-Number: 44545 Gerrit-PatchSet: 8 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: hatch: Create dooly variant
by Tony Huang (Code Review) 08 Sep '20

08 Sep '20

Tony Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45026 ) Change subject: hatch: Create dooly variant ...................................................................... hatch: Create dooly variant Create the dooly variant of the puff reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.1.2). BUG=155261464 BRANCH=None TEST=util/abuild/abuild -p none -t google/hatch -x -a make sure the build includes GOOGLE_DOOLY Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Change-Id: I8e714cc9bf4a49266da77db88f8c4a3ca45878d1 --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/variants/dooly/Makefile.inc A src/mainboard/google/hatch/variants/dooly/gpio.c A src/mainboard/google/hatch/variants/dooly/include/variant/acpi/dptf.asl A src/mainboard/google/hatch/variants/dooly/include/variant/ec.h A src/mainboard/google/hatch/variants/dooly/include/variant/gpio.h A src/mainboard/google/hatch/variants/dooly/overridetree.cb 8 files changed, 559 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/45026/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index ee9210d..cd7ec74 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -141,6 +141,7 @@ default "Stryke" if BOARD_GOOGLE_STRYKE default "Sushi" if BOARD_GOOGLE_SUSHI default "Wyvern" if BOARD_GOOGLE_WYVERN + default "Dooly" if BOARD_GOOGLE_DOOLY config OVERRIDE_DEVICETREE string @@ -174,6 +175,7 @@ default "stryke" if BOARD_GOOGLE_STRYKE default "sushi" if BOARD_GOOGLE_SUSHI default "wyvern" if BOARD_GOOGLE_WYVERN + default "dooly" if BOARD_GOOGLE_DOOLY config VBOOT select HAS_RECOVERY_MRC_CACHE diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index 3f803c5..f4fe50e 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -97,3 +97,7 @@ config BOARD_GOOGLE_WYVERN bool "-> Wyvern" select BOARD_GOOGLE_BASEBOARD_PUFF + +config BOARD_GOOGLE_DOOLY + bool "-> Dooly" + select BOARD_GOOGLE_BASEBOARD_PUFF diff --git a/src/mainboard/google/hatch/variants/dooly/Makefile.inc b/src/mainboard/google/hatch/variants/dooly/Makefile.inc new file mode 100644 index 0000000..3b5b7d0 --- /dev/null +++ b/src/mainboard/google/hatch/variants/dooly/Makefile.inc @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ramstage-y += gpio.c +bootblock-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/dooly/gpio.c b/src/mainboard/google/hatch/variants/dooly/gpio.c new file mode 100644 index 0000000..5a911fc --- /dev/null +++ b/src/mainboard/google/hatch/variants/dooly/gpio.c @@ -0,0 +1,115 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +static const struct pad_config gpio_table[] = { + /* A16 : SD_OC_ODL */ + PAD_CFG_GPI(GPP_A16, NONE, DEEP), + /* A18 : LAN_PE_ISOLATE_ODL */ + PAD_CFG_GPO(GPP_A18, 1, DEEP), + /* A23 : M2_WLAN_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, INVERT), + + /* B5 : LAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + + /* C0 : SMBCLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* C1 : SMBDATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + /* C6: M2_WLAN_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_C6, NONE, DEEP, EDGE_SINGLE), + /* C7 : LAN_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_C7, NONE, DEEP, EDGE_SINGLE), + /* C10 : PCH_PCON_RST_ODL */ + PAD_CFG_GPO(GPP_C10, 1, DEEP), + /* C11 : PCH_PCON_PDB_ODL */ + PAD_CFG_GPO(GPP_C11, 1, DEEP), + /* C15 : WLAN_OFF_L */ + PAD_CFG_GPO(GPP_C15, 1, DEEP), + + /* E2 : EN_PP_MST_OD */ + PAD_CFG_GPO(GPP_E2, 1, DEEP), + /* E9 : USB_A0_OC_ODL */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* E10 : USB_A1_OC_ODL */ + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + + /* F11 : EMMC_CMD */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), + /* F12 : EMMC_DATA0 */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + /* F13 : EMMC_DATA1 */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + /* F14 : EMMC_DATA2 */ + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), + /* F15 : EMMC_DATA3 */ + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + /* F16 : EMMC_DATA4 */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + /* F17 : EMMC_DATA5 */ + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + /* F18 : EMMC_DATA6 */ + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + /* F19 : EMMC_DATA7 */ + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + /* F20 : EMMC_RCLK */ + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + /* F21 : EMMC_CLK */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + /* F22 : EMMC_RST_L */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + + /* H4: PCH_I2C_PCON_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5: PCH_I2C_PCON_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H22 : PWM_PP3300_BIOZZER */ + PAD_CFG_GPO(GPP_H22, 0, DEEP), +}; + +const struct pad_config *override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* B14 : GPP_B14_STRAP */ + PAD_NC(GPP_B14, NONE), + /* B22 : GPP_B22_STRAP */ + PAD_NC(GPP_B22, NONE), + /* E19 : GPP_E19_STRAP */ + PAD_NC(GPP_E19, NONE), + /* E21 : GPP_E21_STRAP */ + PAD_NC(GPP_E21, NONE), + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C14 : BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), + /* PCH_WP_OD */ + PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C23 : WLAN_PE_RST# */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* E1 : M2_SSD_PEDET */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* E5 : SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/hatch/variants/dooly/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/dooly/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..6694063 --- /dev/null +++ b/src/mainboard/google/hatch/variants/dooly/include/variant/acpi/dptf.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <puff/acpi/dptf.asl> diff --git a/src/mainboard/google/hatch/variants/dooly/include/variant/ec.h b/src/mainboard/google/hatch/variants/dooly/include/variant/ec.h new file mode 100644 index 0000000..59fb378 --- /dev/null +++ b/src/mainboard/google/hatch/variants/dooly/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include <puff/ec.h> + +#endif diff --git a/src/mainboard/google/hatch/variants/dooly/include/variant/gpio.h b/src/mainboard/google/hatch/variants/dooly/include/variant/gpio.h new file mode 100644 index 0000000..79a1410 --- /dev/null +++ b/src/mainboard/google/hatch/variants/dooly/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/hatch/variants/dooly/overridetree.cb b/src/mainboard/google/hatch/variants/dooly/overridetree.cb new file mode 100644 index 0000000..244e678 --- /dev/null +++ b/src/mainboard/google/hatch/variants/dooly/overridetree.cb @@ -0,0 +1,415 @@ +chip soc/intel/cannonlake + # Enable heci communication + register "HeciEnabled" = "1" + + # Auto-switch between X4 NVMe and X2 NVMe. + register "TetonGlacierMode" = "1" + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoDisabled, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # USB configuration + register "usb2_ports[0]" = "{ + .enable = 1, + .ocpin = OC2, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_11P25MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 2 + register "usb2_ports[1]" = "{ + .enable = 1, + .ocpin = OC1, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 1 + register "usb2_ports[2]" = "{ + .enable = 1, + .ocpin = OC3, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 3 + register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port + register "usb2_ports[4]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 4 + register "usb2_ports[5]" = "{ + .enable = 1, + .ocpin = OC0, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A port 0 + register "usb2_ports[6]" = "USB2_PORT_EMPTY" + register "usb2_ports[7]" = "USB2_PORT_EMPTY" + register "usb2_ports[8]" = "USB2_PORT_EMPTY" + register "usb2_ports[9]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # BT + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port 2 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 3 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 1 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0 + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4 + + # Bitmap for Wake Enable on USB attach/detach + register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ + USB_PORT_WAKE_ENABLE(2) | \ + USB_PORT_WAKE_ENABLE(3) | \ + USB_PORT_WAKE_ENABLE(5) | \ + USB_PORT_WAKE_ENABLE(6)" + register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ + USB_PORT_WAKE_ENABLE(2) | \ + USB_PORT_WAKE_ENABLE(3) | \ + USB_PORT_WAKE_ENABLE(5) | \ + USB_PORT_WAKE_ENABLE(6)" + + # Enable eMMC HS400 + register "ScsEmmcHs400Enabled" = "1" + + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-14.3.7. + # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-14.3.8. + # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. + # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-14.3.9. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. + # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-14.3.10. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. + # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-14.3.12. + # [17:16] stands for Rx Clock before Output Buffer, + # 00: Rx clock after output buffer, + # 01: Rx clock before output buffer, + # 10: Automatic selection based on working mode. + # 11: Reserved + # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-14.3.11. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515" + + # Intel HDA - disable I2S Audio SSP1 and DMIC0 as puff variant does not have them. + register "PchHdaAudioLinkSsp1" = "0" + register "PchHdaAudioLinkDmic0" = "0" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | RFU | + #| I2C2 | PS175 | + #| I2C3 | MST | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 60, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 60, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 60, + }, + }" + + # PCIe port 7 for LAN + register "PcieRpEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "1" + # PCIe port 11 (x2) for NVMe hybrid storage devices + register "PcieRpEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" + # Uses CLK SRC 0 + register "PcieClkSrcUsage[0]" = "6" + register "PcieClkSrcClkReq[0]" = "0" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "vSD3_CD_B" + + # SATA port 1 Gen3 Strength + # Port1 Tx De-Emphasis = 20*log(0x20/64) = -6dB + register "sata_port[1].TxGen3DeEmphEnable" = "1" + register "sata_port[1].TxGen3DeEmph" = "0x20" + + device domain 0 on + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Front Left"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 0)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port Rear"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 3)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Front Right"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 1)" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Rear Right"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Rear Middle"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Rear Left"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 0)" + device usb 2.5 on end + end + chip drivers/usb/acpi + device usb 2.6 off end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Front Left"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 0)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Front Right"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 1)" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Rear Right"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Rear"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 3)" + device usb 3.3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Rear Left"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 0)" + device usb 3.4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Rear Middle"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.5 on end + end + end + end + end # USB xHCI + device pci 15.0 off + # RFU - Reserved for Future Use. + end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 on + chip drivers/i2c/generic + register "hid" = ""1AF80175"" + register "name" = ""PS17"" + register "desc" = ""Parade PS175"" + device i2c 4a on end + end + end # I2C #2, PCON PS175. + device pci 15.3 on + chip drivers/i2c/generic + register "hid" = ""10EC2142"" + register "name" = ""RTD2"" + register "desc" = ""Realtek RTD2142"" + device i2c 4a on end + end + end # I2C #3, Realtek RTD2142. + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C #4 + device pci 1a.0 on end # eMMC + device pci 1c.6 on + chip drivers/net + register "customized_leds" = "0x05af" + register "wake" = "GPE0_DW1_07" # GPP_C7 + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A18)" + register "stop_delay_ms" = "12" # NIC needs time to quiesce + register "stop_off_delay_ms" = "1" + register "has_power_resource" = "1" + register "device_index" = "0" + device pci 00.0 on end + end + end # RTL8111H Ethernet NIC + device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) + device pci 1e.3 off end # GSPI #1 + end + + # VR Settings Configuration for 4 Domains + #+----------------+-------+-------+-------+-------+ + #| Domain/Setting | SA | IA | GTUS | GTS | + #+----------------+-------+-------+-------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | + #| DcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | + #+----------------+-------+-------+-------+-------+ + #Note: IccMax settings are moved to SoC code + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 1004, + .dc_loadline = 1004, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 181, + .dc_loadline = 181, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 319, + .dc_loadline = 319, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 319, + .dc_loadline = 319, + }" + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/45026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e714cc9bf4a49266da77db88f8c4a3ca45878d1 Gerrit-Change-Number: 45026 Gerrit-PatchSet: 1 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit September 2020