Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45065 )
Change subject: soc/intel/cannonlake: Add PCIe ports on PCH-H ......................................................................
soc/intel/cannonlake: Add PCIe ports on PCH-H
Change-Id: I277f592cd8d2c86a9c7ba4b34d3f703f7d593582 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/soc/intel/cannonlake/acpi/pci_irqs.asl M src/soc/intel/cannonlake/acpi/pcie.asl M src/soc/intel/cannonlake/include/soc/irq.h 3 files changed, 158 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/45065/1
diff --git a/src/soc/intel/cannonlake/acpi/pci_irqs.asl b/src/soc/intel/cannonlake/acpi/pci_irqs.asl index 7439a0e..d70f5c7 100644 --- a/src/soc/intel/cannonlake/acpi/pci_irqs.asl +++ b/src/soc/intel/cannonlake/acpi/pci_irqs.asl @@ -24,6 +24,11 @@ Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ }, Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ }, Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ }, + /* PCI Express Port 17-24 */ + Package(){0x001BFFFF, 0, 0, PCIE_17_IRQ }, + Package(){0x001BFFFF, 1, 0, PCIE_18_IRQ }, + Package(){0x001BFFFF, 2, 0, PCIE_19_IRQ }, + Package(){0x001BFFFF, 3, 0, PCIE_20_IRQ }, /* eMMC */ Package(){0x001AFFFF, 0, 0, eMMC_IRQ }, /* SerialIo */ @@ -88,6 +93,11 @@ Package () { 0x001CFFFF, 1, 0, 10 }, Package () { 0x001CFFFF, 2, 0, 11 }, Package () { 0x001CFFFF, 3, 0, 11 }, + /* D27: PCI Express Port 17-24 */ + Package () { 0x001BFFFF, 0, 0, 11 }, + Package () { 0x001BFFFF, 1, 0, 10 }, + Package () { 0x001BFFFF, 2, 0, 11 }, + Package () { 0x001BFFFF, 3, 0, 11 }, /* D25: Can't use PIC*/ /* D23 */ Package () { 0x0017FFFF, 0, 0, 11 }, diff --git a/src/soc/intel/cannonlake/acpi/pcie.asl b/src/soc/intel/cannonlake/acpi/pcie.asl index 9c0933f..0371f89 100644 --- a/src/soc/intel/cannonlake/acpi/pcie.asl +++ b/src/soc/intel/cannonlake/acpi/pcie.asl @@ -54,7 +54,7 @@
Switch (ToInteger (Arg0)) { - Case (Package () { 1, 5, 9, 13 }) { + Case (Package () { 1, 5, 9, 13, 17, 21 }) { If (PICM) { Return (IQAA) } Else { @@ -62,7 +62,7 @@ } }
- Case (Package () { 2, 6, 10, 14 }) { + Case (Package () { 2, 6, 10, 14, 18, 22 }) { If (PICM) { Return (IQBA) } Else { @@ -70,7 +70,7 @@ } }
- Case (Package () { 3, 7, 11, 15 }) { + Case (Package () { 3, 7, 11, 15, 19, 23 }) { If (PICM) { Return (IQCA) } Else { @@ -78,7 +78,7 @@ } }
- Case (Package () { 4, 8, 12, 16 }) { + Case (Package () { 4, 8, 12, 16, 20, 24 }) { If (PICM) { Return (IQDA) } Else { @@ -367,3 +367,139 @@ Return (IRQM (RPPN)) } } + +Device (RP17) +{ + Name (_ADR, 0x001B0000) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP18) +{ + Name (_ADR, 0x001B0001) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP19) +{ + Name (_ADR, 0x001B0002) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP20) +{ + Name (_ADR, 0x001B0003) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP21) +{ + Name (_ADR, 0x001B0004) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP22) +{ + Name (_ADR, 0x001B0005) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP23) +{ + Name (_ADR, 0x001B0006) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP24) +{ + Name (_ADR, 0x001B0007) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} diff --git a/src/soc/intel/cannonlake/include/soc/irq.h b/src/soc/intel/cannonlake/include/soc/irq.h index 05d4025..1aa6036 100644 --- a/src/soc/intel/cannonlake/include/soc/irq.h +++ b/src/soc/intel/cannonlake/include/soc/irq.h @@ -62,6 +62,14 @@ #define PCIE_10_IRQ 17 #define PCIE_11_IRQ 18 #define PCIE_12_IRQ 19 +#define PCIE_14_IRQ 16 +#define PCIE_15_IRQ 17 +#define PCIE_16_IRQ 18 +#define PCIE_17_IRQ 19 +#define PCIE_18_IRQ 16 +#define PCIE_19_IRQ 17 +#define PCIE_20_IRQ 18 +#define PCIE_21_IRQ 19
#define SATA_IRQ 16
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45065 )
Change subject: soc/intel/cannonlake: Add PCIe ports on PCH-H ......................................................................
Patch Set 1: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/45065/1/src/soc/intel/cannonlake/ac... File src/soc/intel/cannonlake/acpi/pci_irqs.asl:
https://review.coreboot.org/c/coreboot/+/45065/1/src/soc/intel/cannonlake/ac... PS1, Line 27: /* PCI Express Port 17-24 */ : Package(){0x001BFFFF, 0, 0, PCIE_17_IRQ }, : Package(){0x001BFFFF, 1, 0, PCIE_18_IRQ }, : Package(){0x001BFFFF, 2, 0, PCIE_19_IRQ }, : Package(){0x001BFFFF, 3, 0, PCIE_20_IRQ }, Shouldn't these be guarded, so that they aren't added for CNP-LP?
Hello build bot (Jenkins), Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45065
to look at the new patch set (#2).
Change subject: soc/intel/cannonlake: Add PCIe ports on PCH-H ......................................................................
soc/intel/cannonlake: Add PCIe ports on PCH-H
Fixes complains about missing INT configuration by the pciexp kernel modules.
Tested with Linux 5.5 on Prodrive Hermes.
Change-Id: I277f592cd8d2c86a9c7ba4b34d3f703f7d593582 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/soc/intel/cannonlake/acpi/pci_irqs.asl M src/soc/intel/cannonlake/acpi/pcie.asl M src/soc/intel/cannonlake/include/soc/irq.h 3 files changed, 180 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/45065/2
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45065 )
Change subject: soc/intel/cannonlake: Add PCIe ports on PCH-H ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45065/1/src/soc/intel/cannonlake/ac... File src/soc/intel/cannonlake/acpi/pci_irqs.asl:
https://review.coreboot.org/c/coreboot/+/45065/1/src/soc/intel/cannonlake/ac... PS1, Line 27: /* PCI Express Port 17-24 */ : Package(){0x001BFFFF, 0, 0, PCIE_17_IRQ }, : Package(){0x001BFFFF, 1, 0, PCIE_18_IRQ }, : Package(){0x001BFFFF, 2, 0, PCIE_19_IRQ }, : Package(){0x001BFFFF, 3, 0, PCIE_20_IRQ },
Shouldn't these be guarded, so that they aren't added for CNP-LP?
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45065 )
Change subject: soc/intel/cannonlake: Add PCIe ports on PCH-H ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45065 )
Change subject: soc/intel/cannonlake: Add PCIe ports on PCH-H ......................................................................
soc/intel/cannonlake: Add PCIe ports on PCH-H
Fixes complains about missing INT configuration by the pciexp kernel modules.
Tested with Linux 5.5 on Prodrive Hermes.
Change-Id: I277f592cd8d2c86a9c7ba4b34d3f703f7d593582 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/45065 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/cannonlake/acpi/pci_irqs.asl M src/soc/intel/cannonlake/acpi/pcie.asl M src/soc/intel/cannonlake/include/soc/irq.h 3 files changed, 180 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/soc/intel/cannonlake/acpi/pci_irqs.asl b/src/soc/intel/cannonlake/acpi/pci_irqs.asl index 7439a0e..d35f4d7 100644 --- a/src/soc/intel/cannonlake/acpi/pci_irqs.asl +++ b/src/soc/intel/cannonlake/acpi/pci_irqs.asl @@ -24,6 +24,13 @@ Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ }, Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ }, Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ }, +#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) + /* PCI Express Port 17-24 */ + Package(){0x001BFFFF, 0, 0, PCIE_17_IRQ }, + Package(){0x001BFFFF, 1, 0, PCIE_18_IRQ }, + Package(){0x001BFFFF, 2, 0, PCIE_19_IRQ }, + Package(){0x001BFFFF, 3, 0, PCIE_20_IRQ }, +#endif /* eMMC */ Package(){0x001AFFFF, 0, 0, eMMC_IRQ }, /* SerialIo */ @@ -88,6 +95,13 @@ Package () { 0x001CFFFF, 1, 0, 10 }, Package () { 0x001CFFFF, 2, 0, 11 }, Package () { 0x001CFFFF, 3, 0, 11 }, +#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) + /* D27: PCI Express Port 17-24 */ + Package () { 0x001BFFFF, 0, 0, 11 }, + Package () { 0x001BFFFF, 1, 0, 10 }, + Package () { 0x001BFFFF, 2, 0, 11 }, + Package () { 0x001BFFFF, 3, 0, 11 }, +#endif /* D25: Can't use PIC*/ /* D23 */ Package () { 0x0017FFFF, 0, 0, 11 }, diff --git a/src/soc/intel/cannonlake/acpi/pcie.asl b/src/soc/intel/cannonlake/acpi/pcie.asl index 9c0933f..302863b 100644 --- a/src/soc/intel/cannonlake/acpi/pcie.asl +++ b/src/soc/intel/cannonlake/acpi/pcie.asl @@ -54,7 +54,11 @@
Switch (ToInteger (Arg0)) { - Case (Package () { 1, 5, 9, 13 }) { + Case (Package () { 1, 5, 9, 13 +#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) + , 17, 21 +#endif + }) { If (PICM) { Return (IQAA) } Else { @@ -62,7 +66,11 @@ } }
- Case (Package () { 2, 6, 10, 14 }) { + Case (Package () { 2, 6, 10, 14 +#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) + , 18, 22 +#endif + }) { If (PICM) { Return (IQBA) } Else { @@ -70,7 +78,11 @@ } }
- Case (Package () { 3, 7, 11, 15 }) { + Case (Package () { 3, 7, 11, 15 +#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) + , 19, 23 +#endif + }) { If (PICM) { Return (IQCA) } Else { @@ -78,7 +90,11 @@ } }
- Case (Package () { 4, 8, 12, 16 }) { + Case (Package () { 4, 8, 12, 16 +#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) + , 20, 24 +#endif + }) { If (PICM) { Return (IQDA) } Else { @@ -367,3 +383,141 @@ Return (IRQM (RPPN)) } } + +#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) +Device (RP17) +{ + Name (_ADR, 0x001B0000) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP18) +{ + Name (_ADR, 0x001B0001) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP19) +{ + Name (_ADR, 0x001B0002) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP20) +{ + Name (_ADR, 0x001B0003) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP21) +{ + Name (_ADR, 0x001B0004) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP22) +{ + Name (_ADR, 0x001B0005) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP23) +{ + Name (_ADR, 0x001B0006) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP24) +{ + Name (_ADR, 0x001B0007) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} +#endif diff --git a/src/soc/intel/cannonlake/include/soc/irq.h b/src/soc/intel/cannonlake/include/soc/irq.h index 05d4025..1aa6036 100644 --- a/src/soc/intel/cannonlake/include/soc/irq.h +++ b/src/soc/intel/cannonlake/include/soc/irq.h @@ -62,6 +62,14 @@ #define PCIE_10_IRQ 17 #define PCIE_11_IRQ 18 #define PCIE_12_IRQ 19 +#define PCIE_14_IRQ 16 +#define PCIE_15_IRQ 17 +#define PCIE_16_IRQ 18 +#define PCIE_17_IRQ 19 +#define PCIE_18_IRQ 16 +#define PCIE_19_IRQ 17 +#define PCIE_20_IRQ 18 +#define PCIE_21_IRQ 19
#define SATA_IRQ 16
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45065 )
Change subject: soc/intel/cannonlake: Add PCIe ports on PCH-H ......................................................................
Patch Set 3:
Automatic boot test returned (PASS/FAIL/TOTAL): 7/1/8 "QEMU x86 q35/ich9" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/18401 "QEMU x86 q35/ich9" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/18400 "QEMU x86 i440fx/piix4" (x86_64) using payload SeaBIOS : FAIL : https://lava.9esec.io/r/18399 "QEMU x86 i440fx/piix4" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/18398 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/18397 "HP Z220 SFF Workstation" (x86_32) using payload LinuxBoot_BusyBox_kexec : SUCCESS : https://lava.9esec.io/r/18404 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/18403 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/18402
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Angel Pons (Code Review)
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Patrick Georgi (Code Review)
-
Patrick Rudolph (Code Review)