Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45065 )
Change subject: soc/intel/cannonlake: Add PCIe ports on PCH-H ......................................................................
Patch Set 1: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/45065/1/src/soc/intel/cannonlake/ac... File src/soc/intel/cannonlake/acpi/pci_irqs.asl:
https://review.coreboot.org/c/coreboot/+/45065/1/src/soc/intel/cannonlake/ac... PS1, Line 27: /* PCI Express Port 17-24 */ : Package(){0x001BFFFF, 0, 0, PCIE_17_IRQ }, : Package(){0x001BFFFF, 1, 0, PCIE_18_IRQ }, : Package(){0x001BFFFF, 2, 0, PCIE_19_IRQ }, : Package(){0x001BFFFF, 3, 0, PCIE_20_IRQ }, Shouldn't these be guarded, so that they aren't added for CNP-LP?