coreboot-gerrit September 2020

coreboot-gerrit@coreboot.org

1 participants
2629 discussions

Change in coreboot[master]: soc/amd/picasso: Adjust for memory Mhz fraction
by Rob Barnes (Code Review) 16 Sep '20

16 Sep '20

Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45177 ) Change subject: soc/amd/picasso: Adjust for memory Mhz fraction ...................................................................... soc/amd/picasso: Adjust for memory Mhz fraction Memory speed is given as an integer, but it some cases it has an implicit fractional speed. Specifically, speeds ending in 33 are implicitly 33.333 and speeds ending in 67 are implicitly 66.666. So when multiplying by 2 to get MT/s, the result needs to be rounded up or down by one to account for this implicit fraction. BUG=b:167155849 TEST=None Signed-off-by: Rob Barnes <robbarnes(a)google.com> Change-Id: Icc77c21932c68ee9f0ff0b8e35ae7b1a3732b322 --- M src/soc/amd/picasso/dmi.c 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/45177/1 diff --git a/src/soc/amd/picasso/dmi.c b/src/soc/amd/picasso/dmi.c index 5189cd6..33c9e22 100644 --- a/src/soc/amd/picasso/dmi.c +++ b/src/soc/amd/picasso/dmi.c @@ -30,10 +30,20 @@ /** * TYPE17_DMI_INFO holds speed in MHz. * Change to MT/s by multiplying by 2. + * Round up/down by 1 to adjust for implict clock fraction. + * e.g. 1333 Mhz == 1333.333 Mhz == 2666.666 MT/s == 26667 MT/s */ dimm->configured_speed_mts = 2 * dmi17->ConfigSpeed; + if (dimm->configured_speed_mts % 100 == 66) + dimm->configured_speed_mts += 1; + else if (dimm->configured_speed_mts % 100 == 34) + dimm->configured_speed_mts -= 1; dimm->max_speed_mts = 2 * dmi17->Speed; + if (dimm->max_speed_mts % 100 == 66) + dimm->max_speed_mts += 1; + else if (dimm->max_speed_mts % 100 == 34) + dimm->max_speed_mts -= 1; dimm->rank_per_dimm = dmi17->Attributes; -- To view, visit https://review.coreboot.org/c/coreboot/+/45177 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc77c21932c68ee9f0ff0b8e35ae7b1a3732b322 Gerrit-Change-Number: 45177 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newchange

10 33

Change in coreboot[master]: device/dram: Add method for converting MHz to MT/s
by Rob Barnes (Code Review) 16 Sep '20

16 Sep '20

Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45343 ) Change subject: device/dram: Add method for converting MHz to MT/s ...................................................................... device/dram: Add method for converting MHz to MT/s Add method for converting DDR4 speed in MHz to MT/s. Checks that MHz is within a speed grade range. BUG=b:167155849 TEST=ddr4-test unit test Change-Id: I1433f028afb794fe3e397b03f5bd0565494c8130 Signed-off-by: Rob Barnes <robbarnes(a)google.com> --- M src/device/dram/ddr4.c M src/include/device/dram/ddr4.h M tests/device/Makefile.inc A tests/device/ddr4-test.c 4 files changed, 143 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/45343/1 diff --git a/src/device/dram/ddr4.c b/src/device/dram/ddr4.c index 429a9d2..0d4c1e3 100644 --- a/src/device/dram/ddr4.c +++ b/src/device/dram/ddr4.c @@ -9,6 +9,53 @@ #include <smbios.h> #include <types.h> +/** + * DDR4 speed attributes derived from JEDEC 79-4C tables 169 & 170 + * + * min_clock_mhz = 1000/max_tCk_avg(ns) + * max_clock_mhz = 1000/min_tCk_avg(ns) + * reported_mts = Standard reported DDR4 speed in MT/s + * May be 1 less than the actual max MT/s + */ +static const ddr4_speed_attr ddr4_speeds[] = { + [DDR4_UNSPECIFIED] = {}, + [DDR4_1600] = { + .min_clock_mhz = 667, + .max_clock_mhz = 800, + .reported_mts = 1600 + }, + [DDR4_1866]{ + .min_clock_mhz = 800, + .max_clock_mhz = 934, + .reported_mts = 1866 + }, + [DDR4_2133]{ + .min_clock_mhz = 934, + .max_clock_mhz = 1067, + .reported_mts = 2133 + }, + [DDR4_2400]{ + .min_clock_mhz = 1067, + .max_clock_mhz = 1200, + .reported_mts = 2400 + }, + [DDR4_2666]{ + .min_clock_mhz = 1200, + .max_clock_mhz = 1333, + .reported_mts = 2666 + }, + [DDR4_2933]{ + .min_clock_mhz = 1333, + .max_clock_mhz = 1466, + .reported_mts = 2933 + }, + [DDR4_3200]{ + .min_clock_mhz = 1466, + .max_clock_mhz = 1600, + .reported_mts = 3200 + } +}; + typedef enum { BLOCK_0, /* Base Configuration and DRAM Parameters */ BLOCK_1, @@ -68,6 +115,33 @@ } } +/** + * Converts DDR4 clock speed in MHz to the standard reported speed in MT/s + */ +uint16_t ddr4_speed_mhz_to_reported_mts(uint16_t speed_mhz) +{ + for (enum ddr4_speed_grade speed = DDR4_MIN; speed <= DDR4_MAX; speed++) { + const ddr4_speed_attr speed_attr = ddr4_speed_attributes(speed); + if (speed_mhz > speed_attr.min_clock_mhz && + speed_mhz <= speed_attr.max_clock_mhz) { + return speed_attr.reported_mts; + } + } + printk(BIOS_ERR, "DDR4 speed of %d MHz is out of range", speed_mhz); + return 0; +} + +/** + * Gets DDR4 speed attributes for a given DDR4 speed grade + */ +const ddr4_speed_attr ddr4_speed_attributes(enum ddr4_speed_grade speed) +{ + if (speed < DDR4_MIN || speed > DDR4_MAX) { + printk(BIOS_ERR, "Invalid DDR4 speed grade"); + return ddr4_speeds[DDR4_UNSPECIFIED]; + } + return ddr4_speeds[speed]; +} /** * \brief Decode the raw SPD data diff --git a/src/include/device/dram/ddr4.h b/src/include/device/dram/ddr4.h index f258fa9..75dbaf1 100644 --- a/src/include/device/dram/ddr4.h +++ b/src/include/device/dram/ddr4.h @@ -70,4 +70,27 @@ const u16 selected_freq, const dimm_attr *info); +enum ddr4_speed_grade { + DDR4_UNSPECIFIED, + DDR4_1600, + DDR4_1866, + DDR4_2133, + DDR4_2400, + DDR4_2666, + DDR4_2933, + DDR4_3200, + DDR4_MIN = DDR4_1600, + DDR4_MAX = DDR4_3200 +}; + +typedef struct ddr4_speed_attr_st { + uint32_t min_clock_mhz; // exclusive + uint32_t max_clock_mhz; // inclusive + uint32_t reported_mts; +} ddr4_speed_attr; + +const ddr4_speed_attr ddr4_speed_attributes(enum ddr4_speed_grade speed); + +uint16_t ddr4_speed_mhz_to_reported_mts(uint16_t speed_mhz); + #endif /* DEVICE_DRAM_DDR4L_H */ diff --git a/tests/device/Makefile.inc b/tests/device/Makefile.inc index 10223c5..4626c3c 100644 --- a/tests/device/Makefile.inc +++ b/tests/device/Makefile.inc @@ -1,7 +1,12 @@ # SPDX-License-Identifier: GPL-2.0-only tests-y += i2c-test +tests-y += ddr4-test i2c-test-srcs += tests/device/i2c-test.c i2c-test-srcs += src/device/i2c.c i2c-test-mocks += platform_i2c_transfer + +ddr4-test-srcs += tests/device/ddr4-test.c +ddr4-test-srcs += tests/stubs/console.c +ddr4-test-srcs += src/device/dram/ddr4.c \ No newline at end of file diff --git a/tests/device/ddr4-test.c b/tests/device/ddr4-test.c new file mode 100644 index 0000000..0a9831d --- /dev/null +++ b/tests/device/ddr4-test.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/dram/ddr4.h> +#include <tests/test.h> + +static void ddr4_speed_mhz_to_mts_test(void **state) +{ + assert_int_equal(0, ddr4_speed_mhz_to_reported_mts(0)); + assert_int_equal(0, ddr4_speed_mhz_to_reported_mts(667)); + + assert_int_equal(1600, ddr4_speed_mhz_to_reported_mts(668)); + assert_int_equal(1600, ddr4_speed_mhz_to_reported_mts(800)); + + assert_int_equal(1866, ddr4_speed_mhz_to_reported_mts(801)); + assert_int_equal(1866, ddr4_speed_mhz_to_reported_mts(933)); + assert_int_equal(1866, ddr4_speed_mhz_to_reported_mts(934)); + + assert_int_equal(2133, ddr4_speed_mhz_to_reported_mts(1066)); + assert_int_equal(2133, ddr4_speed_mhz_to_reported_mts(1067)); + + assert_int_equal(2400, ddr4_speed_mhz_to_reported_mts(1200)); + + assert_int_equal(2666, ddr4_speed_mhz_to_reported_mts(1333)); + + assert_int_equal(2933, ddr4_speed_mhz_to_reported_mts(1466)); + + assert_int_equal(3200, ddr4_speed_mhz_to_reported_mts(1467)); + assert_int_equal(3200, ddr4_speed_mhz_to_reported_mts(1600)); + + assert_int_equal(0, ddr4_speed_mhz_to_reported_mts(1601)); + assert_int_equal(0, ddr4_speed_mhz_to_reported_mts(INT16_MAX)); +} + +int main(void) +{ + const struct CMUnitTest tests[] = { + cmocka_unit_test(ddr4_speed_mhz_to_mts_test) + }; + + return cmocka_run_group_tests(tests, NULL, NULL); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/45343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1433f028afb794fe3e397b03f5bd0565494c8130 Gerrit-Change-Number: 45343 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

7 27

Change in coreboot[master]: mb/zork/ezkinil: Fix Touchscreen doesn't work on v3.6x rework board
by Lucas Chen (Code Review) 15 Sep '20

15 Sep '20

Lucas Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45415 ) Change subject: mb/zork/ezkinil: Fix Touchscreen doesn't work on v3.6x rework board ...................................................................... mb/zork/ezkinil: Fix Touchscreen doesn't work on v3.6x rework board The gpio90 EN_PWR_TOUCHSCREEN had been set to PAD_GPO(GPIO_90, LOW), but addtional PAD_NC(GPIO_90) cause enable fail. remove it for issue fixed. BUG=b:168580357 TEST=Check Touchscreen function work Signed-off-by: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Change-Id: Id94dd63ba51759cebaf17779a5e659dbe0f1807f --- M src/mainboard/google/zork/variants/ezkinil/gpio.c 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/45415/1 diff --git a/src/mainboard/google/zork/variants/ezkinil/gpio.c b/src/mainboard/google/zork/variants/ezkinil/gpio.c index 108a134..0ec1ab23 100644 --- a/src/mainboard/google/zork/variants/ezkinil/gpio.c +++ b/src/mainboard/google/zork/variants/ezkinil/gpio.c @@ -68,8 +68,6 @@ PAD_NC(GPIO_69), /* EN_DEV_BEEP_L */ PAD_GPO(GPIO_89, HIGH), - /* TP */ - PAD_NC(GPIO_90), /* USI_RESET */ PAD_GPO(GPIO_140, HIGH), }; -- To view, visit https://review.coreboot.org/c/coreboot/+/45415 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id94dd63ba51759cebaf17779a5e659dbe0f1807f Gerrit-Change-Number: 45415 Gerrit-PatchSet: 1 Gerrit-Owner: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

6 12

Change in coreboot[master]: trogdor : invoke new watchdog function before qclib runs
by Ravi kumar (Code Review) 15 Sep '20

15 Sep '20

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45212 ) Change subject: trogdor : invoke new watchdog function before qclib runs ...................................................................... trogdor : invoke new watchdog function before qclib runs Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Change-Id: Ia76323c749a9ba71cc752a91c968aeacc11e0093 --- M src/mainboard/google/trogdor/romstage.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/45212/1 diff --git a/src/mainboard/google/trogdor/romstage.c b/src/mainboard/google/trogdor/romstage.c index 562e329..8b6f1de 100644 --- a/src/mainboard/google/trogdor/romstage.c +++ b/src/mainboard/google/trogdor/romstage.c @@ -3,6 +3,7 @@ #include <arch/stages.h> #include <soc/usb.h> #include <soc/qclib_common.h> +#include <soc/watchdog.h> static void prepare_usb(void) { @@ -17,6 +18,8 @@ { prepare_usb(); + check_wdog(); + /* QCLib: DDR init & train */ qclib_load_and_run(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/45212 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia76323c749a9ba71cc752a91c968aeacc11e0093 Gerrit-Change-Number: 45212 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: trogdor: report hardware watchdog reset after reboot
by Ravi kumar (Code Review) 15 Sep '20

15 Sep '20

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44868 ) Change subject: trogdor: report hardware watchdog reset after reboot ...................................................................... trogdor: report hardware watchdog reset after reboot Change-Id: I57ece39ff3d49f2bab259cbd92ab039a49323119 --- M src/soc/qualcomm/sc7180/soc.c 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/44868/1 diff --git a/src/soc/qualcomm/sc7180/soc.c b/src/soc/qualcomm/sc7180/soc.c index 74f0868..b529bf6 100644 --- a/src/soc/qualcomm/sc7180/soc.c +++ b/src/soc/qualcomm/sc7180/soc.c @@ -6,6 +6,11 @@ #include <soc/mmu_common.h> #include <soc/symbols.h> #include <soc/aop.h> +#include <elog.h> +#include <console/console.h> + +#define AOSS_CC_RESET_STATUS 0x0C2F0020 +#define WDOG_RESET_BIT_MASK 0x1 static void soc_read_resources(struct device *dev) { @@ -19,6 +24,14 @@ static void soc_init(struct device *dev) { + volatile unsigned int aoss = *(unsigned int *)AOSS_CC_RESET_STATUS; + + printk(BIOS_INFO, "\nSOC: AOSS_CC_RESET_STATUS : %x\n", aoss & WDOG_RESET_BIT_MASK); + printk(BIOS_INFO, "AOSS_CC_RESET_STATUS[%x]..[%x]\n", AOSS_CC_RESET_STATUS, aoss); + + if(aoss & WDOG_RESET_BIT_MASK) + elog_add_event(ELOG_TYPE_ASYNC_HW_TIMER_EXPIRED); + aop_fw_load_reset(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/44868 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I57ece39ff3d49f2bab259cbd92ab039a49323119 Gerrit-Change-Number: 44868 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-MessageType: newchange

7 30

Change in coreboot[master]: mb/intel/tglrvp/variants/tglrvp_up4 - Disable TBT_PCIe3 for TGL-Y RVP
by Jason V Le (Code Review) 15 Sep '20

15 Sep '20

Jason V Le has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45216 ) Change subject: mb/intel/tglrvp/variants/tglrvp_up4 - Disable TBT_PCIe3 for TGL-Y RVP ...................................................................... mb/intel/tglrvp/variants/tglrvp_up4 - Disable TBT_PCIe3 for TGL-Y RVP - Disable TBT_PCIe3 since it is not applicable for TGL-Y RVP Test: Boot the system and verify existing TBT ports still working Signed-off-by: Jason Le <jason.v.le(a)intel.com> Change-Id: I4ba873832931c17eed5908127dbb2e44b41f46bf --- M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/45216/1 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index c2c6902..6a0f3dd 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -160,7 +160,7 @@ device pci 07.0 on end # TBT_PCIe0 0x9A23 device pci 07.1 on end # TBT_PCIe1 0x9A25 device pci 07.2 on end # TBT_PCIe2 0x9A27 - device pci 07.3 on end # TBT_PCIe3 0x9A29 + device pci 07.3 off end # TBT_PCIe3 0x9A29 device pci 08.0 off end # GNA 0x9A11 device pci 09.0 off end # NPK 0x9A33 device pci 0a.0 off end # Crash-log SRAM 0x9A0D -- To view, visit https://review.coreboot.org/c/coreboot/+/45216 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ba873832931c17eed5908127dbb2e44b41f46bf Gerrit-Change-Number: 45216 Gerrit-PatchSet: 1 Gerrit-Owner: Jason V Le <jason.v.le(a)intel.com> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: security/tpm/tss/tcg-2.0: add const to marshalling functions
by Julius Werner (Code Review) 15 Sep '20

15 Sep '20

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45409 ) Change subject: security/tpm/tss/tcg-2.0: add const to marshalling functions ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45409 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I099bf46c928733aff2c1d1c134deec35da6309ba Gerrit-Change-Number: 45409 Gerrit-PatchSet: 3 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 16 Sep 2020 00:18:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: [RFC|NEEDTEST] soc/intel: cnl,icl,elh,jsl,tgl: enable C6DRAM
by Michael Niewöhner (Code Review) 15 Sep '20

15 Sep '20

Hello Felix Singer, build bot (Jenkins), Lijian Zhao, John Su, Anil Kumar K, David Wu, Patrick Georgi, Maulik V Vaghela, Matt DeVillier, Ravishankar Sarawadi, Alex Levin, Paul Menzel, Andrey Petrov, Kyösti Mälkki, Aaron Durbin, Patrick Rudolph, Nathaniel L Desimone, Nico Huber, Caveh Jalali, Christian Walter, Andrey Petrov, Edward O'Callaghan, Tim Chen, EricR Lai, Jonas Löffelholz, Shaunak Saha, Furquan Shaikh, Wonkyu Kim, Jeremy Soller, Thomas Heijligen, Subrata Banik, Aamir Bohra, Paul Fagerburg, Andrew McRae, Elyes HAOUAS, Tim Wawrzynczak, Nick Vaccaro, Thejaswani Putta, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45417 to look at the new patch set (#4). Change subject: [RFC|NEEDTEST] soc/intel: cnl,icl,elh,jsl,tgl: enable C6DRAM ...................................................................... [RFC|NEEDTEST] soc/intel: cnl,icl,elh,jsl,tgl: enable C6DRAM C6DRAM is not board design specific, so remove it from devicetree config. Instead, enable it on supported platforms. From Intel doc# 615211-005: The C6DRAM feature saves the processor internal state at Package C6 and deeper to DRAM instead of on-die SRAM. When the processor state has been saved to DRAM, the dedicated save/restore SRAM modules are power gated, enabling idle power savings. This power gating feature - to my knowlege - doesn't depend on board design, thus shouldn't cause any issues. Hopefully. Boards that need testing / have been tested: [] google/dedede [] google/deltaur [] google/drallion [] google/hatch [] google/sarien [] google/volteer [] intel/cannonlake_rvp [] intel/coffeelake_rvp [] intel/jasperlake_rvp [] intel/tglrvp [] prodrive/hermes [x] purism/librem_whl [x] system76/lemp9 Change-Id: I556dba59bc06c9101bdfdfd6aee00610aac516e3 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/romstage/fsp_params.c M src/soc/intel/elkhartlake/chip.h M src/soc/intel/icelake/chip.h M src/soc/intel/icelake/romstage/fsp_params.c M src/soc/intel/jasperlake/chip.h M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params.c 8 files changed, 3 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/45417/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/45417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I556dba59bc06c9101bdfdfd6aee00610aac516e3 Gerrit-Change-Number: 45417 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Andrew McRae <amcrae(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jonas Löffelholz <jonas.loeffelholz(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/cannonlake: add missing special function pads
by Michael Niewöhner (Code Review) 15 Sep '20

15 Sep '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45211 ) Change subject: soc/intel/cannonlake: add missing special function pads ...................................................................... Patch Set 11: @Subrata could you have a look at the two parent commits, too, please? -- To view, visit https://review.coreboot.org/c/coreboot/+/45211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia3bc1df1a14dbca7c7213577cb2d5b98bb0acf64 Gerrit-Change-Number: 45211 Gerrit-PatchSet: 11 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 15 Sep 2020 22:43:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: [NEEDTEST] soc/intel: cnl,icl,elh,jsl,tgl: enable C6DRAM
by Michael Niewöhner (Code Review) 15 Sep '20

15 Sep '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45417 ) Change subject: [NEEDTEST] soc/intel: cnl,icl,elh,jsl,tgl: enable C6DRAM ...................................................................... Patch Set 3: > Patch Set 2: > > So I went back and reviewed the literature, and there have been instances on several chipsets where the c6dram feature was broken in certain ucode releases. Ouch. Can you provide more info on that like uc versions? Is that "literature" public? > I think this is reason enough to leave this off by default, but leave the option open in the devicetree Then it's not good to have it in the devicetree, since the devicetree doesn't force any microcode, right? What about adding a Kconfig (default n) instead? -- To view, visit https://review.coreboot.org/c/coreboot/+/45417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I556dba59bc06c9101bdfdfd6aee00610aac516e3 Gerrit-Change-Number: 45417 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Andrew McRae <amcrae(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jonas Löffelholz <jonas.loeffelholz(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 15 Sep 2020 22:41:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit September 2020