Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45417 )
Change subject: soc/intel: cnl,icl,elh,jsl,tgl: enable C6DRAM
......................................................................
Patch Set 2:
So I went back and reviewed the literature, and there have been instances on several chipsets where the c6dram feature was broken in certain ucode releases. I think this is reason enough to leave this off by default, but leave the option open in the devicetree
--
To view, visit https://review.coreboot.org/c/coreboot/+/45417
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I556dba59bc06c9101bdfdfd6aee00610aac516e3
Gerrit-Change-Number: 45417
Gerrit-PatchSet: 2
Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de>
Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Alex Levin <levinale(a)google.com>
Gerrit-Reviewer: Andrew McRae <amcrae(a)google.com>
Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com>
Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com>
Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org>
Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com>
Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com>
Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org>
Gerrit-Reviewer: Elyes HAOUAS
Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com>
Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com>
Gerrit-Reviewer: Jonas Löffelholz <jonas.loeffelholz(a)9elements.com>
Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com>
Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com>
Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com>
Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com>
Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de>
Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Comment-Date: Tue, 15 Sep 2020 22:02:14 +0000
Gerrit-HasComments: No
Gerrit-Has-Labels: No
Gerrit-MessageType: comment
Masanori Ogino has uploaded a new patch set (#11) to the change originally created by Denis Carikli. ( https://review.coreboot.org/c/coreboot/+/13410 )
Change subject: mb/lenovo/x60: Enable TPM
......................................................................
mb/lenovo/x60: Enable TPM
Enable the onboard TPM device in the devicetree, and select Kconfig
options to add the appropriate ASL code.
This is adapted from commit 3d02b9c7.
(mainboard/lenovo/{t430s,t420s,t520,t530,x220}: Add TPM 1.2 mainboard
support)
Without this, coreboot doesn't touch the device and generates no ACPI
entry for it. Thus, in GNU/Linux, it is not detected automatically.
You can, however, force the Linux kernel to scan buses by running the
following commands:
# modprobe -r tpm_tis
# modprobe tpm_tis force=1
Running the commands above outputs some messages to dmesg, although the
actual messages vary between kernel versions. With Linux 4.9.235:
tpm_tis tpm_tis: 1.2 TPM (device-id 0x3202, rev-id 5)
tpm tpm0: Issuing TPM_STARTUP
tpm tpm0: [Hardware Error]: Adjusting reported timeouts: A 10000->10000us B 10000->10000us C 0->750000us D 0->750000us
tpm tpm0: [Hardware Error]: Adjusting reported timeouts: A 10000->10000us B 10000->10000us C 0->750000us D 0->750000us
tpm tpm0: TPM is disabled/deactivated (0x6)
Then /dev/tpm0 is created. The content of /sys/class/tpm/tpm0/caps is:
Manufacturer: 0x41544d4c
TCG version: 1.2
Firmware version: 11.5
With Linux 5.4.64:
tpm_tis tpm_tis: 1.2 TPM (device-id 0xFFFF, rev-id 255)
tpm tpm0: tpm_try_transmit: send(): error -5
tpm tpm0: A TPM error (-5) occurred attempting to determine the timeouts
tpm_tis tpm_tis: Could not get TPM timeouts and durations
In this case, tpm0 is not created.
Now, coreboot tries to initialize the device but fails to do so. From
the console log:
lpc_tpm: Read reg 0xf00 returns 0xffffffff
tis_probe: No TPM device found
TPM: Can't initialize.
While coreboot provides an ACPI entry anyway, for some reasons, Linux
still does not scan the device automatically.
See also previous discussions on LKML [1].
[1]: https://lore.kernel.org/lkml/?q=Regression+between+Linux+3.16+and+4.8%2F4.9…
Change-Id: I6e65b37507c111af1c0c56822327d5497f58f085
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org>
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Signed-off-by: Masanori Ogino <mogino(a)acm.org>
---
M src/mainboard/lenovo/x60/Kconfig
M src/mainboard/lenovo/x60/devicetree.cb
2 files changed, 5 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/13410/11
--
To view, visit https://review.coreboot.org/c/coreboot/+/13410
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I6e65b37507c111af1c0c56822327d5497f58f085
Gerrit-Change-Number: 13410
Gerrit-PatchSet: 11
Gerrit-Owner: Denis Carikli <GNUtoo(a)no-log.org>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Denis 'GNUtoo' Carikli <GNUtoo(a)cyberdimension.org>
Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Masanori Ogino <mogino(a)acm.org>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>
Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: newpatchset
Harshit Sharma has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44814 )
Change subject: Documentation: Add ASan documentation
......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44814/7/Documentation/technotes/as…
File Documentation/technotes/asan.md:
https://review.coreboot.org/c/coreboot/+/44814/7/Documentation/technotes/as…
PS7, Line 248: additional steps need to be taken to enable ASan in
: romstage on the platform
> Maybe suggest playing around with CONFIG_DCACHE_RAM_SIZE (and CONFIG_DCACHE_RAM_BASE)?
As I wrote in the very next sentence, the compile errors should be easy to resolve but it is way more work in case of a full cache. We believe a different translation function and an additional gcc patch would be required as I mentioned at line 285.
--
To view, visit https://review.coreboot.org/c/coreboot/+/44814
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I710ea495798597189941620c7e48fd5aa7476781
Gerrit-Change-Number: 44814
Gerrit-PatchSet: 7
Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Comment-Date: Tue, 15 Sep 2020 21:18:36 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-MessageType: comment
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45417 )
Change subject: soc/intel: cnl,icl,elh,jsl,tgl: enable C6DRAM
......................................................................
Patch Set 2:
> > There are 0 mainboards that use this feature right now, and you want to enable it for all of those platforms? Have you tested it on any?
>
> Heh, I did not say this shall be merged without any testing ;) I just didn't have the time earlier to add all relevant people.
The default is to review and merge patches. If you want to
avoid confusion, you can add a tag in the commit summary,
e.g. [UNTESTED] or [WIP]. Or mark them as WIP in Gerrit
(works already when pushing, e.g. `refs/for/master%wip`).
--
To view, visit https://review.coreboot.org/c/coreboot/+/45417
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I556dba59bc06c9101bdfdfd6aee00610aac516e3
Gerrit-Change-Number: 45417
Gerrit-PatchSet: 2
Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de>
Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Alex Levin <levinale(a)google.com>
Gerrit-Reviewer: Andrew McRae <amcrae(a)google.com>
Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com>
Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com>
Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org>
Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com>
Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com>
Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org>
Gerrit-Reviewer: Elyes HAOUAS
Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com>
Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com>
Gerrit-Reviewer: Jonas Löffelholz <jonas.loeffelholz(a)9elements.com>
Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com>
Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com>
Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com>
Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com>
Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de>
Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Comment-Date: Tue, 15 Sep 2020 21:03:44 +0000
Gerrit-HasComments: No
Gerrit-Has-Labels: No
Gerrit-MessageType: comment
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45409 )
Change subject: security/tpm/tss/tcg-2.0: add const to marshalling functions
......................................................................
Patch Set 3: Code-Review+2
--
To view, visit https://review.coreboot.org/c/coreboot/+/45409
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I099bf46c928733aff2c1d1c134deec35da6309ba
Gerrit-Change-Number: 45409
Gerrit-PatchSet: 3
Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Comment-Date: Tue, 15 Sep 2020 20:55:36 +0000
Gerrit-HasComments: No
Gerrit-Has-Labels: Yes
Gerrit-MessageType: comment
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45384 )
Change subject: volteer: set GSPI CS to deasserted by default
......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45384/1//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/45384/1//COMMIT_MSG@9
PS1, Line 9: This sets the state of GSPI chip select to 1 (deasserted). GSPI 0 and
> Could you mention this is set by the FSP?
Done
--
To view, visit https://review.coreboot.org/c/coreboot/+/45384
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I47aa5db429d75e66095d58a1eb77963dcfc3b9f3
Gerrit-Change-Number: 45384
Gerrit-PatchSet: 2
Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org>
Gerrit-Reviewer: Andrey Pronin <apronin(a)chromium.org>
Gerrit-Reviewer: Jes Klinke <jbk(a)chromium.org>
Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Comment-Date: Tue, 15 Sep 2020 20:50:08 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-MessageType: comment
Hello Jes Klinke, build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro, Andrey Pronin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45384
to look at the new patch set (#2).
Change subject: volteer: set GSPI CS to deasserted by default
......................................................................
volteer: set GSPI CS to deasserted by default
This sets the state of GSPI chip select to 1 (deasserted) as applied
by the FSP during the silicon init phase. GSPI 0 and 1 are set to CS
mode manual in the SerialIoGSpiCsMode section which means we need to
explicitly configure CS to deasserted in the SerialIoGSpiCsState
section. GSPI0 is the CR50 and GSPI1 is the fingerprint sensor. We
were running into problems where the normal expected CS toggle
sequence to wake up CR50 did not work because CS was already asserted
when it was expected to be deasserted, leading to TPM timeouts.
BUG=b:168090038
TEST=booted on volteer, no more "TPM flow control failure" messages;
verified fingerprint enrollment still works.
Change-Id: I47aa5db429d75e66095d58a1eb77963dcfc3b9f3
Signed-off-by: Caveh Jalali <caveh(a)chromium.org>
---
M src/mainboard/google/volteer/variants/baseboard/devicetree.cb
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/45384/2
--
To view, visit https://review.coreboot.org/c/coreboot/+/45384
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I47aa5db429d75e66095d58a1eb77963dcfc3b9f3
Gerrit-Change-Number: 45384
Gerrit-PatchSet: 2
Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org>
Gerrit-Reviewer: Andrey Pronin <apronin(a)chromium.org>
Gerrit-Reviewer: Jes Klinke <jbk(a)chromium.org>
Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: newpatchset