coreboot-gerrit September 2020

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Change in coreboot[master]: soc/intel: rename get_prmrr_size
by Michael Niewöhner (Code Review) 15 Sep '20

15 Sep '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45414 ) Change subject: soc/intel: rename get_prmrr_size ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/45414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id243be50acb741f2c3118ddde082743d08983a53 Gerrit-Change-Number: 45414 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph Gerrit-Comment-Date: Tue, 15 Sep 2020 10:24:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/lenovo/x60: Enable TPM
by Masanori Ogino (Code Review) 15 Sep '20

15 Sep '20

Masanori Ogino has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/13410 ) Change subject: mb/lenovo/x60: Enable TPM ...................................................................... Patch Set 10: (2 comments) Update the commit message to reflect the current situation. It turns out that the latest kernel in 4.9 series still does *not* detect the device automatically even with this patch, same as a recent 5.4 kernel. I could try an older kernel (earlier one in 4.4 series?) too, but, since the output of Linux 5.4 matches the Arthur's observation commented to patchset 8, it makes more sense to investigate coreboot's failure on probing IMHO. Suggestions are more than welcome. https://review.coreboot.org/c/coreboot/+/13410/9//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/13410/9//COMMIT_MSG@7 PS9, Line 7: lenovo/x60 > Ack Done https://review.coreboot.org/c/coreboot/+/13410/9//COMMIT_MSG@14 PS9, Line 14: 3d02b9c > Ack Done -- To view, visit https://review.coreboot.org/c/coreboot/+/13410 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e65b37507c111af1c0c56822327d5497f58f085 Gerrit-Change-Number: 13410 Gerrit-PatchSet: 10 Gerrit-Owner: Denis Carikli <GNUtoo(a)no-log.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Denis 'GNUtoo' Carikli <GNUtoo(a)cyberdimension.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Masanori Ogino <mogino(a)acm.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 15 Sep 2020 10:23:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Masanori Ogino <mogino(a)acm.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/sgx: drop no-ops from PRMRR Kconfig
by Michael Niewöhner (Code Review) 15 Sep '20

15 Sep '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45413 ) Change subject: soc/intel/common/block/sgx: drop no-ops from PRMRR Kconfig ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/45413 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7a19c7223a0de2e03b7df9184cddf7c9fc87a68 Gerrit-Change-Number: 45413 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph Gerrit-Comment-Date: Tue, 15 Sep 2020 10:15:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/sgx: make PRMRR size setting depend on SGX
by Michael Niewöhner (Code Review) 15 Sep '20

15 Sep '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45412 ) Change subject: soc/intel/common/block/sgx: make PRMRR size setting depend on SGX ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/45412 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I551942fd9cb8e7123d00dbd752abffe24788148c Gerrit-Change-Number: 45412 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph Gerrit-Comment-Date: Tue, 15 Sep 2020 10:15:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/lenovo/x60: Enable TPM
by Masanori Ogino (Code Review) 15 Sep '20

15 Sep '20

Masanori Ogino has uploaded a new patch set (#10) to the change originally created by Denis Carikli. ( https://review.coreboot.org/c/coreboot/+/13410 ) Change subject: mb/lenovo/x60: Enable TPM ...................................................................... mb/lenovo/x60: Enable TPM Enable the onboard TPM device in the devicetree, and select Kconfig options to add the appropriate ASL code. This is adapted from commit 3d02b9c7. (mainboard/lenovo/{t430s,t420s,t520,t530,x220}: Add TPM 1.2 mainboard support) Without this, coreboot doesn't touch the device and generates no ACPI entry for it. Thus, in GNU/Linux, it is not detected automatically. You can, however, force the Linux kernel to scan buses by running the following commands: # modprobe -r tpm_tis # modprobe tpm_tis force=1 Running the commands above outputs some messages to dmesg, although the actual messages vary between kernel versions. With Linux 4.9.235: tpm_tis tpm_tis: 1.2 TPM (device-id 0x3202, rev-id 5) tpm tpm0: Issuing TPM_STARTUP tpm tpm0: [Hardware Error]: Adjusting reported timeouts: A 10000->10000us B 10000->10000us C 0->750000us D 0->750000us tpm tpm0: [Hardware Error]: Adjusting reported timeouts: A 10000->10000us B 10000->10000us C 0->750000us D 0->750000us tpm tpm0: TPM is disabled/deactivated (0x6) After that, The /dev/tpm0 device is created. The content of /sys/class/tpm/tpm0/caps is: Manufacturer: 0x41544d4c TCG version: 1.2 Firmware version: 11.5 With Linux 5.4.64: tpm_tis tpm_tis: 1.2 TPM (device-id 0xFFFF, rev-id 255) tpm tpm0: tpm_try_transmit: send(): error -5 tpm tpm0: A TPM error (-5) occurred attempting to determine the timeouts tpm_tis tpm_tis: Could not get TPM timeouts and durations In this case, tpm0 is not created. Now, coreboot tries to initialize the device but fails. From the console log: tis_probe: No TPM device found TPM: Can't initialize. While coreboot provides an ACPI entry anyway, for some reasons, Linux still does not scan the device automatically. See also previous discussions on LKML [1]. [1]: https://lore.kernel.org/lkml/?q=Regression+between+Linux+3.16+and+4.8%2F4.9… Change-Id: I6e65b37507c111af1c0c56822327d5497f58f085 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Signed-off-by: Masanori Ogino <mogino(a)acm.org> --- M src/mainboard/lenovo/x60/Kconfig M src/mainboard/lenovo/x60/devicetree.cb 2 files changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/13410/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/13410 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e65b37507c111af1c0c56822327d5497f58f085 Gerrit-Change-Number: 13410 Gerrit-PatchSet: 10 Gerrit-Owner: Denis Carikli <GNUtoo(a)no-log.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Denis 'GNUtoo' Carikli <GNUtoo(a)cyberdimension.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Masanori Ogino <mogino(a)acm.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/cannonlake: add missing special function pads
by Subrata Banik (Code Review) 15 Sep '20

15 Sep '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45211 ) Change subject: soc/intel/cannonlake: add missing special function pads ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia3bc1df1a14dbca7c7213577cb2d5b98bb0acf64 Gerrit-Change-Number: 45211 Gerrit-PatchSet: 11 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 15 Sep 2020 10:04:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/sgx: Make PRMRR sizes always visible
by Angel Pons (Code Review) 15 Sep '20

15 Sep '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45345 ) Change subject: soc/intel/common/block/sgx: Make PRMRR sizes always visible ...................................................................... soc/intel/common/block/sgx: Make PRMRR sizes always visible Apparently, PRMRRs can be set to a non-zero size even if SGX is not to be enabled. This fixes boot failures when SGX is disabled. Change-Id: I27f1d3741e8e3755130078c79ab13ae8873354fc Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/common/block/sgx/Kconfig 1 file changed, 18 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/45345/1 diff --git a/src/soc/intel/common/block/sgx/Kconfig b/src/soc/intel/common/block/sgx/Kconfig index 771c54c..b59c8ba 100644 --- a/src/soc/intel/common/block/sgx/Kconfig +++ b/src/soc/intel/common/block/sgx/Kconfig @@ -6,24 +6,6 @@ help Intel Processor common SGX support -if SOC_INTEL_COMMON_BLOCK_SGX - -config SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY - bool - default n - help - Lock memory before SGX activation. This is only needed if MCHECK does not do it. - -config SOC_INTEL_COMMON_BLOCK_SGX_ENABLE - bool "Enable Software Guard Extensions (SGX) if available" - default n - help - Intel Software Guard Extensions (SGX) is a set of new CPU instructions that can be - used by applications to set aside private regions (so-called Secure Enclaves) of - code and data. - - SGX will only be enabled when supported by the CPU! - config SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE int default 256 if SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_MAX @@ -71,4 +53,22 @@ endchoice +if SOC_INTEL_COMMON_BLOCK_SGX + +config SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY + bool + default n + help + Lock memory before SGX activation. This is only needed if MCHECK does not do it. + +config SOC_INTEL_COMMON_BLOCK_SGX_ENABLE + bool "Enable Software Guard Extensions (SGX) if available" + default n + help + Intel Software Guard Extensions (SGX) is a set of new CPU instructions that can be + used by applications to set aside private regions (so-called Secure Enclaves) of + code and data. + + SGX will only be enabled when supported by the CPU! + endif -- To view, visit https://review.coreboot.org/c/coreboot/+/45345 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27f1d3741e8e3755130078c79ab13ae8873354fc Gerrit-Change-Number: 45345 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Revert "soc/intel/common/block/*/Kconfig: Guard options with if-blocks"
by Angel Pons (Code Review) 15 Sep '20

15 Sep '20

Hello build bot (Jenkins), Subrata Banik, Patrick Rudolph, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44996 to review the following change. Change subject: Revert "soc/intel/common/block/*/Kconfig: Guard options with if-blocks" ...................................................................... Revert "soc/intel/common/block/*/Kconfig: Guard options with if-blocks" This reverts commit 1b89f5eeab3f28c6d4d096203c9bd0deaf21f19e. Reason for revert: Breaks CFL. No agreement was reached on how to fix. Change-Id: Ic39963d0f091a3c795b029b15dcd3d30bdd5cb8f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/common/block/gpio/Kconfig M src/soc/intel/common/block/sgx/Kconfig M src/soc/intel/common/block/uart/Kconfig 3 files changed, 9 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/44996/1 diff --git a/src/soc/intel/common/block/gpio/Kconfig b/src/soc/intel/common/block/gpio/Kconfig index 753d8e0..bdbc323 100644 --- a/src/soc/intel/common/block/gpio/Kconfig +++ b/src/soc/intel/common/block/gpio/Kconfig @@ -4,40 +4,42 @@ help Intel Processor common GPIO support -if SOC_INTEL_COMMON_BLOCK_GPIO - # Use to program Interrupt Polarity Control (IPCx) register # Each bit represents IRQx Active High Polarity Disable configuration: # when set to 1, the interrupt polarity associated with IRQx is inverted # to appear as Active Low to IOAPIC and vice versa config SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG + depends on SOC_INTEL_COMMON_BLOCK_GPIO bool default n # Used to configure Pad Tolerance as 1.8V or 3.3V config SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL + depends on SOC_INTEL_COMMON_BLOCK_GPIO bool default n # Used to configure IOSSTATE and IOSTERM config SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY + depends on SOC_INTEL_COMMON_BLOCK_GPIO bool default n # Used to provide support for legacy macros config SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS + depends on SOC_INTEL_COMMON_BLOCK_GPIO bool default n # Indicate if multiple ACPI devices are used for each gpio community. config SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES + depends on SOC_INTEL_COMMON_BLOCK_GPIO bool default n # Indicate if SoC supports dual-routing of GPIOs (to different paths like SCI, # NMI, SMI, IOAPIC). This is required to support IRQ and wake on the same pad. config SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT + depends on SOC_INTEL_COMMON_BLOCK_GPIO bool default n - -endif diff --git a/src/soc/intel/common/block/sgx/Kconfig b/src/soc/intel/common/block/sgx/Kconfig index 771c54c..6e8323f 100644 --- a/src/soc/intel/common/block/sgx/Kconfig +++ b/src/soc/intel/common/block/sgx/Kconfig @@ -6,16 +6,16 @@ help Intel Processor common SGX support -if SOC_INTEL_COMMON_BLOCK_SGX - config SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY bool + depends on SOC_INTEL_COMMON_BLOCK_SGX default n help Lock memory before SGX activation. This is only needed if MCHECK does not do it. config SOC_INTEL_COMMON_BLOCK_SGX_ENABLE bool "Enable Software Guard Extensions (SGX) if available" + depends on SOC_INTEL_COMMON_BLOCK_SGX default n help Intel Software Guard Extensions (SGX) is a set of new CPU instructions that can be @@ -70,5 +70,3 @@ bool "Disabled" endchoice - -endif diff --git a/src/soc/intel/common/block/uart/Kconfig b/src/soc/intel/common/block/uart/Kconfig index 3437ec7..7d30c41 100644 --- a/src/soc/intel/common/block/uart/Kconfig +++ b/src/soc/intel/common/block/uart/Kconfig @@ -4,10 +4,9 @@ help Intel Processor common UART support -if SOC_INTEL_COMMON_BLOCK_UART - config INTEL_LPSS_UART_FOR_CONSOLE bool + depends on SOC_INTEL_COMMON_BLOCK_UART select DRIVERS_UART_8250MEM_32 select FIXED_UART_FOR_CONSOLE help @@ -15,5 +14,3 @@ for the coreboot console. WARNING: UART_FOR_CONSOLE has to be set to a correct value, otherwise wrong pad configurations might be selected. - -endif -- To view, visit https://review.coreboot.org/c/coreboot/+/44996 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic39963d0f091a3c795b029b15dcd3d30bdd5cb8f Gerrit-Change-Number: 44996 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/*/Kconfig: Guard options with if-blocks
by Angel Pons (Code Review) 15 Sep '20

15 Sep '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45043 ) Change subject: soc/intel/common/block/*/Kconfig: Guard options with if-blocks ...................................................................... soc/intel/common/block/*/Kconfig: Guard options with if-blocks The usual structure of these files is a global enable symbol, usually followed by an if-block which contains all other dependent symbols. Use this instead of having a `depends on` line to each symbol. Guard all symbols, even if they originally were not guarded, since they don't do anything useful unless the global enable option is selected. Change-Id: If5347187b07a46192f0063011ab197b5047f555f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/common/block/gpio/Kconfig M src/soc/intel/common/block/sgx/Kconfig M src/soc/intel/common/block/uart/Kconfig 3 files changed, 12 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/45043/1 diff --git a/src/soc/intel/common/block/gpio/Kconfig b/src/soc/intel/common/block/gpio/Kconfig index bdbc323..753d8e0 100644 --- a/src/soc/intel/common/block/gpio/Kconfig +++ b/src/soc/intel/common/block/gpio/Kconfig @@ -4,42 +4,40 @@ help Intel Processor common GPIO support +if SOC_INTEL_COMMON_BLOCK_GPIO + # Use to program Interrupt Polarity Control (IPCx) register # Each bit represents IRQx Active High Polarity Disable configuration: # when set to 1, the interrupt polarity associated with IRQx is inverted # to appear as Active Low to IOAPIC and vice versa config SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG - depends on SOC_INTEL_COMMON_BLOCK_GPIO bool default n # Used to configure Pad Tolerance as 1.8V or 3.3V config SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL - depends on SOC_INTEL_COMMON_BLOCK_GPIO bool default n # Used to configure IOSSTATE and IOSTERM config SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY - depends on SOC_INTEL_COMMON_BLOCK_GPIO bool default n # Used to provide support for legacy macros config SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS - depends on SOC_INTEL_COMMON_BLOCK_GPIO bool default n # Indicate if multiple ACPI devices are used for each gpio community. config SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES - depends on SOC_INTEL_COMMON_BLOCK_GPIO bool default n # Indicate if SoC supports dual-routing of GPIOs (to different paths like SCI, # NMI, SMI, IOAPIC). This is required to support IRQ and wake on the same pad. config SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT - depends on SOC_INTEL_COMMON_BLOCK_GPIO bool default n + +endif diff --git a/src/soc/intel/common/block/sgx/Kconfig b/src/soc/intel/common/block/sgx/Kconfig index 6e8323f..771c54c 100644 --- a/src/soc/intel/common/block/sgx/Kconfig +++ b/src/soc/intel/common/block/sgx/Kconfig @@ -6,16 +6,16 @@ help Intel Processor common SGX support +if SOC_INTEL_COMMON_BLOCK_SGX + config SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY bool - depends on SOC_INTEL_COMMON_BLOCK_SGX default n help Lock memory before SGX activation. This is only needed if MCHECK does not do it. config SOC_INTEL_COMMON_BLOCK_SGX_ENABLE bool "Enable Software Guard Extensions (SGX) if available" - depends on SOC_INTEL_COMMON_BLOCK_SGX default n help Intel Software Guard Extensions (SGX) is a set of new CPU instructions that can be @@ -70,3 +70,5 @@ bool "Disabled" endchoice + +endif diff --git a/src/soc/intel/common/block/uart/Kconfig b/src/soc/intel/common/block/uart/Kconfig index e731465..2de2a3a 100644 --- a/src/soc/intel/common/block/uart/Kconfig +++ b/src/soc/intel/common/block/uart/Kconfig @@ -4,21 +4,20 @@ help Intel Processor common UART support +if SOC_INTEL_COMMON_BLOCK_UART + config SOC_INTEL_COMMON_BLOCK_UART_LPSS_CLK_M_VAL - depends on SOC_INTEL_COMMON_BLOCK_UART hex help Clock m-divisor value for m/n divider config SOC_INTEL_COMMON_BLOCK_UART_LPSS_CLK_N_VAL - depends on SOC_INTEL_COMMON_BLOCK_UART hex help Clock m-divisor value for m/n divider config INTEL_LPSS_UART_FOR_CONSOLE bool - depends on SOC_INTEL_COMMON_BLOCK_UART select DRIVERS_UART_8250MEM_32 select FIXED_UART_FOR_CONSOLE help @@ -26,3 +25,5 @@ for the coreboot console. WARNING: UART_FOR_CONSOLE has to be set to a correct value, otherwise wrong pad configurations might be selected. + +endif -- To view, visit https://review.coreboot.org/c/coreboot/+/45043 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5347187b07a46192f0063011ab197b5047f555f Gerrit-Change-Number: 45043 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: common/block/pmc: Add a check to program the PchPmPwrCycDur
by V Sowmya (Code Review) 15 Sep '20

15 Sep '20

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45028 ) Change subject: common/block/pmc: Add a check to program the PchPmPwrCycDur ...................................................................... common/block/pmc: Add a check to program the PchPmPwrCycDur This patch adds a check to avoid violating the PCH EDS recommendation that the PchPmPwrCycDur will never be smaller than the the SLP_Sx assertion widths. Change-Id: Ie7d5f54939c5eb1f885d303f75a04958b9d77f4d Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/pmc/pmclib.c 2 files changed, 133 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/45028/1 diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h index 2b06a50..bd668c2 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmclib.h +++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h @@ -220,4 +220,12 @@ */ void pmc_set_power_failure_state(bool target_on); +/* This function ensures that the duration programmed in the PchPmPwrCycDur will never be + * smaller than the SLP_Sx assertion widths. + * If the pm_pwr_cyc_dur is less than any of the SLP_Sx assertion widths then it returns the + * default value PCH_PM_PWR_CYC_DUR. + */ +uint8_t get_pm_pwr_cyc_dur(uint8_t slp_s4_min_assert, uint8_t slp_s3_min_assert, + uint8_t slp_a_min_assert, uint8_t pm_pwr_cyc_dur); + #endif /* SOC_INTEL_COMMON_BLOCK_PMCLIB_H */ diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index 40d407b..56ce3d6 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -18,6 +18,38 @@ static struct chipset_power_state power_state; +/* List of Minimum Assertion durations in microseconds */ +enum min_assert_dur { + MinAssertDur0s = 0, + MinAssertDur60us = 60, + MinAssertDur1ms = 1000, + MinAssertDur50ms = 50000, + MinAssertDur98ms = 98000, + MinAssertDur500ms = 500000, + MinAssertDur1s = 1000000, + MinAssertDur2s = 2000000, + MinAssertDur3s = 3000000, + MinAssertDur4s = 4000000, +}; + +/* Signal Assertion duration values */ +struct cfg_assert_dur { + /* Minimum assertion duration of SLP_A signal */ + enum min_assert_dur slp_a; + + /* Minimum assertion duration of SLP_4 signal */ + enum min_assert_dur slp_s4; + + /* Minimum assertion duration of SLP_3 signal */ + enum min_assert_dur slp_s3; + + /* PCH PM Power Cycle duration */ + enum min_assert_dur pm_pwr_cyc_dur; +}; + +/* Default value of PchPmPwrCycDur */ +#define PCH_PM_PWR_CYC_DUR 0 + struct chipset_power_state *pmc_get_power_state(void) { struct chipset_power_state *ptr = NULL; @@ -573,3 +605,96 @@ pmc_soc_set_afterg3_en(on); } + +/* This function returns the highest assertion duration of the SLP_Sx assertion widths */ +static enum min_assert_dur get_high_assert_width(const struct cfg_assert_dur *cfg_assert_dur) +{ + enum min_assert_dur max_assert_dur = cfg_assert_dur->slp_s4; + + if (max_assert_dur < cfg_assert_dur->slp_s3) + max_assert_dur = cfg_assert_dur->slp_s3; + + if (max_assert_dur < cfg_assert_dur->slp_a) + max_assert_dur = cfg_assert_dur->slp_a; + + return max_assert_dur; +} + +/* This function converts assertion durations from register-encoded to microseconds */ +static void get_min_assert_dur(uint8_t slp_s4_min_assert, uint8_t slp_s3_min_assert, + uint8_t slp_a_min_assert, uint8_t pm_pwr_cyc_dur, + struct cfg_assert_dur *cfg_assert_dur) +{ + /* + * Ensure slp_x_dur_list[] elements in the devicetree config are in sync with + * FSP encoded values. + */ + + /* slp_s4_assert_dur_list : 1s, 1s(default), 2s, 3s, 4s */ + const enum min_assert_dur slp_s4_assert_dur_list[] = { + MinAssertDur1s, MinAssertDur1s, MinAssertDur2s, MinAssertDur3s, MinAssertDur4s + }; + + /* slp_s3_assert_dur_list: 50ms, 60us, 1ms, 50ms (Default), 2s */ + const enum min_assert_dur slp_s3_assert_dur_list[] = { + MinAssertDur50ms, MinAssertDur60us, MinAssertDur1ms, MinAssertDur50ms, MinAssertDur2s + }; + + /* slp_a_assert_dur_list: 2s, 0s, 4s, 98ms, 2s(Default) */ + const enum min_assert_dur slp_a_assert_dur_list[] = { + MinAssertDur2s, MinAssertDur0s, MinAssertDur4s, MinAssertDur98ms, MinAssertDur2s + }; + + /* pm_pwr_cyc_dur_list: 4s(Default), 1s, 2s, 3s, 4s */ + const enum min_assert_dur pm_pwr_cyc_dur_list[] = { + MinAssertDur4s, MinAssertDur1s, MinAssertDur2s, MinAssertDur3s, MinAssertDur4s + }; + + /* Get signal assertion width */ + if (slp_s4_min_assert < ARRAY_SIZE(slp_s4_assert_dur_list)) + cfg_assert_dur->slp_s4 = slp_s4_assert_dur_list[slp_s4_min_assert]; + + if (slp_s3_min_assert < ARRAY_SIZE(slp_s3_assert_dur_list)) + cfg_assert_dur->slp_s3 = slp_s3_assert_dur_list[slp_s3_min_assert]; + + if (slp_a_min_assert < ARRAY_SIZE(slp_a_assert_dur_list)) + cfg_assert_dur->slp_a = slp_a_assert_dur_list[slp_a_min_assert]; + + if (pm_pwr_cyc_dur < ARRAY_SIZE(pm_pwr_cyc_dur_list)) + cfg_assert_dur->pm_pwr_cyc_dur = pm_pwr_cyc_dur_list[pm_pwr_cyc_dur]; +} + +/* This function ensures that the duration programmed in the PchPmPwrCycDur will never be + * smaller than the SLP_Sx assertion widths. + * If the pm_pwr_cyc_dur is less than any of the SLP_Sx assertion widths then it returns the + * default value PCH_PM_PWR_CYC_DUR. + */ +uint8_t get_pm_pwr_cyc_dur(uint8_t slp_s4_min_assert, uint8_t slp_s3_min_assert, + uint8_t slp_a_min_assert, uint8_t pm_pwr_cyc_dur) +{ + /* Set default values for the minimum assertion duration */ + struct cfg_assert_dur cfg_assert_dur = { + .slp_a = MinAssertDur2s, + .slp_s4 = MinAssertDur1s, + .slp_s3 = MinAssertDur50ms, + .pm_pwr_cyc_dur = MinAssertDur4s + }; + + enum min_assert_dur high_assert_width; + + /* Convert assertion durations from register-encoded to microseconds */ + get_min_assert_dur(slp_s4_min_assert, slp_s3_min_assert, slp_a_min_assert, pm_pwr_cyc_dur, + &cfg_assert_dur); + + /* Get the highest assertion duration among PCH EDS specified signals for pwr_cyc_dur */ + high_assert_width = get_high_assert_width(&cfg_assert_dur); + + if (cfg_assert_dur.pm_pwr_cyc_dur >= high_assert_width) + return pm_pwr_cyc_dur; + + printk(BIOS_DEBUG, + "Set PmPwrCycDur to 4s as configured PmPwrCycDur (%d) violates PCH EDS " + "spec\n", pm_pwr_cyc_dur); + + return PCH_PM_PWR_CYC_DUR; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/45028 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7d5f54939c5eb1f885d303f75a04958b9d77f4d Gerrit-Change-Number: 45028 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit September 2020