Change in coreboot[master]: soc/intel/common/block/*/Kconfig: Guard options with if-blocks
Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45043 )
Change subject: soc/intel/common/block/*/Kconfig: Guard options with if-blocks ......................................................................
soc/intel/common/block/*/Kconfig: Guard options with if-blocks
The usual structure of these files is a global enable symbol, usually followed by an if-block which contains all other dependent symbols.
Use this instead of having a `depends on` line to each symbol. Guard all symbols, even if they originally were not guarded, since they don't do anything useful unless the global enable option is selected.
Change-Id: If5347187b07a46192f0063011ab197b5047f555f Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/common/block/gpio/Kconfig M src/soc/intel/common/block/sgx/Kconfig M src/soc/intel/common/block/uart/Kconfig 3 files changed, 12 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/45043/1
diff --git a/src/soc/intel/common/block/gpio/Kconfig b/src/soc/intel/common/block/gpio/Kconfig index bdbc323..753d8e0 100644 --- a/src/soc/intel/common/block/gpio/Kconfig +++ b/src/soc/intel/common/block/gpio/Kconfig @@ -4,42 +4,40 @@ help Intel Processor common GPIO support
+if SOC_INTEL_COMMON_BLOCK_GPIO + # Use to program Interrupt Polarity Control (IPCx) register # Each bit represents IRQx Active High Polarity Disable configuration: # when set to 1, the interrupt polarity associated with IRQx is inverted # to appear as Active Low to IOAPIC and vice versa config SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG - depends on SOC_INTEL_COMMON_BLOCK_GPIO bool default n
# Used to configure Pad Tolerance as 1.8V or 3.3V config SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL - depends on SOC_INTEL_COMMON_BLOCK_GPIO bool default n
# Used to configure IOSSTATE and IOSTERM config SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY - depends on SOC_INTEL_COMMON_BLOCK_GPIO bool default n
# Used to provide support for legacy macros config SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS - depends on SOC_INTEL_COMMON_BLOCK_GPIO bool default n
# Indicate if multiple ACPI devices are used for each gpio community. config SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES - depends on SOC_INTEL_COMMON_BLOCK_GPIO bool default n
# Indicate if SoC supports dual-routing of GPIOs (to different paths like SCI, # NMI, SMI, IOAPIC). This is required to support IRQ and wake on the same pad. config SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT - depends on SOC_INTEL_COMMON_BLOCK_GPIO bool default n + +endif diff --git a/src/soc/intel/common/block/sgx/Kconfig b/src/soc/intel/common/block/sgx/Kconfig index 6e8323f..771c54c 100644 --- a/src/soc/intel/common/block/sgx/Kconfig +++ b/src/soc/intel/common/block/sgx/Kconfig @@ -6,16 +6,16 @@ help Intel Processor common SGX support
+if SOC_INTEL_COMMON_BLOCK_SGX + config SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY bool - depends on SOC_INTEL_COMMON_BLOCK_SGX default n help Lock memory before SGX activation. This is only needed if MCHECK does not do it.
config SOC_INTEL_COMMON_BLOCK_SGX_ENABLE bool "Enable Software Guard Extensions (SGX) if available" - depends on SOC_INTEL_COMMON_BLOCK_SGX default n help Intel Software Guard Extensions (SGX) is a set of new CPU instructions that can be @@ -70,3 +70,5 @@ bool "Disabled"
endchoice + +endif diff --git a/src/soc/intel/common/block/uart/Kconfig b/src/soc/intel/common/block/uart/Kconfig index e731465..2de2a3a 100644 --- a/src/soc/intel/common/block/uart/Kconfig +++ b/src/soc/intel/common/block/uart/Kconfig @@ -4,21 +4,20 @@ help Intel Processor common UART support
+if SOC_INTEL_COMMON_BLOCK_UART + config SOC_INTEL_COMMON_BLOCK_UART_LPSS_CLK_M_VAL - depends on SOC_INTEL_COMMON_BLOCK_UART hex help Clock m-divisor value for m/n divider
config SOC_INTEL_COMMON_BLOCK_UART_LPSS_CLK_N_VAL - depends on SOC_INTEL_COMMON_BLOCK_UART hex help Clock m-divisor value for m/n divider
config INTEL_LPSS_UART_FOR_CONSOLE bool - depends on SOC_INTEL_COMMON_BLOCK_UART select DRIVERS_UART_8250MEM_32 select FIXED_UART_FOR_CONSOLE help @@ -26,3 +25,5 @@ for the coreboot console. WARNING: UART_FOR_CONSOLE has to be set to a correct value, otherwise wrong pad configurations might be selected. + +endif
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45043 )
Change subject: soc/intel/common/block/*/Kconfig: Guard options with if-blocks ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/45043/1/src/soc/intel/common/block/... File src/soc/intel/common/block/uart/Kconfig:
https://review.coreboot.org/c/coreboot/+/45043/1/src/soc/intel/common/block/... PS1, Line 9: SOC_INTEL_COMMON_BLOCK_UART_LPSS_CLK_M_VAL Unused symbol?
grep -r SOC_INTEL_COMMON_BLOCK_UART_LPSS_CLK_M_VAL , gives nothing
https://review.coreboot.org/c/coreboot/+/45043/1/src/soc/intel/common/block/... PS1, Line 14: SOC_INTEL_COMMON_BLOCK_UART_LPSS_CLK_N_VAL unused ?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45043 )
Change subject: soc/intel/common/block/*/Kconfig: Guard options with if-blocks ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45043/1/src/soc/intel/common/block/... File src/soc/intel/common/block/uart/Kconfig:
https://review.coreboot.org/c/coreboot/+/45043/1/src/soc/intel/common/block/... PS1, Line 9: SOC_INTEL_COMMON_BLOCK_UART_LPSS_CLK_M_VAL
Unused symbol? […]
sure, but that should be done in another change. I'll do it later today
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45043
to look at the new patch set (#2).
Change subject: soc/intel/common/block/*/Kconfig: Guard options with if-blocks ......................................................................
soc/intel/common/block/*/Kconfig: Guard options with if-blocks
The usual structure of these files is a global enable symbol, usually followed by an if-block which contains all other dependent symbols.
Use this instead of having a `depends on` line to each symbol. Guard all symbols, even if they originally were not guarded, since they don't do anything useful unless the global enable option is selected.
Change-Id: If5347187b07a46192f0063011ab197b5047f555f Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/common/block/gpio/Kconfig M src/soc/intel/common/block/sgx/Kconfig M src/soc/intel/common/block/uart/Kconfig 3 files changed, 12 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/45043/2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45043 )
Change subject: soc/intel/common/block/*/Kconfig: Guard options with if-blocks ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/45043/1/src/soc/intel/common/block/... File src/soc/intel/common/block/uart/Kconfig:
https://review.coreboot.org/c/coreboot/+/45043/1/src/soc/intel/common/block/... PS1, Line 9: SOC_INTEL_COMMON_BLOCK_UART_LPSS_CLK_M_VAL
sure, but that should be done in another change. […]
Done
https://review.coreboot.org/c/coreboot/+/45043/1/src/soc/intel/common/block/... PS1, Line 14: SOC_INTEL_COMMON_BLOCK_UART_LPSS_CLK_N_VAL
unused ?
Done
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45043 )
Change subject: soc/intel/common/block/*/Kconfig: Guard options with if-blocks ......................................................................
Patch Set 3: Code-Review+2
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45043 )
Change subject: soc/intel/common/block/*/Kconfig: Guard options with if-blocks ......................................................................
soc/intel/common/block/*/Kconfig: Guard options with if-blocks
The usual structure of these files is a global enable symbol, usually followed by an if-block which contains all other dependent symbols.
Use this instead of having a `depends on` line to each symbol. Guard all symbols, even if they originally were not guarded, since they don't do anything useful unless the global enable option is selected.
Change-Id: If5347187b07a46192f0063011ab197b5047f555f Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/45043 Reviewed-by: Subrata Banik subrata.banik@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/common/block/gpio/Kconfig M src/soc/intel/common/block/sgx/Kconfig M src/soc/intel/common/block/uart/Kconfig 3 files changed, 12 insertions(+), 9 deletions(-)
Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved
diff --git a/src/soc/intel/common/block/gpio/Kconfig b/src/soc/intel/common/block/gpio/Kconfig index bdbc323..753d8e0 100644 --- a/src/soc/intel/common/block/gpio/Kconfig +++ b/src/soc/intel/common/block/gpio/Kconfig @@ -4,42 +4,40 @@ help Intel Processor common GPIO support
+if SOC_INTEL_COMMON_BLOCK_GPIO + # Use to program Interrupt Polarity Control (IPCx) register # Each bit represents IRQx Active High Polarity Disable configuration: # when set to 1, the interrupt polarity associated with IRQx is inverted # to appear as Active Low to IOAPIC and vice versa config SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG - depends on SOC_INTEL_COMMON_BLOCK_GPIO bool default n
# Used to configure Pad Tolerance as 1.8V or 3.3V config SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL - depends on SOC_INTEL_COMMON_BLOCK_GPIO bool default n
# Used to configure IOSSTATE and IOSTERM config SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY - depends on SOC_INTEL_COMMON_BLOCK_GPIO bool default n
# Used to provide support for legacy macros config SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS - depends on SOC_INTEL_COMMON_BLOCK_GPIO bool default n
# Indicate if multiple ACPI devices are used for each gpio community. config SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES - depends on SOC_INTEL_COMMON_BLOCK_GPIO bool default n
# Indicate if SoC supports dual-routing of GPIOs (to different paths like SCI, # NMI, SMI, IOAPIC). This is required to support IRQ and wake on the same pad. config SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT - depends on SOC_INTEL_COMMON_BLOCK_GPIO bool default n + +endif diff --git a/src/soc/intel/common/block/sgx/Kconfig b/src/soc/intel/common/block/sgx/Kconfig index 6e8323f..771c54c 100644 --- a/src/soc/intel/common/block/sgx/Kconfig +++ b/src/soc/intel/common/block/sgx/Kconfig @@ -6,16 +6,16 @@ help Intel Processor common SGX support
+if SOC_INTEL_COMMON_BLOCK_SGX + config SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY bool - depends on SOC_INTEL_COMMON_BLOCK_SGX default n help Lock memory before SGX activation. This is only needed if MCHECK does not do it.
config SOC_INTEL_COMMON_BLOCK_SGX_ENABLE bool "Enable Software Guard Extensions (SGX) if available" - depends on SOC_INTEL_COMMON_BLOCK_SGX default n help Intel Software Guard Extensions (SGX) is a set of new CPU instructions that can be @@ -70,3 +70,5 @@ bool "Disabled"
endchoice + +endif diff --git a/src/soc/intel/common/block/uart/Kconfig b/src/soc/intel/common/block/uart/Kconfig index 7d30c41..3437ec7 100644 --- a/src/soc/intel/common/block/uart/Kconfig +++ b/src/soc/intel/common/block/uart/Kconfig @@ -4,9 +4,10 @@ help Intel Processor common UART support
+if SOC_INTEL_COMMON_BLOCK_UART + config INTEL_LPSS_UART_FOR_CONSOLE bool - depends on SOC_INTEL_COMMON_BLOCK_UART select DRIVERS_UART_8250MEM_32 select FIXED_UART_FOR_CONSOLE help @@ -14,3 +15,5 @@ for the coreboot console. WARNING: UART_FOR_CONSOLE has to be set to a correct value, otherwise wrong pad configurations might be selected. + +endif
Angel Pons has created a revert of this change. ( https://review.coreboot.org/c/coreboot/+/45043 )
Change subject: soc/intel/common/block/*/Kconfig: Guard options with if-blocks ......................................................................
-
Angel Pons (Code Review) -
HAOUAS Elyes (Code Review)
-
Subrata Banik (Code Review)