coreboot-gerrit September 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: volteer: set GSPI CS to deasserted by default
by Caveh Jalali (Code Review) 15 Sep '20

15 Sep '20

Hello Jes Klinke, build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro, Andrey Pronin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45384 to look at the new patch set (#2). Change subject: volteer: set GSPI CS to deasserted by default ...................................................................... volteer: set GSPI CS to deasserted by default This sets the state of GSPI chip select to 1 (deasserted) as applied by the FSP during the silicon init phase. GSPI 0 and 1 are set to CS mode manual in the SerialIoGSpiCsMode section which means we need to explicitly configure CS to deasserted in the SerialIoGSpiCsState section. GSPI0 is the CR50 and GSPI1 is the fingerprint sensor. We were running into problems where the normal expected CS toggle sequence to wake up CR50 did not work because CS was already asserted when it was expected to be deasserted, leading to TPM timeouts. BUG=b:168090038 TEST=booted on volteer, no more "TPM flow control failure" messages; verified fingerprint enrollment still works. Change-Id: I47aa5db429d75e66095d58a1eb77963dcfc3b9f3 Signed-off-by: Caveh Jalali <caveh(a)chromium.org> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/45384/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47aa5db429d75e66095d58a1eb77963dcfc3b9f3 Gerrit-Change-Number: 45384 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Andrey Pronin <apronin(a)chromium.org> Gerrit-Reviewer: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: security/tpm/tss/tcg-2.0: add const to marshalling functions
by Caveh Jalali (Code Review) 15 Sep '20

15 Sep '20

Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45409 ) Change subject: security/tpm/tss/tcg-2.0: add const to marshalling functions ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/45409/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45409/2//COMMIT_MSG@9 PS2, Line 9: This adds the const qualifier to inputs of marshalling functions. > … as the variables are only read and not changed. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/45409 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I099bf46c928733aff2c1d1c134deec35da6309ba Gerrit-Change-Number: 45409 Gerrit-PatchSet: 3 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 15 Sep 2020 20:46:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: security/tpm/tss/tcg-2.0: add const to marshalling functions
by Caveh Jalali (Code Review) 15 Sep '20

15 Sep '20

Hello build bot (Jenkins), Tim Wawrzynczak, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45409 to look at the new patch set (#3). Change subject: security/tpm/tss/tcg-2.0: add const to marshalling functions ...................................................................... security/tpm/tss/tcg-2.0: add const to marshalling functions This adds the const qualifier to inputs of marshalling functions as they are intended to be read-only. Change-Id: I099bf46c928733aff2c1d1c134deec35da6309ba Signed-off-by: Caveh Jalali <caveh(a)chromium.org> --- M src/security/tpm/tss/tcg-2.0/tss_marshaling.c M src/security/tpm/tss/tcg-2.0/tss_marshaling.h 2 files changed, 30 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/45409/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/45409 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I099bf46c928733aff2c1d1c134deec35da6309ba Gerrit-Change-Number: 45409 Gerrit-PatchSet: 3 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/picasso/acpi/sb_pci0_fch: remove duplicate I/O range reservation
by Felix Held (Code Review) 15 Sep '20

15 Sep '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45368 ) Change subject: soc/amd/picasso/acpi/sb_pci0_fch: remove duplicate I/O range reservation ...................................................................... soc/amd/picasso/acpi/sb_pci0_fch: remove duplicate I/O range reservation This I/O region is already covered by the range declared right above the deleted one. TEST=Linux stops complaining about overlapping I/O regions. BRANCH=zork Change-Id: I149fb0dc85bfe721a6b0d81e4e9c197194718876 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/acpi/sb_pci0_fch.asl 1 file changed, 0 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/45368/1 diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl index 8f4993f..9208e13 100644 --- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl @@ -49,13 +49,6 @@ 0x0000, /* translation */ 0x0cf8 /* length */ ) - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x03b0, /* range minimum */ - 0x03df, /* range maximum */ - 0x0000, /* translation */ - 0x0030 /* length */ - ) WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, 0x0000, /* address granularity */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45368 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I149fb0dc85bfe721a6b0d81e4e9c197194718876 Gerrit-Change-Number: 45368 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: security/tpm/tss/tcg-2.0: add const to marshalling functions
by Tim Wawrzynczak (Code Review) 15 Sep '20

15 Sep '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45409 ) Change subject: security/tpm/tss/tcg-2.0: add const to marshalling functions ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45409 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I099bf46c928733aff2c1d1c134deec35da6309ba Gerrit-Change-Number: 45409 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 15 Sep 2020 19:50:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/ironlake/raminit: Fix compiler bug
by Patrick Rudolph (Code Review) 15 Sep '20

15 Sep '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45174 ) Change subject: nb/intel/ironlake/raminit: Fix compiler bug ...................................................................... nb/intel/ironlake/raminit: Fix compiler bug This fixes e1d1fe454cf27d6b1c2ef5625f1cefc1a9c6ec9d initialize 'reply.command'. The compiler now optimized away the final condition, resulting in a binary that always calls die(). Fix that behaviour by using volatile. Tested on Lenovo T410: Boots again into Linux. Change-Id: I63cffc8812bd22695c01bf57283ca593b12e3d87 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/northbridge/intel/ironlake/raminit.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/45174/1 diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index 81ba450..5d58b27 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -1770,7 +1770,7 @@ static void send_heci_uma_message(struct raminfo *info) { - struct uma_reply { + volatile struct uma_reply { u8 group_id; u8 command; u8 reserved; -- To view, visit https://review.coreboot.org/c/coreboot/+/45174 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63cffc8812bd22695c01bf57283ca593b12e3d87 Gerrit-Change-Number: 45174 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel: cnl,icl,elh,jsl,tgl: enable C6DRAM
by Tim Wawrzynczak (Code Review) 15 Sep '20

15 Sep '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45417 ) Change subject: soc/intel: cnl,icl,elh,jsl,tgl: enable C6DRAM ...................................................................... Patch Set 2: > Patch Set 1: > > > Patch Set 1: > > > > There are 0 mainboards that use this feature right now, and you want to enable it for all of those platforms? Have you tested it on any? > > Heh, I did not say this shall be merged without any testing ;) I just didn't have the time earlier to add all relevant people. > > However, this power gating feature - to my knowlege - doesn't depend on board design, thus shouldn't cause any issues. Hopefully. > > @all Would be great if you could test this on your boards and give feedback. Feel free to add people, if you think someone is missing. Thanks! Gotcha, I will test on what I have. -- To view, visit https://review.coreboot.org/c/coreboot/+/45417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I556dba59bc06c9101bdfdfd6aee00610aac516e3 Gerrit-Change-Number: 45417 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Andrew McRae <amcrae(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jonas Löffelholz <jonas.loeffelholz(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 15 Sep 2020 18:47:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: cnl,icl,elh,jsl,tgl: enable C6DRAM
by Michael Niewöhner (Code Review) 15 Sep '20

15 Sep '20

Hello Felix Singer, Lijian Zhao, John Su, Anil Kumar K, build bot (Jenkins), David Wu, Patrick Georgi, Maulik V Vaghela, Matt DeVillier, Ravishankar Sarawadi, Alex Levin, Paul Menzel, Andrey Petrov, Kyösti Mälkki, Aaron Durbin, Patrick Rudolph, Nathaniel L Desimone, Nico Huber, Caveh Jalali, Christian Walter, Andrey Petrov, Edward O'Callaghan, Tim Chen, EricR Lai, Jonas Löffelholz, Shaunak Saha, Furquan Shaikh, Wonkyu Kim, Jeremy Soller, Thomas Heijligen, Subrata Banik, Aamir Bohra, Paul Fagerburg, Andrew McRae, Elyes HAOUAS, Tim Wawrzynczak, Nick Vaccaro, Thejaswani Putta, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45417 to look at the new patch set (#2). Change subject: soc/intel: cnl,icl,elh,jsl,tgl: enable C6DRAM ...................................................................... soc/intel: cnl,icl,elh,jsl,tgl: enable C6DRAM C6DRAM is not board design specific, so remove it from devicetree config. Instead, enable it on supported platforms. From Intel doc# 615211-005: The C6DRAM feature saves the processor internal state at Package C6 and deeper to DRAM instead of on-die SRAM. When the processor state has been saved to DRAM, the dedicated save/restore SRAM modules are power gated, enabling idle power savings. This power gating feature - to my knowlege - doesn't depend on board design, thus shouldn't cause any issues. Hopefully. Boards that need testing / have been tested: [] google/dedede [] google/deltaur [] google/drallion [] google/hatch [] google/sarien [] google/volteer [] intel/cannonlake_rvp [] intel/coffeelake_rvp [] intel/jasperlake_rvp [] intel/tglrvp [] prodrive/hermes [] purism/librem_whl [x] system76/lemp9 Change-Id: I556dba59bc06c9101bdfdfd6aee00610aac516e3 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/romstage/fsp_params.c M src/soc/intel/elkhartlake/chip.h M src/soc/intel/icelake/chip.h M src/soc/intel/icelake/romstage/fsp_params.c M src/soc/intel/jasperlake/chip.h M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params.c 8 files changed, 3 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/45417/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I556dba59bc06c9101bdfdfd6aee00610aac516e3 Gerrit-Change-Number: 45417 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Andrew McRae <amcrae(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jonas Löffelholz <jonas.loeffelholz(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel: cnl,icl,elh,jsl,tgl: enable C6DRAM
by Michael Niewöhner (Code Review) 15 Sep '20

15 Sep '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45417 ) Change subject: soc/intel: cnl,icl,elh,jsl,tgl: enable C6DRAM ...................................................................... Patch Set 1: > Patch Set 1: > > There are 0 mainboards that use this feature right now, and you want to enable it for all of those platforms? Have you tested it on any? Heh, I did not say this shall be merged without any testing ;) I just didn't have the time earlier to add all relevant people. However, this power gating feature - to my knowlege - doesn't depend on board design, thus shouldn't cause any issues. Hopefully. @all Would be great if you could test this on your boards and give feedback. Feel free to add people, if you think someone is missing. Thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/45417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I556dba59bc06c9101bdfdfd6aee00610aac516e3 Gerrit-Change-Number: 45417 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Andrew McRae <amcrae(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jonas Löffelholz <jonas.loeffelholz(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 15 Sep 2020 18:35:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: cnl,icl,elh,jsl,tgl: enable C6DRAM
by Tim Wawrzynczak (Code Review) 15 Sep '20

15 Sep '20

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coreboot-gerrit September 2020