coreboot-gerrit September 2020

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Change in coreboot[master]: soc/mediatek: move power status bits under each chip
by CK HU (Code Review) 16 Sep '20

16 Sep '20

Hello Weiyi Lu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45393 to review the following change. Change subject: soc/mediatek: move power status bits under each chip ...................................................................... soc/mediatek: move power status bits under each chip The power status bits of display and audio of MT8192 are different from the bits of MT8173 & MT8183, so move those under each chip. Signed-off-by: … [View More]Weiyi Lu <weiyi.lu(a)mediatek.com> Change-Id: Iaa211b8db733d8aa52d93af9e507042bf0984d55 --- M src/soc/mediatek/common/mtcmos.c M src/soc/mediatek/mt8173/include/soc/spm.h M src/soc/mediatek/mt8183/include/soc/spm.h 3 files changed, 4 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/45393/1 diff --git a/src/soc/mediatek/common/mtcmos.c b/src/soc/mediatek/common/mtcmos.c index cbec250..cfd148c 100644 --- a/src/soc/mediatek/common/mtcmos.c +++ b/src/soc/mediatek/common/mtcmos.c @@ -21,11 +21,6 @@ PWR_RST_B = 1U << 0 }; -enum { - DISP_PWR_STA_MASK = 0x1 << 3, - AUDIO_PWR_STA_MASK = 0x1 << 24, -}; - static void mtcmos_power_on(const struct power_domain_data *pd) { write32(&mtk_spm->poweron_config_set, diff --git a/src/soc/mediatek/mt8173/include/soc/spm.h b/src/soc/mediatek/mt8173/include/soc/spm.h index 0d8e0d3..efc04d1 100644 --- a/src/soc/mediatek/mt8173/include/soc/spm.h +++ b/src/soc/mediatek/mt8173/include/soc/spm.h @@ -11,8 +11,10 @@ }; enum { + DISP_PWR_STA_MASK = 0x1 << 3, DISP_SRAM_PDN_MASK = 0xf << 8, DISP_SRAM_ACK_MASK = 0x1 << 12, + AUDIO_PWR_STA_MASK = 0x1 << 24, AUDIO_SRAM_PDN_MASK = 0xf << 8, AUDIO_SRAM_ACK_MASK = 0xf << 12, }; diff --git a/src/soc/mediatek/mt8183/include/soc/spm.h b/src/soc/mediatek/mt8183/include/soc/spm.h index fa6d6d0..327355a 100644 --- a/src/soc/mediatek/mt8183/include/soc/spm.h +++ b/src/soc/mediatek/mt8183/include/soc/spm.h @@ -117,8 +117,10 @@ #define PCM_SW_INT_ALL (0x3FF) enum { + DISP_PWR_STA_MASK = 0x1 << 3, DISP_SRAM_PDN_MASK = 0x1 << 8, DISP_SRAM_ACK_MASK = 0x1 << 12, + AUDIO_PWR_STA_MASK = 0x1 << 24, AUDIO_SRAM_PDN_MASK = 0xf << 8, AUDIO_SRAM_ACK_MASK = 0xf << 12, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/45393 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa211b8db733d8aa52d93af9e507042bf0984d55 Gerrit-Change-Number: 45393 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Weiyi Lu <weiyi.lu(a)mediatek.com> Gerrit-MessageType: newchange [View Less]

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Change in coreboot[master]: [DONOTSUBMIT] drivers/pc80/tpm: Poll VID and DID.
by Masanori Ogino (Code Review) 16 Sep '20

16 Sep '20

Masanori Ogino has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45442 ) Change subject: [DONOTSUBMIT] drivers/pc80/tpm: Poll VID and DID. ...................................................................... [DONOTSUBMIT] drivers/pc80/tpm: Poll VID and DID. Signed-off-by: Masanori Ogino <mogino(a)acm.org> Change-Id: I49000b9dd5560e8a36c925b3ad1dbfc78d6c14af --- M src/drivers/pc80/tpm/tis.c 1 file changed, 14 insertions(+), 3 deletions(-) git pull … [View More]

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Change in coreboot[master]: drivers/aspeed/common: Reduce severity of `EDID not found` log message
by Angel Pons (Code Review) 16 Sep '20

16 Sep '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45234 ) Change subject: drivers/aspeed/common: Reduce severity of `EDID not found` log message ...................................................................... drivers/aspeed/common: Reduce severity of `EDID not found` log message Servers often run headless, so a missing EDID isn't a problem. However, we still need to initialize a framebuffer for the BMC's KVM function. Reduce the log level to … [View More]

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Change in coreboot[master]: mb/google/dedede/var/madoo: Enable keyboard backlight feature
by Ian Feng (Code Review) 16 Sep '20

16 Sep '20

Ian Feng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45330 ) Change subject: mb/google/dedede/var/madoo: Enable keyboard backlight feature ...................................................................... mb/google/dedede/var/madoo: Enable keyboard backlight feature This enables the keyboard backlight feature in ACPI for madoo. BUG=b:167943993 TEST=Verified 'kbd_backlight' shows up in the '/sys/class/leds'. Signed-off-by: Ian Feng <ian_feng(a)… [View More]

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Change in coreboot[master]: drivers/spi/tpm: Improve error checking
by 9elements QA (Code Review) 16 Sep '20

16 Sep '20

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45232 ) Change subject: drivers/spi/tpm: Improve error checking ...................................................................... Patch Set 4: Automatic boot test returned (PASS/FAIL/TOTAL): 8/1/9 "QEMU x86 q35/ich9" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/19524 "QEMU x86 q35/ich9" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/19523 "QEMU x86 … [View More]

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Change in coreboot[master]: security/tpm: Add generalized ACPI table generation
by Masanori Ogino (Code Review) 16 Sep '20

16 Sep '20

Masanori Ogino has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29194 ) Change subject: security/tpm: Add generalized ACPI table generation ...................................................................... Patch Set 3: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/29194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: … [View More]

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Change in coreboot[master]: dptf
by Ren Kuo (Code Review) 16 Sep '20

16 Sep '20

Ren Kuo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45441 ) Change subject: dptf ...................................................................... dptf Change-Id: I887d494ff097a881d519a456f24578a278323051 --- M src/mainboard/google/dedede/variants/magolor/overridetree.cb 1 file changed, 42 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/45441/1 diff --git a/src/mainboard/google/dedede/variants/… [View More]magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb index 0daaea3..f0d7439 100644 --- a/src/mainboard/google/dedede/variants/magolor/overridetree.cb +++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb @@ -40,7 +40,49 @@ }, }" + register "power_limits_config" = "{ + .tdp_pl1_override = 7, + .tdp_pl2_override = 12, + }" + + register "tcc_offset" = "15" # TCC of 90C + device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + register "options.tsr[0].desc" = ""Memory"" + register "options.tsr[1].desc" = ""Ambient"" + + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 90, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 6000)" + register "policies.passive[2]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 60, 5000)" + + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 105, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 80, SHUTDOWN)" + register "policies.critical[2]" = "DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN)" + + register "controls.power_limits.pl1" = "{ + .min_power = 300, + .max_power = 7000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 7000, + .max_power = 12000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 1000,}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf[0]" = "{ 255, 3000 }" + register "controls.charger_perf[1]" = "{ 24, 1500 }" + register "controls.charger_perf[2]" = "{ 16, 1000 }" + register "controls.charger_perf[3]" = "{ 8, 500 }" + + device generic 0 on end + end + end # SA Thermal device device pci 05.0 on # IPU - MIPI Camera chip drivers/intel/mipi_camera register "acpi_uid" = "0x50000" -- To view, visit https://review.coreboot.org/c/coreboot/+/45441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I887d494ff097a881d519a456f24578a278323051 Gerrit-Change-Number: 45441 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange [View Less]

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Change in coreboot[master]: mb/google/dedede: Replace static Camera ACPI by driver for WDoo
by Varshit B Pandya (Code Review) 16 Sep '20

16 Sep '20

Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44397 ) Change subject: mb/google/dedede: Replace static Camera ACPI by driver for WDoo ...................................................................... mb/google/dedede: Replace static Camera ACPI by driver for WDoo Signed-off-by: Pandya, Varshit B <varshit.b.pandya(a)intel.com> Change-Id: Ib7e875d297c04f35d4e980ff33d9a3767d2910ac --- M src/mainboard/google/dedede/Kconfig M src/… [View More]mainboard/google/dedede/Kconfig.name M src/mainboard/google/dedede/variants/waddledoo/overridetree.cb 3 files changed, 141 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/44397/1 diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index d5057c71..e4c6fb2 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -107,10 +107,4 @@ default "wheelie" if BOARD_GOOGLE_WHEELIE default "magolor" if BOARD_GOOGLE_MAGOLOR -config VARIANT_HAS_CAMERA_ACPI - bool - default n - help - Select this option to enable camera ACPI support on the variant. - endif #BOARD_GOOGLE_BASEBOARD_DEDEDE diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 40738a0..b168f19 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -42,7 +42,6 @@ select BOARD_ROMSIZE_KB_32768 select DRIVERS_GENERIC_MAX98357A select DRIVERS_I2C_DA7219 - select VARIANT_HAS_CAMERA_ACPI config BOARD_GOOGLE_WADDLEDEE bool "Waddledee" diff --git a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb index 3943882..7cc2351 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb @@ -50,6 +50,21 @@ }, }" device domain 0 on + device pci 05.0 on + chip drivers/intel/mipi_camera + register "acpi_uid" = "0x50000" + register "acpi_name" = ""IPU0"" + register "device_type" = "INTEL_ACPI_CAMERA_CIO2" + + register "cio2_num_ports" = "2" + register "cio2_lanes_used" = "{2,2}" + register "cio2_lane_endpoint[0]" = ""^I2C3.CAM0"" + register "cio2_lane_endpoint[1]" = ""^I2C3.CAM1"" + register "cio2_prt[0]" = "0" + register "cio2_prt[1]" = "2" + device generic 0 on end + end + end device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on @@ -122,6 +137,132 @@ device i2c 10 on end end end # I2C 2 + device pci 15.3 on #I2C #3 CAM0 CAM1 and VCM0 + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI8856"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM1"" + register "chip_name" = ""Ov 8856 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + + register "ssdb.lanes_used" = "2" + register "ssdb.link_used" = "1" + register "ssdb.vcm_type" = "0x0C" + register "vcm_name" = ""VCM0"" + register "num_freq_entries" = "1" + register "link_freq[0]" = "DEFAULT_LINK_FREQ" + register "remote_name" = ""IPU0"" + + register "has_power_resource" = "1" + #Controls + register "clk_panel.clks[0].clknum" = "1" #IMGCLKOUT_1 + register "clk_panel.clks[0].freq" = "1" #19.2 Mhz + + register "gpio_panel.gpio[0].gpio_num" = "GPP_D4" #power_enable + register "gpio_panel.gpio[1].gpio_num" = "GPP_C19" #reset + + #_ON + register "on_seq.ops_cnt" = "4" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" + + #_OFF + register "off_seq.ops_cnt" = "3" + register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + + device i2c 36 on end + end + chip drivers/intel/mipi_camera + register "acpi_hid" = "ACPI_DT_NAMESPACE_HID" + register "acpi_uid" = "3" + register "acpi_name" = ""VCM0"" + register "chip_name" = ""DW AF DAC"" + register "device_type" = "INTEL_ACPI_CAMERA_VCM" + + register "pr0" = ""\\_SB.PCI0.I2C5.CAM1.PRIC"" + register "vcm_compat" = ""dongwoon,dw9714"" + + register "ssdb.lanes_used" = "2" + register "num_freq_entries" = "1" + register "link_freq[0]" = "DEFAULT_LINK_FREQ" + register "remote_name" = ""IPU0"" + device i2c 0C on end + end + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI2740"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM0"" + register "chip_name" = ""Ov 2740 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + register "has_power_resource" = "1" + + register "ssdb.lanes_used" = "2" + register "num_freq_entries" = "1" + register "link_freq[0]" = "360000000" + register "remote_name" = ""IPU0"" + + #Controls + register "clk_panel.clks[0].clknum" = "0" #IMGCLKOUT_3 + register "clk_panel.clks[0].freq" = "1" #19.2 Mhz + + register "gpio_panel.gpio[0].gpio_num" = "GPP_D5" #reset + register "gpio_panel.gpio[1].gpio_num" = "GPP_B14" #power + + #_ON + register "on_seq.ops_cnt" = "4" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" + + #_OFF + register "off_seq.ops_cnt" = "3" + register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + + device i2c 10 on end + end + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI9734"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM0"" + register "chip_name" = ""Ov 2740 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + register "has_power_resource" = "1" + + register "ssdb.lanes_used" = "2" + register "num_freq_entries" = "1" + register "link_freq[0]" = "360000000" + register "remote_name" = ""IPU0"" + + #Controls + register "clk_panel.clks[0].clknum" = "0" #IMGCLKOUT_3 + register "clk_panel.clks[0].freq" = "1" #19.2 Mhz + + register "gpio_panel.gpio[0].gpio_num" = "GPP_D5" #reset + register "gpio_panel.gpio[1].gpio_num" = "GPP_B14" #power + + #_ON + register "on_seq.ops_cnt" = "4" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" + + #_OFF + register "off_seq.ops_cnt" = "3" + register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + + device i2c 10 on end + end + end device pci 1c.7 on chip drivers/intel/wifi register "wake" = "GPE0_DW2_03" -- To view, visit https://review.coreboot.org/c/coreboot/+/44397 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7e875d297c04f35d4e980ff33d9a3767d2910ac Gerrit-Change-Number: 44397 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-MessageType: newchange [View Less]

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Change in coreboot[master]: drivers/intel/mipi_camera: Remove unused condition
by Varshit B Pandya (Code Review) 16 Sep '20

16 Sep '20

Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45091 ) Change subject: drivers/intel/mipi_camera: Remove unused condition ...................................................................... drivers/intel/mipi_camera: Remove unused condition NVM also uses PRP0001 as HID hence combining it with condition for VCM Signed-off-by: Pandya, Varshit B <varshit.b.pandya(a)intel.com> Change-Id: Iad7afa7b3170982eb5d6215e766f3e98f7a89213 --- M … [View More]

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Change in coreboot[master]: drivers/spi/tpm: Improve error checking
by Patrick Georgi (Code Review) 16 Sep '20

16 Sep '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45232 ) Change subject: drivers/spi/tpm: Improve error checking ...................................................................... drivers/spi/tpm: Improve error checking This adds error checking in paths that previously ignored TPM communication errors. We hit this case occasionally during "Checking cr50 for pending updates"; previously we would go down this path and eventually time out using … [View More]MAX_STATUS_TIMEOUT, which is 2 minutes. Now, we detect the failure and return with an error indication instead of timing out after a long time. The root cause of the communication error is an open issue. BUG=b:168090038 TEST=booted on volteer, observed error handling when "Checking cr50 for pending updates" fails. Signed-off-by: Caveh Jalali <caveh(a)chromium.org> Change-Id: Ia8a1202000abce1857ee694b06b1478e6b045069 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45232 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jes Klinke <jbk(a)chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/drivers/spi/tpm/tpm.c 1 file changed, 39 insertions(+), 17 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Jes Klinke: Looks good to me, approved diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c index 66db671..d65decd 100644 --- a/src/drivers/spi/tpm/tpm.c +++ b/src/drivers/spi/tpm/tpm.c @@ -348,7 +348,7 @@ return tpm2_read_reg(TPM_STS_REG, status, sizeof(*status)); } -static int write_tpm_sts(uint32_t status) +static int __must_check write_tpm_sts(uint32_t status) { return tpm2_write_reg(TPM_STS_REG, &status, sizeof(status)); } @@ -688,9 +688,9 @@ * Transfer requested number of bytes to or from TPM FIFO, accounting for the * current burst count value. */ -static void fifo_transfer(size_t transfer_size, - union fifo_transfer_buffer buffer, - enum fifo_transfer_direction direction) +static int __must_check fifo_transfer(size_t transfer_size, + union fifo_transfer_buffer buffer, + enum fifo_transfer_direction direction) { size_t transaction_size; size_t burst_count; @@ -711,18 +711,23 @@ */ transaction_size = MIN(transaction_size, 64); - if (direction == fifo_receive) - tpm2_read_reg(TPM_DATA_FIFO_REG, - buffer.rx_buffer + handled_so_far, - transaction_size); - else - tpm2_write_reg(TPM_DATA_FIFO_REG, - buffer.tx_buffer + handled_so_far, - transaction_size); + if (direction == fifo_receive) { + if (!tpm2_read_reg(TPM_DATA_FIFO_REG, + buffer.rx_buffer + handled_so_far, + transaction_size)) + return 0; + } else { + if (!tpm2_write_reg(TPM_DATA_FIFO_REG, + buffer.tx_buffer + handled_so_far, + transaction_size)) + return 0; + } handled_so_far += transaction_size; } while (handled_so_far != transfer_size); + + return 1; } size_t tpm2_process_command(const void *tpm2_command, size_t command_size, @@ -755,7 +760,10 @@ } /* Let the TPM know that the command is coming. */ - write_tpm_sts(TPM_STS_COMMAND_READY); + if (!write_tpm_sts(TPM_STS_COMMAND_READY)) { + printk(BIOS_ERR, "TPM_STS_COMMAND_READY failed\n"); + return 0; + } /* * TPM commands and responses written to and read from the FIFO @@ -769,10 +777,17 @@ * burst count or the maximum PDU size, whatever is smaller. */ fifo_buffer.tx_buffer = cmd_body; - fifo_transfer(command_size, fifo_buffer, fifo_transmit); + if (!fifo_transfer(command_size, fifo_buffer, fifo_transmit)) { + printk(BIOS_ERR, "fifo_transfer %zd command bytes failed\n", + command_size); + return 0; + } /* Now tell the TPM it can start processing the command. */ - write_tpm_sts(TPM_STS_GO); + if (!write_tpm_sts(TPM_STS_GO)) { + printk(BIOS_ERR, "TPM_STS_GO failed\n"); + return 0; + } /* Now wait for it to report that the response is ready. */ expected_status_bits = TPM_STS_VALID | TPM_STS_DATA_AVAIL; @@ -815,7 +830,11 @@ */ bytes_to_go = payload_size - 1 - HEADER_SIZE; fifo_buffer.rx_buffer = rsp_body + HEADER_SIZE; - fifo_transfer(bytes_to_go, fifo_buffer, fifo_receive); + if (!fifo_transfer(bytes_to_go, fifo_buffer, fifo_receive)) { + printk(BIOS_ERR, "fifo_transfer %zd receive bytes failed\n", + bytes_to_go); + return 0; + } /* Verify that there is still data to read. */ read_tpm_sts(&status); @@ -840,7 +859,10 @@ } /* Move the TPM back to idle state. */ - write_tpm_sts(TPM_STS_COMMAND_READY); + if (!write_tpm_sts(TPM_STS_COMMAND_READY)) { + printk(BIOS_ERR, "TPM_STS_COMMAND_READY failed\n"); + return 0; + } return payload_size; } -- To view, visit https://review.coreboot.org/c/coreboot/+/45232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8a1202000abce1857ee694b06b1478e6b045069 Gerrit-Change-Number: 45232 Gerrit-PatchSet: 4 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged [View Less]

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coreboot-gerrit September 2020