coreboot-gerrit September 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/cannonlake: fix GPIO community numbering in ACPI
by Michael Niewöhner (Code Review) 17 Sep '20

17 Sep '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45209 ) Change subject: soc/intel/cannonlake: fix GPIO community numbering in ACPI ...................................................................... soc/intel/cannonlake: fix GPIO community numbering in ACPI This corrects the GPIO community numbers in CNL-LP ACPI code. Change-Id: I9f13a28d3e8f427859570a4d209304ae8444efd9 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45209 Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/cannonlake/acpi/gpio.asl 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/acpi/gpio.asl b/src/soc/intel/cannonlake/acpi/gpio.asl index 5deb26a..e3e1e8c 100644 --- a/src/soc/intel/cannonlake/acpi/gpio.asl +++ b/src/soc/intel/cannonlake/acpi/gpio.asl @@ -75,13 +75,13 @@ /* GPIO Community 2 */ If (LAnd (LGreaterEqual (Arg0, GPD0), LLessEqual (Arg0, GPD11))) { - Store (PID_GPIOCOM1, Local0) + Store (PID_GPIOCOM2, Local0) Subtract (Arg0, GPD0, Local1) } /* GPIO Community 3 */ If (LAnd (LGreaterEqual (Arg0, HDA_BCLK), LLessEqual (Arg0, GPIO_RSVD_38))) { - Store (PID_GPIOCOM1, Local0) + Store (PID_GPIOCOM3, Local0) Subtract (Arg0, HDA_BCLK, Local1) } /* GPIO Community 04*/ -- To view, visit https://review.coreboot.org/c/coreboot/+/45209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f13a28d3e8f427859570a4d209304ae8444efd9 Gerrit-Change-Number: 45209 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel: cnl,icl,elh,jsl,tgl: enable C6DRAM
by Michael Niewöhner (Code Review) 17 Sep '20

17 Sep '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45417 ) Change subject: soc/intel: cnl,icl,elh,jsl,tgl: enable C6DRAM ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/c/coreboot/+/45417/5//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45417/5//COMMIT_MSG@18 PS5, Line 18: knowlege > knowledge Done -- To view, visit https://review.coreboot.org/c/coreboot/+/45417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I556dba59bc06c9101bdfdfd6aee00610aac516e3 Gerrit-Change-Number: 45417 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Andrew McRae <amcrae(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jonas Löffelholz <jonas.loeffelholz(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 17 Sep 2020 10:35:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: cnl,icl,elh,jsl,tgl: enable C6DRAM
by Michael Niewöhner (Code Review) 17 Sep '20

17 Sep '20

Hello Felix Singer, build bot (Jenkins), Lijian Zhao, John Su, Anil Kumar K, David Wu, Patrick Georgi, Maulik V Vaghela, Matt DeVillier, Ravishankar Sarawadi, Paul Menzel, Alex Levin, Andrey Petrov, Kyösti Mälkki, Aaron Durbin, Patrick Rudolph, Nathaniel L Desimone, Nico Huber, Caveh Jalali, Christian Walter, Andrey Petrov, Edward O'Callaghan, Tim Chen, EricR Lai, Jonas Löffelholz, Shaunak Saha, Furquan Shaikh, Wonkyu Kim, Jeremy Soller, Thomas Heijligen, Subrata Banik, Aamir Bohra, Paul Fagerburg, Andrew McRae, Elyes HAOUAS, Tim Wawrzynczak, Nick Vaccaro, Thejaswani Putta, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45417 to look at the new patch set (#6). Change subject: soc/intel: cnl,icl,elh,jsl,tgl: enable C6DRAM ...................................................................... soc/intel: cnl,icl,elh,jsl,tgl: enable C6DRAM C6DRAM is not board design specific, so remove it from devicetree config. Instead, enable it on supported platforms. From Intel doc# 615211-005: The C6DRAM feature saves the processor internal state at Package C6 and deeper to DRAM instead of on-die SRAM. When the processor state has been saved to DRAM, the dedicated save/restore SRAM modules are power gated, enabling idle power savings. This power gating feature - to my knowledge - doesn't depend on board design, thus shouldn't cause any issues. Hopefully. Boards that need testing / have been tested: [] google/dedede [] google/deltaur [] google/drallion [] google/hatch [] google/sarien [] google/volteer [] intel/cannonlake_rvp [] intel/coffeelake_rvp [] intel/jasperlake_rvp [] intel/tglrvp [] prodrive/hermes [x] purism/librem_whl [x] system76/lemp9 Change-Id: I556dba59bc06c9101bdfdfd6aee00610aac516e3 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/romstage/fsp_params.c M src/soc/intel/elkhartlake/chip.h M src/soc/intel/icelake/chip.h M src/soc/intel/icelake/romstage/fsp_params.c M src/soc/intel/jasperlake/chip.h M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params.c 8 files changed, 3 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/45417/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/45417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I556dba59bc06c9101bdfdfd6aee00610aac516e3 Gerrit-Change-Number: 45417 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Andrew McRae <amcrae(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jonas Löffelholz <jonas.loeffelholz(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel: cnl,icl,elh,jsl,tgl: enable C6DRAM
by Paul Menzel (Code Review) 17 Sep '20

17 Sep '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45417 ) Change subject: soc/intel: cnl,icl,elh,jsl,tgl: enable C6DRAM ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/45417/5//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45417/5//COMMIT_MSG@18 PS5, Line 18: knowlege knowledge -- To view, visit https://review.coreboot.org/c/coreboot/+/45417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I556dba59bc06c9101bdfdfd6aee00610aac516e3 Gerrit-Change-Number: 45417 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Andrew McRae <amcrae(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jonas Löffelholz <jonas.loeffelholz(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 17 Sep 2020 09:46:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8192: Init PLL in bootblock
by CK HU (Code Review) 17 Sep '20

17 Sep '20

CK HU has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45395 ) Change subject: soc/mediatek/mt8192: Init PLL in bootblock ...................................................................... soc/mediatek/mt8192: Init PLL in bootblock Signed-off-by: CK Hu <ck.hu(a)mediatek.com> Change-Id: If16d244e07d9f369efd991132587a92e38200b45 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/bootblock.c 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/45395/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 8f37c7b..c7dbe51 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -4,6 +4,7 @@ bootblock-y += flash_controller.c bootblock-y += ../common/gpio.c gpio.c bootblock-y += ../common/mmu_operations.c +bootblock-y += ../common/pll.c pll.c bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c bootblock-y += ../common/timer.c bootblock-y += ../common/uart.c diff --git a/src/soc/mediatek/mt8192/bootblock.c b/src/soc/mediatek/mt8192/bootblock.c index 770c603..8dffe56 100644 --- a/src/soc/mediatek/mt8192/bootblock.c +++ b/src/soc/mediatek/mt8192/bootblock.c @@ -2,10 +2,12 @@ #include <bootblock_common.h> #include <soc/mmu_operations.h> +#include <soc/pll.h> #include <soc/wdt.h> void bootblock_soc_init(void) { mtk_mmu_init(); mtk_wdt_init(); + mt_pll_init(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/45395 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If16d244e07d9f369efd991132587a92e38200b45 Gerrit-Change-Number: 45395 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8192: Add mtcmos init support
by CK HU (Code Review) 17 Sep '20

17 Sep '20

Hello Weiyi Lu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45394 to review the following change. Change subject: soc/mediatek/mt8192: Add mtcmos init support ...................................................................... soc/mediatek/mt8192: Add mtcmos init support Using common mtcmos code to power on audio and display modules in SOC. TEST=Boots correctly on NT8192EVB. Passes the status check at the end of mtcmos_power_on() Signed-off-by: Weiyi Lu <weiyi.lu(a)mediatek.com> Change-Id: Ie7bff831eecfc2b4d315a577f6ff86befc483eab --- M src/soc/mediatek/common/include/soc/mtcmos.h M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/include/soc/spm.h A src/soc/mediatek/mt8192/mtcmos.c 4 files changed, 285 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/45394/1 diff --git a/src/soc/mediatek/common/include/soc/mtcmos.h b/src/soc/mediatek/common/include/soc/mtcmos.h index 6477906..d8cb9f5 100644 --- a/src/soc/mediatek/common/include/soc/mtcmos.h +++ b/src/soc/mediatek/common/include/soc/mtcmos.h @@ -6,6 +6,7 @@ void mtcmos_audio_power_on(void); void mtcmos_display_power_on(void); +void mtcmos_protect_audio_bus(void); void mtcmos_protect_display_bus(void); #endif /* __SOC_MEDIATEK_COMMON_MTCMOS_H__ */ diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 01db141..8f37c7b 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -27,6 +27,7 @@ ramstage-y += ../common/gpio.c gpio.c ramstage-y += emi.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c +ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-y += soc.c ramstage-y += ../common/timer.c ramstage-y += ../common/uart.c diff --git a/src/soc/mediatek/mt8192/include/soc/spm.h b/src/soc/mediatek/mt8192/include/soc/spm.h new file mode 100644 index 0000000..73ef798 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/spm.h @@ -0,0 +1,248 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_SPM_H +#define SOC_MEDIATEK_MT8192_SPM_H + +#include <soc/addressmap.h> +#include <types.h> + +/* SPM READ/WRITE CFG */ +#define SPM_PROJECT_CODE 0xb16 + +enum { + DISP_PWR_STA_MASK = 0x1 << 20, + DISP_SRAM_PDN_MASK = 0x1 << 8, + DISP_SRAM_ACK_MASK = 0x1 << 12, + AUDIO_PWR_STA_MASK = 0x1 << 21, + AUDIO_SRAM_PDN_MASK = 0x1 << 8, + AUDIO_SRAM_ACK_MASK = 0x1 << 12, +}; + +struct mtk_spm_regs { + u32 poweron_config_set; + u32 spm_power_on_val0; + u32 spm_power_on_val1; + u32 spm_clk_con; + u32 spm_clk_settle; + u32 spm_ap_standby_con; + u32 pcm_con0; + u32 pcm_con1; + u32 spm_power_on_val2; + u32 spm_power_on_val3; + u32 pcm_reg_data_ini; + u32 pcm_pwr_io_en; + u32 pcm_timer_val; + u32 pcm_wdt_val; + u32 spm_src6_mask; + u32 reserved1[1]; + u32 spm_sw_rst_con; /* 0x0040 */ + u32 spm_sw_rst_con_set; + u32 spm_sw_rst_con_clr; + u32 vs1_psr_mask_b; + u32 vs2_psr_mask_b; + u32 reserved2[12]; + u32 md32_clk_con; /* 0x0084 */ + u32 spm_sram_rsv_con; + u32 spm_swint; + u32 spm_swint_set; + u32 spm_swint_clr; + u32 spm_scp_mailbox; + u32 scp_spm_mailbox; + u32 spm_twam_con; + u32 spm_twam_window_len; + u32 spm_twam_idle_sel; + u32 spm_scp_irq; + u32 spm_cpu_wakeup_event; + u32 spm_irq_mask; + u32 spm_src_req; + u32 spm_src_mask; + u32 spm_src2_mask; + u32 spm_src3_mask; + u32 spm_src4_mask; + u32 spm_src5_mask; + u32 spm_wakeup_event_mask; + u32 spm_wakeup_event_ext_mask; + u32 spm_twam_event_clear; + u32 scp_clk_con; + u32 pcm_debug_con; + u32 ahb_bus_con; + u32 ddr_en_dbc_con0; + u32 ddr_en_dbc_con1; + u32 spm_resource_ack_con0; + u32 spm_resource_ack_con1; + u32 spm_resource_ack_con2; + u32 spm_resource_ack_con3; + u32 pcm_reg0_data; + u32 pcm_reg2_data; + u32 pcm_reg6_data; + u32 pcm_reg7_data; + u32 pcm_reg13_data; + u32 src_req_sta_0; + u32 src_req_sta_1; + u32 src_req_sta_2; + u32 pcm_timer_out; + u32 pcm_wdt_out; + u32 spm_irq_sta; + u32 src_req_sta_4; + u32 md32pcm_wakeup_sta; + u32 md32pcm_event_sta; + u32 spm_wakeup_sta; + u32 spm_wakeup_ext_sta; + u32 spm_wakeup_misc; + u32 mm_dvfs_halt; + u32 reserved3[2]; + u32 bus_protect_rdy; /* 0x0150 */ + u32 bus_protect1_rdy; + u32 bus_protect2_rdy; + u32 bus_protect3_rdy; + u32 subsys_idle_sta; + u32 pcm_sta; + u32 src_req_sta_3; + u32 pwr_status; + u32 pwr_status_2nd; + u32 cpu_pwr_status; + u32 other_pwr_status; + u32 spm_vtcxo_event_count_sta; + u32 spm_infra_event_count_sta; + u32 spm_vrf18_event_count_sta; + u32 spm_apsrc_event_count_sta; + u32 spm_ddren_event_count_sta; + u32 md32pcm_sta; + u32 md32pcm_pc; + u32 reserved4[3]; + u32 dvfsrc_event_sta; /* 0x01a4 */ + u32 bus_protect4_rdy; + u32 bus_protect5_rdy; + u32 bus_protect6_rdy; + u32 bus_protect7_rdy; + u32 bus_protect8_rdy; + u32 reserved5[5]; + u32 spm_twam_last_sta0; /* 0x01d0 */ + u32 spm_twam_last_sta1; + u32 spm_twam_last_sta2; + u32 spm_twam_last_sta3; + u32 spm_twam_curr_sta0; + u32 spm_twam_curr_sta1; + u32 spm_twam_curr_sta2; + u32 spm_twam_curr_sta3; + u32 spm_twam_timer_out; + u32 spm_cg_check_sta; + u32 spm_dvfs_sta; + u32 spm_dvfs_opp_sta; + u32 spm_mcusys_pwr_con; + u32 spm_cputop_pwr_con; + u32 spm_cpu0_pwr_con; + u32 spm_cpu1_pwr_con; + u32 spm_cpu2_pwr_con; + u32 spm_cpu3_pwr_con; + u32 spm_cpu4_pwr_con; + u32 spm_cpu5_pwr_con; + u32 spm_cpu6_pwr_con; + u32 spm_cpu7_pwr_con; + u32 reserved6[1]; + u32 armpll_clk_con; /* 0x022c */ + u32 mcusys_idle_sta; + u32 gic_wakeup_sta; + u32 cpu_spare_con; + u32 cpu_spare_con_set; + u32 cpu_spare_con_clr; + u32 armpll_clk_sel; + u32 ext_int_wakeup_req; + u32 ext_int_wakeup_req_set; + u32 ext_int_wakeup_req_clr; + u32 reserved7[3]; + u32 mp0_cpu0_irq_mask; /* 0x0260 */ + u32 mp0_cpu1_irq_mask; + u32 mp0_cpu2_irq_mask; + u32 mp0_cpu3_irq_mask; + u32 mp1_cpu0_irq_mask; + u32 mp1_cpu1_irq_mask; + u32 mp1_cpu2_irq_mask; + u32 mp1_cpu3_irq_mask; + u32 mp0_cpu0_wfi_en; + u32 mp0_cpu1_wfi_en; + u32 mp0_cpu2_wfi_en; + u32 mp0_cpu3_wfi_en; + u32 mp0_cpu4_wfi_en; + u32 mp0_cpu5_wfi_en; + u32 mp0_cpu6_wfi_en; + u32 mp0_cpu7_wfi_en; + u32 root_cputop_addr; + u32 root_core_addr; + u32 reserved8[10]; + u32 spm2sw_mailbox_0; /* 0x02d0 */ + u32 spm2sw_mailbox_1; + u32 spm2sw_mailbox_2; + u32 spm2sw_mailbox_3; + u32 sw2spm_int; + u32 sw2spm_int_set; + u32 sw2spm_int_clr; + u32 sw2spm_mailbox_0; + u32 sw2spm_mailbox_1; + u32 sw2spm_mailbox_2; + u32 sw2spm_mailbox_3; + u32 sw2spm_cfg; + u32 md1_pwr_con; + u32 conn_pwr_con; + u32 mfg0_pwr_con; + u32 mfg1_pwr_con; + u32 mfg2_pwr_con; + u32 mfg3_pwr_con; + u32 mfg4_pwr_con; + u32 mfg5_pwr_con; + u32 mfg6_pwr_con; + u32 ifr_pwr_con; + u32 ifr_sub_pwr_con; + u32 dpy_pwr_con; + u32 isp_pwr_con; + u32 isp2_pwr_con; + u32 ipe_pwr_con; + u32 vde_pwr_con; + u32 vde2_pwr_con; + u32 ven_pwr_con; + u32 ven_core1_pwr_con; + u32 mdp_pwr_con; + u32 dis_pwr_con; + u32 audio_pwr_con; + u32 adsp_pwr_con; + u32 cam_pwr_con; + u32 cam_rawa_pwr_con; + u32 cam_rawb_pwr_con; + u32 cam_rawc_pwr_con; + u32 sysram_con; + u32 sysrom_con; + u32 sspm_sram_con; + u32 scp_sram_con; + u32 dpy_shu_sram_con; + u32 ufs_sram_con; + u32 devapc_ifr_sram_con; + u32 devapc_subifr_sram_con; + u32 devapc_acp_sram_con; + u32 usb_sram_con; + u32 dummy_sram_con; + u32 md_ext_buck_iso_con; + u32 ext_buck_iso; + u32 dxcc_sram_con; + u32 msdc_pwr_con; + u32 debugtop_sram_con; + u32 dp_tx_pwr_con; + u32 dpmaif_sram_con; + u32 dpy_shu2_sram_con; + u32 dramc_mcu2_sram_con; + u32 dramc_mcu_sram_con; + u32 mcupm_pwr_con; + u32 dpy2_pwr_con; + u32 peri_pwr_con; +}; + +check_member(mtk_spm_regs, md32_clk_con, 0x0084); +check_member(mtk_spm_regs, bus_protect_rdy, 0x0150); +check_member(mtk_spm_regs, dvfsrc_event_sta, 0x01a4); +check_member(mtk_spm_regs, spm_twam_last_sta0, 0x01d0); +check_member(mtk_spm_regs, mp0_cpu0_irq_mask, 0x0260); +check_member(mtk_spm_regs, spm2sw_mailbox_0, 0x02d0); +check_member(mtk_spm_regs, peri_pwr_con, 0x03c8); + +static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE; + +#endif /* SOC_MEDIATEK_MT8192_SPM_H */ diff --git a/src/soc/mediatek/mt8192/mtcmos.c b/src/soc/mediatek/mt8192/mtcmos.c new file mode 100644 index 0000000..5a3b1fb --- /dev/null +++ b/src/soc/mediatek/mt8192/mtcmos.c @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <soc/infracfg.h> +#include <soc/mtcmos.h> + +enum { + DISP_PROT_STEP1_0_MASK = 0x05015405, + DISP_PROT_STEP1_1_MASK = 0x00001100, + DISP_PROT_STEP2_0_MASK = 0x00800040, + DISP_PROT_STEP2_1_MASK = 0x0a02800a, + DISP_PROT_STEP2_2_MASK = 0x00002200, + + AUDIO_PROT_STEP1_0_MASK = 0x00000010, +}; + +void mtcmos_protect_display_bus(void) +{ + write32(&mt8192_infracfg->infra_topaxi_protecten_clr, + DISP_PROT_STEP2_0_MASK); + write32(&mt8192_infracfg->infra_topaxi_protecten_mm_clr, + DISP_PROT_STEP2_1_MASK); + write32(&mt8192_infracfg->infra_topaxi_protecten_mm_clr_2, + DISP_PROT_STEP2_2_MASK); + write32(&mt8192_infracfg->infra_topaxi_protecten_mm_clr, + DISP_PROT_STEP1_0_MASK); + write32(&mt8192_infracfg->infra_topaxi_protecten_mm_clr_2, + DISP_PROT_STEP1_1_MASK); +} + +void mtcmos_protect_audio_bus(void) +{ + write32(&mt8192_infracfg->infra_topaxi_protecten_clr_2, + AUDIO_PROT_STEP1_0_MASK); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/45394 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7bff831eecfc2b4d315a577f6ff86befc483eab Gerrit-Change-Number: 45394 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Weiyi Lu <weiyi.lu(a)mediatek.com> Gerrit-MessageType: newchange

5 10

Change in coreboot[master]: ec/google/chromeec: Add dptc interface support
by chris wang (Code Review) 17 Sep '20

17 Sep '20

Hello Chris Wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44265 to review the following change. Change subject: ec/google/chromeec: Add dptc interface support ...................................................................... ec/google/chromeec: Add dptc interface support add the dptc interface support when system in tablet mode BUG=b:157943445 BRANCH=none TEST=Build. check the setting changed. Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: I2be7942132cea474237f531021ad4fd9856b5050 --- M src/ec/google/chromeec/acpi/ec.asl M src/mainboard/google/zork/dsdt.asl M src/soc/amd/picasso/acpi/soc.asl 3 files changed, 10 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/44265/1 diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index f8d4bdf..4038a9a 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -10,7 +10,9 @@ #ifdef DPTF_ENABLE_CHARGER External (\_SB.DPTF.TCHG, DeviceObj) #endif - +#ifdef DPTC_ENABLE +External(\_SB.DPTC, MethodObj) +#endif Device (EC0) { @@ -380,6 +382,9 @@ #ifdef EC_ENABLE_TBMC_DEVICE Notify (TBMC, 0x80) #endif +#ifdef DPTC_ENABLE + \_SB.DPTC() +#endif } /* diff --git a/src/mainboard/google/zork/dsdt.asl b/src/mainboard/google/zork/dsdt.asl index 2dc456d..b3e5f1b 100644 --- a/src/mainboard/google/zork/dsdt.asl +++ b/src/mainboard/google/zork/dsdt.asl @@ -34,9 +34,9 @@ Scope(\_SB) { /* Start \_SB scope */ /* global utility methods expected within the \_SB scope */ #include <arch/x86/acpi/globutil.asl> - +#ifdef DPTC_ENABLE #include <variant/acpi/dptc.asl> - +#endif /* Describe the SOC */ #include <soc.asl> diff --git a/src/soc/amd/picasso/acpi/soc.asl b/src/soc/amd/picasso/acpi/soc.asl index 909b985..a0a05fa 100644 --- a/src/soc/amd/picasso/acpi/soc.asl +++ b/src/soc/amd/picasso/acpi/soc.asl @@ -17,7 +17,9 @@ /* Describe the devices in the Southbridge */ #include "sb_fch.asl" +#ifdef DPTC_ENABLE #include "dptc.asl" +#endif /* Add GPIO library */ #include <soc/amd/common/acpi/gpio_bank_lib.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/44265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2be7942132cea474237f531021ad4fd9856b5050 Gerrit-Change-Number: 44265 Gerrit-PatchSet: 1 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

4 14

Change in coreboot[master]: soc/intel/common/block/sgx: make PRMRR size setting depend on SGX
by Michael Niewöhner (Code Review) 17 Sep '20

17 Sep '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45412 ) Change subject: soc/intel/common/block/sgx: make PRMRR size setting depend on SGX ...................................................................... Patch Set 3: > Patch Set 2: Code-Review+1 > > Please also update get_prmrr_size() to bail out early if > SGX is disabled (i.e. change the check `!..._BLOCK_SGX` > to `!..._BLOCK_SGX_ENABLE`). done -- To view, visit https://review.coreboot.org/c/coreboot/+/45412 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I551942fd9cb8e7123d00dbd752abffe24788148c Gerrit-Change-Number: 45412 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 17 Sep 2020 07:41:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel: cnl,icl,elh,jsl,tgl: enable C6DRAM
by Michael Niewöhner (Code Review) 17 Sep '20

17 Sep '20

Hello Felix Singer, build bot (Jenkins), Lijian Zhao, John Su, Anil Kumar K, David Wu, Patrick Georgi, Maulik V Vaghela, Matt DeVillier, Ravishankar Sarawadi, Alex Levin, Paul Menzel, Andrey Petrov, Kyösti Mälkki, Aaron Durbin, Patrick Rudolph, Nathaniel L Desimone, Nico Huber, Caveh Jalali, Christian Walter, Andrey Petrov, Edward O'Callaghan, Tim Chen, EricR Lai, Jonas Löffelholz, Shaunak Saha, Furquan Shaikh, Wonkyu Kim, Jeremy Soller, Thomas Heijligen, Subrata Banik, Aamir Bohra, Paul Fagerburg, Andrew McRae, Elyes HAOUAS, Tim Wawrzynczak, Nick Vaccaro, Thejaswani Putta, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45417 to look at the new patch set (#5). Change subject: soc/intel: cnl,icl,elh,jsl,tgl: enable C6DRAM ...................................................................... soc/intel: cnl,icl,elh,jsl,tgl: enable C6DRAM C6DRAM is not board design specific, so remove it from devicetree config. Instead, enable it on supported platforms. From Intel doc# 615211-005: The C6DRAM feature saves the processor internal state at Package C6 and deeper to DRAM instead of on-die SRAM. When the processor state has been saved to DRAM, the dedicated save/restore SRAM modules are power gated, enabling idle power savings. This power gating feature - to my knowlege - doesn't depend on board design, thus shouldn't cause any issues. Hopefully. Boards that need testing / have been tested: [] google/dedede [] google/deltaur [] google/drallion [] google/hatch [] google/sarien [] google/volteer [] intel/cannonlake_rvp [] intel/coffeelake_rvp [] intel/jasperlake_rvp [] intel/tglrvp [] prodrive/hermes [] purism/librem_whl [x] system76/lemp9 Change-Id: I556dba59bc06c9101bdfdfd6aee00610aac516e3 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/romstage/fsp_params.c M src/soc/intel/elkhartlake/chip.h M src/soc/intel/icelake/chip.h M src/soc/intel/icelake/romstage/fsp_params.c M src/soc/intel/jasperlake/chip.h M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params.c 8 files changed, 3 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/45417/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/45417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I556dba59bc06c9101bdfdfd6aee00610aac516e3 Gerrit-Change-Number: 45417 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Andrew McRae <amcrae(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jonas Löffelholz <jonas.loeffelholz(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/common/block/sgx: make PRMRR size setting depend on SGX
by Michael Niewöhner (Code Review) 17 Sep '20

17 Sep '20

Hello build bot (Jenkins), Nico Huber, Patrick Rudolph, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45412 to look at the new patch set (#3). Change subject: soc/intel/common/block/sgx: make PRMRR size setting depend on SGX ...................................................................... soc/intel/common/block/sgx: make PRMRR size setting depend on SGX PRMRR size shall only be set when SGX is enabled. Make PRMRR depend on SGX enablement in Kconfig. Change-Id: I551942fd9cb8e7123d00dbd752abffe24788148c Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/sgx/Kconfig 2 files changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/45412/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/45412 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I551942fd9cb8e7123d00dbd752abffe24788148c Gerrit-Change-Number: 45412 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

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coreboot-gerrit September 2020