coreboot-gerrit September 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: drivers/intel/mipi_camera: Add support for dynamic SSDT generation
by Paul Fagerburg (Code Review) 17 Sep '20

17 Sep '20

Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45172 ) Change subject: drivers/intel/mipi_camera: Add support for dynamic SSDT generation ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/c/coreboot/+/45172/8/src/drivers/intel/mipi_cam… File src/drivers/intel/mipi_camera/camera_sku.c: https://review.coreboot.org/c/coreboot/+/45172/8/src/drivers/intel/mipi_cam… PS8, Line 36: /* By default device will be set to enabled in alloc_dev. So calling dev_set_enabled : is not making call to chip_ops->enable_dev as device is already enabled */ : dev_set_enabled(sensor, 0); : dev_set_enabled(sensor, 1); : } This is a little confusing. You say that it's already enabled, and then you disable and re-enable it without explaining why you have to do that. Maybe reword the comment to explain why you have to disable it first, something like this? "Disable and re-enable the device so that chip_ops->enable_dev will always get called." -- To view, visit https://review.coreboot.org/c/coreboot/+/45172 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a5aa6c313c026871e55bc6d067b44de4c1f1afe Gerrit-Change-Number: 45172 Gerrit-PatchSet: 8 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Andy Yeh <andy.yeh(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Chiasheng Lee <chiasheng.lee(a)intel.com> Gerrit-Reviewer: Jett Rink <jettrink(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: ShawnX Tu <shawnx.tu(a)intel.com> Gerrit-Reviewer: Tomasz Figa <tfiga(a)google.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-CC: Henry Sun <henrysun(a)google.com> Gerrit-CC: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 17 Sep 2020 17:52:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: src: Remove redundant <pnp_type.h>
by HAOUAS Elyes (Code Review) 17 Sep '20

17 Sep '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45403 ) Change subject: src: Remove redundant <pnp_type.h> ...................................................................... src: Remove redundant <pnp_type.h> When <device/pnp.h> is needed, supposed to provide <device/pnp_type.h>. Change-Id: I0e479e2abdb6cfb8633840db2222ce5397fe7d55 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/include/device/pnp.h M src/include/device/pnp_ops.h M src/superio/nuvoton/nct5104d/early_init.c 3 files changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/45403/1 diff --git a/src/include/device/pnp.h b/src/include/device/pnp.h index bbd0498..cf809d0 100644 --- a/src/include/device/pnp.h +++ b/src/include/device/pnp.h @@ -3,7 +3,7 @@ #include <stdint.h> #include <device/device.h> -/* When <device/pnp.h> is needed, it supposed to provide <device/pnp_def.h> */ +/* When <device/pnp.h> is needed, it supposed to provide <device/pnp_{def,type}.h> */ #include <device/pnp_def.h> #include <device/pnp_type.h> #include <arch/io.h> diff --git a/src/include/device/pnp_ops.h b/src/include/device/pnp_ops.h index 0d63f1b..15acf36 100644 --- a/src/include/device/pnp_ops.h +++ b/src/include/device/pnp_ops.h @@ -6,7 +6,6 @@ #include <stdint.h> #include <arch/io.h> #include <device/pnp.h> -#include <device/pnp_type.h> #if ENV_PNP_SIMPLE_DEVICE diff --git a/src/superio/nuvoton/nct5104d/early_init.c b/src/superio/nuvoton/nct5104d/early_init.c index 5ed4c5c..c5e9388 100644 --- a/src/superio/nuvoton/nct5104d/early_init.c +++ b/src/superio/nuvoton/nct5104d/early_init.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <arch/io.h> -#include <device/pnp_type.h> #include <device/pnp.h> #include <stdint.h> #include "nct5104d.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/45403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e479e2abdb6cfb8633840db2222ce5397fe7d55 Gerrit-Change-Number: 45403 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: soc/amd/picasso: Cleanup legacy UART config
by Felix Held (Code Review) 17 Sep '20

17 Sep '20

Hello Martin Roth, Rob Barnes, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/40322 to review the following change. Change subject: soc/amd/picasso: Cleanup legacy UART config ...................................................................... soc/amd/picasso: Cleanup legacy UART config Cleaned up configuration of the legacy UART. Added Kconfig options for the mapping between UART and legacy I/O decode. TEST=Manual, boot trembyle, verify UART configured correctly in log. serial8250: ttyS3 at I/O 0x2e8 (IRQ = 3, base_baud = 115200) is a 16550A $ io_write8 0x2e8 97 -> a is output on console BUG=b:143283592 Signed-off-by: Rob Barnes <robbarnes(a)google.com> Change-Id: Id08ff6428d4019303ebb6e44e13aba480cf1fde2 Reviewed-on: https://chromium-review.googlesource.com/2037891 Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: Martin Roth <martinroth(a)google.com> --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/picasso/southbridge.c M src/soc/amd/picasso/uart.c 4 files changed, 39 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/40322/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index d9211b4..8279fd8 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -157,6 +157,7 @@ config PICASSO_UART_LEGACY bool "Decode legacy I/O range" + default n depends on PICASSO_UART help Assign I/O 3F8, 2F8, etc. to a Picasso UART. Only a single UART may @@ -164,6 +165,19 @@ console. A UART accessed with I/O does not allow all the features of MMIO. The MMIO decode is still present when this option is used. +config PICASSO_UART_LEGACY_RANGE + int "Console uart legacy I/O range" + depends on PICASSO_UART_LEGACY + range 0 3 + default 0 + help + Assign legacy I/O range to the Picasso console UART. + Possible I/O ranges: + 0: 2e8 + 1: 2f8 + 2: 3e8 + 3: 3f8 + config CONSOLE_UART_BASE_ADDRESS depends on CONSOLE_SERIAL && PICASSO_UART hex diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index a134245..3c13711 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -226,10 +226,8 @@ #define FCH_AOAC_STAT0 BIT(6) #define FCH_AOAC_STAT1 BIT(7) -#define FCH_UART_LEGACY_DECODE 0xfedc0020 -#define FCH_LEGACY_3F8_SH 3 -#define FCH_LEGACY_2F8_SH 1 -#define FCH_LEGACY_3E8_SH 2 +#define FCH_LEGACY_UART_DECODE 0xfedc0020 +#define FCH_LEGACY_UART_WHICH_SHIFT 8 #define PM1_LIMIT 16 #define GPE0_LIMIT 28 @@ -322,6 +320,7 @@ void fch_pre_init(void); void fch_early_init(void); void set_uart_config(int idx); +void set_uart_legacy_config(int uart_idx, int range_idx); /* Initialize all the i2c buses that are marked with early init. */ void i2c_soc_early_init(void); diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 6bedab0..fa3a71c 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -276,6 +276,9 @@ sb_reset_i2c_slaves(); if (CONFIG(PICASSO_UART)) set_uart_config(CONFIG_UART_FOR_CONSOLE); + if (CONFIG(PICASSO_UART_LEGACY)) + set_uart_legacy_config(CONFIG_UART_FOR_CONSOLE, + CONFIG_PICASSO_UART_LEGACY_RANGE); } static void print_num_status_bits(int num_bits, uint32_t status, diff --git a/src/soc/amd/picasso/uart.c b/src/soc/amd/picasso/uart.c index 14a43c1..38e0865 100644 --- a/src/soc/amd/picasso/uart.c +++ b/src/soc/amd/picasso/uart.c @@ -39,10 +39,28 @@ return uart_info[idx].base; } + +void set_uart_legacy_config(int uart_idx, int range_idx) +{ + uint16_t uart_leg; + uint8_t uart_leg_which_offset; + + if (uart_idx < 0 || uart_idx > 3 || range_idx < 0 || range_idx > 3) + return; + + uart_leg = read16((void *)FCH_LEGACY_UART_DECODE); + /* Map uart_idx to io range_idx */ + uart_leg_which_offset = range_idx * 2 + FCH_LEGACY_UART_WHICH_SHIFT; + uart_leg &= ~(0x3 << uart_leg_which_offset); + uart_leg |= uart_idx << uart_leg_which_offset; + /* Enable io range */ + uart_leg |= 1 << range_idx; + write16((void *)FCH_LEGACY_UART_DECODE, uart_leg); +} + void set_uart_config(int idx) { uint32_t uart_ctrl; - uint16_t uart_leg; if (idx < 0 || idx > ARRAY_SIZE(uart_info)) return; @@ -55,20 +73,6 @@ sm_pci_write32(SMB_UART_CONFIG, uart_ctrl); } - if (CONFIG(PICASSO_UART_LEGACY) && idx != 3) { - /* Force 3F8 if idx=0, 2F8 if idx=1, 3E8 if idx=2 */ - - /* TODO: make clearer once PPR is updated */ - uart_leg = (idx << 8) | (idx << 10) | (idx << 12) | (idx << 14); - if (idx == 0) - uart_leg |= 1 << FCH_LEGACY_3F8_SH; - else if (idx == 1) - uart_leg |= 1 << FCH_LEGACY_2F8_SH; - else if (idx == 2) - uart_leg |= 1 << FCH_LEGACY_3E8_SH; - - write16((void *)FCH_UART_LEGACY_DECODE, uart_leg); - } } unsigned int uart_platform_refclk(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/40322 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id08ff6428d4019303ebb6e44e13aba480cf1fde2 Gerrit-Change-Number: 40322 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newchange

8 32

Change in coreboot[master]: mb/google/volteer/variants/eldrid:: Configure USB4 probe
by Nick Chen (Code Review) 17 Sep '20

17 Sep '20

Nick Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45466 ) Change subject: mb/google/volteer/variants/eldrid:: Configure USB4 probe ...................................................................... mb/google/volteer/variants/eldrid:: Configure USB4 probe Disable USB4 probe on overridetree.cb for power off smoothly BUG=b:167983038 Signed-off-by: nick_xr_chen <nick_xr_chen(a)wistron.corp-partner.google.com> Change-Id: I61ef5444de22b9e87a6d494dade15e39f9acaa61 --- M src/mainboard/google/volteer/variants/eldrid/overridetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/45466/1 diff --git a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb index 171e397..395534a 100644 --- a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb +++ b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb @@ -48,6 +48,8 @@ }" device domain 0 on device pci 04.0 off end + device pci 07.0 on end + device pci 07.1 on end device pci 15.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" -- To view, visit https://review.coreboot.org/c/coreboot/+/45466 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61ef5444de22b9e87a6d494dade15e39f9acaa61 Gerrit-Change-Number: 45466 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Chen <nick_xr_chen(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

1 3

Change in coreboot[master]: src: Add missing <device/pnp_def.h>
by HAOUAS Elyes (Code Review) 17 Sep '20

17 Sep '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45316 ) Change subject: src: Add missing <device/pnp_def.h> ...................................................................... src: Add missing <device/pnp_def.h> Also remove unused "include <device/pnp_def.h>" in "device/pnp.h". Change-Id: Ib9903ae456c32db4ba346020659c17c27a939e89 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/device/pnp_device.c M src/ec/hp/kbc1126/early_init.c M src/ec/kontron/it8516e/ec.c M src/include/device/pnp.h M src/mainboard/facebook/monolith/com_init.c M src/mainboard/lenovo/t400/dock.c M src/superio/fintek/common/early_serial.c M src/superio/fintek/f71808a/f71808a_hwm.c M src/superio/fintek/f71863fg/superio.c M src/superio/fintek/f71869ad/f71869ad_hwm.c M src/superio/fintek/f81866d/f81866d_hwm.c M src/superio/fintek/f81866d/f81866d_uart.c M src/superio/ite/common/early_serial.c M src/superio/ite/it8613e/superio.c M src/superio/ite/it8623e/superio.c M src/superio/ite/it8718f/superio.c M src/superio/ite/it8720f/superio.c M src/superio/ite/it8728f/superio.c M src/superio/ite/it8772f/superio.c M src/superio/ite/it8783ef/superio.c M src/superio/ite/it8786e/superio.c M src/superio/nuvoton/common/early_serial.c M src/superio/nuvoton/npcd378/superio.c M src/superio/serverengines/pilot/early_serial.c M src/superio/smsc/kbc1100/superio.c M src/superio/smsc/lpc47m10x/early_serial.c M src/superio/smsc/lpc47m15x/early_serial.c M src/superio/smsc/lpc47n217/superio.c M src/superio/smsc/lpc47n227/superio.c M src/superio/smsc/sch5545/superio.c M src/superio/winbond/common/early_init.c M src/superio/winbond/w83627ehg/superio.c M src/superio/winbond/w83627hf/superio.c 33 files changed, 38 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/45316/1 diff --git a/src/device/pnp_device.c b/src/device/pnp_device.c index cd7adf3..1f5a8ee 100644 --- a/src/device/pnp_device.c +++ b/src/device/pnp_device.c @@ -5,6 +5,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <device/pnp_def.h> /* PNP config mode wrappers */ diff --git a/src/ec/hp/kbc1126/early_init.c b/src/ec/hp/kbc1126/early_init.c index 415ebab..45a7c62 100644 --- a/src/ec/hp/kbc1126/early_init.c +++ b/src/ec/hp/kbc1126/early_init.c @@ -3,6 +3,8 @@ #include <arch/io.h> #include <device/pnp_ops.h> #include <device/pnp.h> +#include <device/pnp_def.h> + #include "ec.h" void kbc1126_enter_conf(void) diff --git a/src/ec/kontron/it8516e/ec.c b/src/ec/kontron/it8516e/ec.c index 9af670a..3ace04a 100644 --- a/src/ec/kontron/it8516e/ec.c +++ b/src/ec/kontron/it8516e/ec.c @@ -3,6 +3,7 @@ #include <console/console.h> #include <device/device.h> #include <device/pnp.h> +#include <device/pnp_def.h> #include <ec/acpi/ec.h> #include <option.h> diff --git a/src/include/device/pnp.h b/src/include/device/pnp.h index 800bcc0..ffc5036 100644 --- a/src/include/device/pnp.h +++ b/src/include/device/pnp.h @@ -3,7 +3,6 @@ #include <stdint.h> #include <device/device.h> -#include <device/pnp_def.h> #include <device/pnp_type.h> #include <arch/io.h> diff --git a/src/mainboard/facebook/monolith/com_init.c b/src/mainboard/facebook/monolith/com_init.c index 98a0232..f0c2157 100644 --- a/src/mainboard/facebook/monolith/com_init.c +++ b/src/mainboard/facebook/monolith/com_init.c @@ -3,6 +3,8 @@ #include <bootblock_common.h> #include <device/pnp_ops.h> #include <device/pnp.h> +#include <device/pnp_def.h> + #include "onboard.h" #define SERIAL_DEV1 PNP_DEV(ITE8528_CMD_PORT, 1) /* ITE8528 UART1 */ diff --git a/src/mainboard/lenovo/t400/dock.c b/src/mainboard/lenovo/t400/dock.c index b8163e71..043f3ac 100644 --- a/src/mainboard/lenovo/t400/dock.c +++ b/src/mainboard/lenovo/t400/dock.c @@ -6,6 +6,7 @@ #include <device/pnp_ops.h> #include <device/device.h> #include <device/pnp.h> +#include <device/pnp_def.h> #include <delay.h> #include "dock.h" #include <superio/nsc/pc87382/pc87382.h> diff --git a/src/superio/fintek/common/early_serial.c b/src/superio/fintek/common/early_serial.c index 79af111..843e209 100644 --- a/src/superio/fintek/common/early_serial.c +++ b/src/superio/fintek/common/early_serial.c @@ -22,6 +22,7 @@ #include <arch/io.h> #include <device/pnp_ops.h> #include <device/pnp.h> +#include <device/pnp_def.h> #include <stdint.h> #include "fintek.h" diff --git a/src/superio/fintek/f71808a/f71808a_hwm.c b/src/superio/fintek/f71808a/f71808a_hwm.c index 340bc30..992a870 100644 --- a/src/superio/fintek/f71808a/f71808a_hwm.c +++ b/src/superio/fintek/f71808a/f71808a_hwm.c @@ -3,6 +3,7 @@ #include <console/console.h> #include <device/device.h> #include <device/pnp.h> +#include <device/pnp_def.h> #include "fintek_internal.h" #include "chip.h" diff --git a/src/superio/fintek/f71863fg/superio.c b/src/superio/fintek/f71863fg/superio.c index c4e8dc9..11e1600 100644 --- a/src/superio/fintek/f71863fg/superio.c +++ b/src/superio/fintek/f71863fg/superio.c @@ -2,6 +2,7 @@ #include <device/device.h> #include <device/pnp.h> +#include <device/pnp_def.h> #include <superio/conf_mode.h> #include <pc80/keyboard.h> diff --git a/src/superio/fintek/f71869ad/f71869ad_hwm.c b/src/superio/fintek/f71869ad/f71869ad_hwm.c index 6333ae1..408e0e1 100644 --- a/src/superio/fintek/f71869ad/f71869ad_hwm.c +++ b/src/superio/fintek/f71869ad/f71869ad_hwm.c @@ -3,6 +3,8 @@ #include <console/console.h> #include <device/device.h> #include <device/pnp.h> +#include <device/pnp_def.h> + #include "chip.h" #include "fintek_internal.h" diff --git a/src/superio/fintek/f81866d/f81866d_hwm.c b/src/superio/fintek/f81866d/f81866d_hwm.c index a7ed96b..41f9d47 100644 --- a/src/superio/fintek/f81866d/f81866d_hwm.c +++ b/src/superio/fintek/f81866d/f81866d_hwm.c @@ -7,6 +7,8 @@ #include <console/console.h> #include <device/device.h> #include <device/pnp.h> +#include <device/pnp_def.h> + #include "fintek_internal.h" #include "chip.h" diff --git a/src/superio/fintek/f81866d/f81866d_uart.c b/src/superio/fintek/f81866d/f81866d_uart.c index 7d98a7f..23dda77 100644 --- a/src/superio/fintek/f81866d/f81866d_uart.c +++ b/src/superio/fintek/f81866d/f81866d_uart.c @@ -3,6 +3,8 @@ #include <console/console.h> #include <device/device.h> #include <device/pnp.h> +#include <device/pnp_def.h> + #include "fintek_internal.h" #include "f81866d.h" diff --git a/src/superio/ite/common/early_serial.c b/src/superio/ite/common/early_serial.c index 6b05a38..b26680b 100644 --- a/src/superio/ite/common/early_serial.c +++ b/src/superio/ite/common/early_serial.c @@ -3,6 +3,7 @@ #include <arch/io.h> #include <device/pnp_ops.h> #include <device/pnp.h> +#include <device/pnp_def.h> #include <stdint.h> #include "ite.h" diff --git a/src/superio/ite/it8613e/superio.c b/src/superio/ite/it8613e/superio.c index 4d12457..83b1858 100644 --- a/src/superio/ite/it8613e/superio.c +++ b/src/superio/ite/it8613e/superio.c @@ -2,6 +2,7 @@ #include <device/device.h> #include <device/pnp.h> +#include <device/pnp_def.h> #include <pc80/keyboard.h> #include <superio/conf_mode.h> #include <superio/ite/common/env_ctrl.h> diff --git a/src/superio/ite/it8623e/superio.c b/src/superio/ite/it8623e/superio.c index ca3455a..b7a4b49 100644 --- a/src/superio/ite/it8623e/superio.c +++ b/src/superio/ite/it8623e/superio.c @@ -2,6 +2,7 @@ #include <device/device.h> #include <device/pnp.h> +#include <device/pnp_def.h> #include <pc80/keyboard.h> #include <superio/conf_mode.h> #include <superio/ite/common/env_ctrl.h> diff --git a/src/superio/ite/it8718f/superio.c b/src/superio/ite/it8718f/superio.c index aab554f..47ecb27 100644 --- a/src/superio/ite/it8718f/superio.c +++ b/src/superio/ite/it8718f/superio.c @@ -2,6 +2,7 @@ #include <device/device.h> #include <device/pnp.h> +#include <device/pnp_def.h> #include <pc80/keyboard.h> #include <superio/ite/common/env_ctrl.h> #include <superio/conf_mode.h> diff --git a/src/superio/ite/it8720f/superio.c b/src/superio/ite/it8720f/superio.c index c395953..dd399f8 100644 --- a/src/superio/ite/it8720f/superio.c +++ b/src/superio/ite/it8720f/superio.c @@ -2,6 +2,7 @@ #include <device/device.h> #include <device/pnp.h> +#include <device/pnp_def.h> #include <pc80/keyboard.h> #include <option.h> #include <superio/ite/common/env_ctrl.h> diff --git a/src/superio/ite/it8728f/superio.c b/src/superio/ite/it8728f/superio.c index 22e6ecb..7943f13 100644 --- a/src/superio/ite/it8728f/superio.c +++ b/src/superio/ite/it8728f/superio.c @@ -2,6 +2,7 @@ #include <device/device.h> #include <device/pnp.h> +#include <device/pnp_def.h> #include <superio/conf_mode.h> #include <pc80/keyboard.h> #include <superio/ite/common/env_ctrl.h> diff --git a/src/superio/ite/it8772f/superio.c b/src/superio/ite/it8772f/superio.c index 6672cdc..dc323ae 100644 --- a/src/superio/ite/it8772f/superio.c +++ b/src/superio/ite/it8772f/superio.c @@ -2,6 +2,7 @@ #include <device/device.h> #include <device/pnp.h> +#include <device/pnp_def.h> #include <console/console.h> #include <pc80/keyboard.h> #include <arch/io.h> diff --git a/src/superio/ite/it8783ef/superio.c b/src/superio/ite/it8783ef/superio.c index feb373f..36651a1 100644 --- a/src/superio/ite/it8783ef/superio.c +++ b/src/superio/ite/it8783ef/superio.c @@ -2,6 +2,7 @@ #include <device/device.h> #include <device/pnp.h> +#include <device/pnp_def.h> #include <pc80/keyboard.h> #include <superio/conf_mode.h> #include <superio/ite/common/env_ctrl.h> diff --git a/src/superio/ite/it8786e/superio.c b/src/superio/ite/it8786e/superio.c index 55fff91..df4b3e7 100644 --- a/src/superio/ite/it8786e/superio.c +++ b/src/superio/ite/it8786e/superio.c @@ -2,6 +2,7 @@ #include <device/device.h> #include <device/pnp.h> +#include <device/pnp_def.h> #include <pc80/keyboard.h> #include <superio/conf_mode.h> #include <superio/ite/common/env_ctrl.h> diff --git a/src/superio/nuvoton/common/early_serial.c b/src/superio/nuvoton/common/early_serial.c index 22d882e..b87feea 100644 --- a/src/superio/nuvoton/common/early_serial.c +++ b/src/superio/nuvoton/common/early_serial.c @@ -22,6 +22,7 @@ #include <arch/io.h> #include <device/pnp_ops.h> #include <device/pnp.h> +#include <device/pnp_def.h> #include <stdint.h> #include "nuvoton.h" diff --git a/src/superio/nuvoton/npcd378/superio.c b/src/superio/nuvoton/npcd378/superio.c index b7f98af..949e278 100644 --- a/src/superio/nuvoton/npcd378/superio.c +++ b/src/superio/nuvoton/npcd378/superio.c @@ -4,6 +4,7 @@ #include <console/console.h> #include <device/device.h> #include <device/pnp.h> +#include <device/pnp_def.h> #include <option.h> #include <pc80/keyboard.h> #include <superio/conf_mode.h> diff --git a/src/superio/serverengines/pilot/early_serial.c b/src/superio/serverengines/pilot/early_serial.c index e415413..11d6631 100644 --- a/src/superio/serverengines/pilot/early_serial.c +++ b/src/superio/serverengines/pilot/early_serial.c @@ -5,6 +5,8 @@ #include <arch/io.h> #include <device/pnp_ops.h> #include <device/pnp.h> +#include <device/pnp_def.h> + #include "pilot.h" /* Pilot uses 0x5A/0xA5 pattern to activate deactivate config access. */ diff --git a/src/superio/smsc/kbc1100/superio.c b/src/superio/smsc/kbc1100/superio.c index 91457a1..1743624 100644 --- a/src/superio/smsc/kbc1100/superio.c +++ b/src/superio/smsc/kbc1100/superio.c @@ -4,6 +4,7 @@ #include <device/device.h> #include <device/pnp.h> +#include <device/pnp_def.h> #include <superio/conf_mode.h> #include <pc80/keyboard.h> diff --git a/src/superio/smsc/lpc47m10x/early_serial.c b/src/superio/smsc/lpc47m10x/early_serial.c index 38a13f5..7a8e18f 100644 --- a/src/superio/smsc/lpc47m10x/early_serial.c +++ b/src/superio/smsc/lpc47m10x/early_serial.c @@ -3,6 +3,7 @@ #include <arch/io.h> #include <device/pnp_ops.h> #include <device/pnp.h> +#include <device/pnp_def.h> #include <stdint.h> #include "lpc47m10x.h" diff --git a/src/superio/smsc/lpc47m15x/early_serial.c b/src/superio/smsc/lpc47m15x/early_serial.c index 5921a48..6c78edc 100644 --- a/src/superio/smsc/lpc47m15x/early_serial.c +++ b/src/superio/smsc/lpc47m15x/early_serial.c @@ -5,6 +5,7 @@ #include <arch/io.h> #include <device/pnp_ops.h> #include <device/pnp.h> +#include <device/pnp_def.h> #include <stdint.h> #include "lpc47m15x.h" diff --git a/src/superio/smsc/lpc47n217/superio.c b/src/superio/smsc/lpc47n217/superio.c index a716d19..b721f4b 100644 --- a/src/superio/smsc/lpc47n217/superio.c +++ b/src/superio/smsc/lpc47n217/superio.c @@ -5,6 +5,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <device/pnp_def.h> #include <console/console.h> #include <assert.h> diff --git a/src/superio/smsc/lpc47n227/superio.c b/src/superio/smsc/lpc47n227/superio.c index 376fddb..90a06ff 100644 --- a/src/superio/smsc/lpc47n227/superio.c +++ b/src/superio/smsc/lpc47n227/superio.c @@ -4,6 +4,7 @@ #include <device/device.h> #include <device/pnp.h> +#include <device/pnp_def.h> #include <console/console.h> #include <assert.h> #include <pc80/keyboard.h> diff --git a/src/superio/smsc/sch5545/superio.c b/src/superio/smsc/sch5545/superio.c index b6e5308..ce8cdd2 100644 --- a/src/superio/smsc/sch5545/superio.c +++ b/src/superio/smsc/sch5545/superio.c @@ -3,6 +3,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <device/pnp_def.h> #include <superio/conf_mode.h> #include <console/console.h> #include <pc80/keyboard.h> diff --git a/src/superio/winbond/common/early_init.c b/src/superio/winbond/common/early_init.c index 4b9497e..2fa0144 100644 --- a/src/superio/winbond/common/early_init.c +++ b/src/superio/winbond/common/early_init.c @@ -22,6 +22,7 @@ #include <arch/io.h> #include <device/pnp_ops.h> #include <device/pnp.h> +#include <device/pnp_def.h> #include <stdint.h> #include "winbond.h" diff --git a/src/superio/winbond/w83627ehg/superio.c b/src/superio/winbond/w83627ehg/superio.c index 7793fa4..8edf0a2 100644 --- a/src/superio/winbond/w83627ehg/superio.c +++ b/src/superio/winbond/w83627ehg/superio.c @@ -2,6 +2,7 @@ #include <device/device.h> #include <device/pnp.h> +#include <device/pnp_def.h> #include <superio/conf_mode.h> #include <superio/hwm5_conf.h> #include <console/console.h> diff --git a/src/superio/winbond/w83627hf/superio.c b/src/superio/winbond/w83627hf/superio.c index c6d2f57..1469baf 100644 --- a/src/superio/winbond/w83627hf/superio.c +++ b/src/superio/winbond/w83627hf/superio.c @@ -2,6 +2,7 @@ #include <device/device.h> #include <device/pnp.h> +#include <device/pnp_def.h> #include <superio/conf_mode.h> #include <superio/hwm5_conf.h> #include <console/console.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/45316 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9903ae456c32db4ba346020659c17c27a939e89 Gerrit-Change-Number: 45316 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 10

Change in coreboot[master]: soc/intel/common/block/cpu: Fix boot failure
by Patrick Rudolph (Code Review) 17 Sep '20

17 Sep '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45344 ) Change subject: soc/intel/common/block/cpu: Fix boot failure ...................................................................... soc/intel/common/block/cpu: Fix boot failure This fixes CB:45043 "Guard options with if-blocks". The code no longer returns if SGX is disabled, but as the PRMRR configuration is missing it runs into die(). Tested on Prodrive Hermes: Boots again into Linux. Change-Id: I6d32ca32b1b53767b2db91305103cd532823a5ca Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/common/block/cpu/cpulib.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/45344/1 diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 5b703cf..9cf7777 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -346,6 +346,9 @@ int i; int valid_size; + if (!CONFIG(SOC_INTEL_COMMON_BLOCK_SGX)) + return 0; + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_DISABLED)) { printk(BIOS_DEBUG, "PRMRR disabled by config.\n"); return 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/45344 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d32ca32b1b53767b2db91305103cd532823a5ca Gerrit-Change-Number: 45344 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

9 24

Change in coreboot[master]: soc/intel/cannonlake: fix GPIO community numbering in ACPI
by 9elements QA (Code Review) 17 Sep '20

17 Sep '20

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45209 ) Change subject: soc/intel/cannonlake: fix GPIO community numbering in ACPI ...................................................................... Patch Set 6: Automatic boot test returned (PASS/FAIL/TOTAL): 8/1/9 "QEMU x86 q35/ich9" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/19695 "QEMU x86 q35/ich9" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/19694 "QEMU x86 i440fx/piix4" (x86_64) using payload SeaBIOS : FAIL : https://lava.9esec.io/r/19693 "QEMU x86 i440fx/piix4" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/19692 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/19691 "HP Z220 SFF Workstation" (x86_32) using payload LinuxBoot_BusyBox_kexec : SUCCESS : https://lava.9esec.io/r/19699 "HP Z220 SFF Workstation" (x86_32) using payload LinuxBoot_BusyBox_kexec : SUCCESS : https://lava.9esec.io/r/19698 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/19697 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/19696 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/45209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f13a28d3e8f427859570a4d209304ae8444efd9 Gerrit-Change-Number: 45209 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Thu, 17 Sep 2020 11:37:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common/block: Fix Klocwork issue
by Subrata Banik (Code Review) 17 Sep '20

17 Sep '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45411 ) Change subject: soc/intel/common/block: Fix Klocwork issue ...................................................................... soc/intel/common/block: Fix Klocwork issue List of changes: 1. Add NULL check for pointer ctx 2. Initialize pointer soc_config with NULL Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Change-Id: I16015b538112e0b125b4a5e145c26263c456953c --- M src/soc/intel/common/block/chip/chip.c M src/soc/intel/common/block/cse/cse_lite.c 2 files changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/45411/1 diff --git a/src/soc/intel/common/block/chip/chip.c b/src/soc/intel/common/block/chip/chip.c index 09f2c47..47bee7c 100644 --- a/src/soc/intel/common/block/chip/chip.c +++ b/src/soc/intel/common/block/chip/chip.c @@ -5,7 +5,7 @@ const struct soc_intel_common_config *chip_get_common_soc_structure(void) { - const struct soc_intel_common_config *soc_config; + const struct soc_intel_common_config *soc_config = NULL; const config_t *config; config = config_of_soc(); diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index edb08da..17e8ef6 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -169,8 +169,9 @@ /* Log CSE Firmware Status Registers to help debugging */ cse_log_status_registers(); if (CONFIG(VBOOT)) { - struct vb2_context *ctx; - ctx = vboot_get_context(); + struct vb2_context *ctx = vboot_get_context(); + if (ctx == NULL) + return; vb2api_fail(ctx, VB2_RECOVERY_INTEL_CSE_LITE_SKU, rec_sub_code); vboot_save_data(ctx); vboot_reboot(); -- To view, visit https://review.coreboot.org/c/coreboot/+/45411 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16015b538112e0b125b4a5e145c26263c456953c Gerrit-Change-Number: 45411 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

6 19

Change in coreboot[master]: soc/intel/xeon_sp/cpx: Enable ACPI Continuous Performance Control
by Jingle Hsu (Code Review) 17 Sep '20

17 Sep '20

Jingle Hsu has removed build bot (Jenkins) from this change. ( https://review.coreboot.org/c/coreboot/+/45426 ) Change subject: soc/intel/xeon_sp/cpx: Enable ACPI Continuous Performance Control ...................................................................... Removed reviewer build bot (Jenkins). -- To view, visit https://review.coreboot.org/c/coreboot/+/45426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I612598a5189375f335315933b590e1f7d24b2944 Gerrit-Change-Number: 45426 Gerrit-PatchSet: 3 Gerrit-Owner: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: deleteReviewer

1 0

Change in coreboot[master]: soc/intel/common/block/chip: Refactor chip_get_common_soc_structure()
by Subrata Banik (Code Review) 17 Sep '20

17 Sep '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45416 ) Change subject: soc/intel/common/block/chip: Refactor chip_get_common_soc_structure() ...................................................................... soc/intel/common/block/chip: Refactor chip_get_common_soc_structure() Found-by: Klocwork, Pointer soc_config is used uninitialized. Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Change-Id: I7e2aa4ef23a68a2ec2ba9d55cf890a7f81e3e278 --- M src/soc/intel/common/block/chip/chip.c 1 file changed, 1 insertion(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/45416/1 diff --git a/src/soc/intel/common/block/chip/chip.c b/src/soc/intel/common/block/chip/chip.c index 09f2c47..a9bfb17 100644 --- a/src/soc/intel/common/block/chip/chip.c +++ b/src/soc/intel/common/block/chip/chip.c @@ -5,11 +5,5 @@ const struct soc_intel_common_config *chip_get_common_soc_structure(void) { - const struct soc_intel_common_config *soc_config; - const config_t *config; - - config = config_of_soc(); - soc_config = &config->common_soc_config; - - return soc_config; + return &config_of_soc()->common_soc_config; } -- To view, visit https://review.coreboot.org/c/coreboot/+/45416 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e2aa4ef23a68a2ec2ba9d55cf890a7f81e3e278 Gerrit-Change-Number: 45416 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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