coreboot-gerrit September 2020

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Change in coreboot[master]: [WIP] mb/google/zork: add dptc support
by chris wang (Code Review) 17 Sep '20

17 Sep '20

Hello Chris Wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/43408 to review the following change. Change subject: [WIP] mb/google/zork: add dptc support ...................................................................... [WIP] mb/google/zork: add dptc support add dptc support for different factory. Profile 0 : claimshell mode Profile 1 : Tablet mode Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: Icae94103f254f8fdb84e6ee0f5404fb09fa97b2d --- M src/ec/google/chromeec/acpi/ec.asl M src/mainboard/google/zork/dsdt.asl A src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/dtpc.asl A src/mainboard/google/zork/variants/trembyle/include/variant/acpi/dptc.asl A src/soc/amd/picasso/acpi/dptc.asl M src/soc/amd/picasso/acpi/soc.asl A src/soc/amd/picasso/include/dptc.h 7 files changed, 145 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/43408/1 diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index f8d4bdf..993932a 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -10,7 +10,9 @@ #ifdef DPTF_ENABLE_CHARGER External (\_SB.DPTF.TCHG, DeviceObj) #endif - +#ifdef DPTC_ENABLE +External(\_SB.DPTC, MethodObj) +#endif Device (EC0) { @@ -358,6 +360,9 @@ { Store ("EC: MKBP", Debug) Notify (CREC, 0x80) +#ifdef DPTC_ENABLE + \_SB.DPTC(0x0) +#endif } #ifdef EC_ENABLE_PD_MCU_DEVICE @@ -377,6 +382,9 @@ #ifdef EC_ENABLE_MULTIPLE_DPTF_PROFILES \_SB.DPTF.TPET() #endif +#ifdef DPTC_ENABLE + \_SB.DPTC(0x1) +#endif #ifdef EC_ENABLE_TBMC_DEVICE Notify (TBMC, 0x80) #endif diff --git a/src/mainboard/google/zork/dsdt.asl b/src/mainboard/google/zork/dsdt.asl index d256f66..e853c25 100644 --- a/src/mainboard/google/zork/dsdt.asl +++ b/src/mainboard/google/zork/dsdt.asl @@ -41,6 +41,8 @@ /* global utility methods expected within the \_SB scope */ #include <arch/x86/acpi/globutil.asl> + #include <variant/acpi/dptc.asl> + /* Describe the SOC */ #include <soc.asl> diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/dtpc.asl b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/dtpc.asl new file mode 100644 index 0000000..b421ae3 --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/dtpc.asl @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define SUSTAINED_POWER_LIMIT_MW_0 25000 +#define SLOW_PPT_LIMIT_MW_0 30000 + +#define SUSTAINED_POWER_LIMIT_MW_1 16000 +#define SLOW_PPT_LIMIT_MW_1 20000 + diff --git a/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/dptc.asl b/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/dptc.asl new file mode 100644 index 0000000..d43a9c6 --- /dev/null +++ b/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/dptc.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/dptc.asl> diff --git a/src/soc/amd/picasso/acpi/dptc.asl b/src/soc/amd/picasso/acpi/dptc.asl new file mode 100644 index 0000000..9bd9779 --- /dev/null +++ b/src/soc/amd/picasso/acpi/dptc.asl @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + #define DPTC_CTDP 0x0 + #define DPTC_STAPM_TIME_CONSTANT 0x1 + #define DPTC_SKIN_CONTROL_SCALAR 0x2 + #define DPTC_THERMAL_CONTROL_LIMIT 0x3 + #define DPTC_PACKAGE_POWER_LIMIT 0x4 + #define DPTC_SUSTAINED_POWER_LIMIT 0x5 + #define DPTC_FAST_PPT_LIMIT 0x6 + #define DPTC_SLOW_PPT_LIMIT 0x7 + #define DPTC_SLOW_PPT_TIME_CONSTANT 0x8 + #define DPTC_PROCHOT_L 0x9 + #define DPTC_SYS_TEMP_TRACKING 0xa + #define DPTC_VRM_CURRENT_LIMIT 0xb + #define DPTC_VRM_MAXIMUM_CURRENT_LIMIT 0xc + #define DPTC_VRM_LOW_POWER_THRESHOLD 0xd + #define DPTC_VRM_SOC_CURRENT_LIMIT 0xe + #define DPTC_VRM_SOC_LOW_POWER_THRESHOLD 0xf + #define DPTC_DGPU_CONTROL 0x10 +#define DPTC_PROFILE_0 0x0 +#define DPTC_PROFILE_1 0x1 +External(\_SB.ALIB, MethodObj) +Name(DPTI, Buffer(0x07){}) +CreateWordField(DPTI, Zero, SSZE) +CreateByteField(DPTI, 0x02,MSID) +CreateDwordField(DPTI,0x03,DECI) +/* System Bus */ +Method(DPTC, 1, Serialized) +{ + Method(POF0, 0, Serialized) { + Store(0x07, SSZE) + Store(DPTC_SUSTAINED_POWER_LIMIT, MSID) + Store(SUSTAINED_POWER_LIMIT_MW_0, DECI) + ALIB(0xC, DPTI) //for PL1:Sustained power limit + Store(0x07, SSZE) + Store(DPTC_SLOW_PPT_LIMIT, MSID) + Store(SLOW_PPT_LIMIT_MW_0, DECI) + ALIB(0xC, DPTI) //for PL2:Slow PPT limit + } + Method(POF1, 0, Serialized) { + Store(0x07, SSZE) + Store(DPTC_SUSTAINED_POWER_LIMIT, MSID) + Store(SUSTAINED_POWER_LIMIT_MW_1, DECI) + ALIB(0xC, DPTI) //for PL1:Sustained power limit + Store(0x07, SSZE) + Store(DPTC_SLOW_PPT_LIMIT, MSID) + Store(SLOW_PPT_LIMIT_MW_1, DECI) + ALIB(0xC, DPTI) //for PL2:Slow PPT limit + } + Switch (ToInteger(Arg0)) + { + Case (DPTC_PROFILE_0) { + POF0() + } + Case (DPTC_PROFILE_1) { + POF1() + } + } +} diff --git a/src/soc/amd/picasso/acpi/soc.asl b/src/soc/amd/picasso/acpi/soc.asl index b3b036e..909b985 100644 --- a/src/soc/amd/picasso/acpi/soc.asl +++ b/src/soc/amd/picasso/acpi/soc.asl @@ -17,5 +17,7 @@ /* Describe the devices in the Southbridge */ #include "sb_fch.asl" +#include "dptc.asl" + /* Add GPIO library */ #include <soc/amd/common/acpi/gpio_bank_lib.asl> diff --git a/src/soc/amd/picasso/include/dptc.h b/src/soc/amd/picasso/include/dptc.h new file mode 100644 index 0000000..c4f723b --- /dev/null +++ b/src/soc/amd/picasso/include/dptc.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + #define DPTC_CTDP 0x0 + #define DPTC_STAPM_TIME_CONSTANT 0x1 + #define DPTC_SKIN_CONTROL_SCALAR 0x2 + #define DPTC_THERMAL_CONTROL_LIMIT 0x3 + #define DPTC_PACKAGE_POWER_LIMIT 0x4 + #define DPTC_SUSTAINED_POWER_LIMIT 0x5 + #define DPTC_FAST_PPT_LIMIT 0x6 + #define DPTC_SLOW_PPT_LIMIT 0x7 + #define DPTC_SLOW_PPT_TIME_CONSTANT 0x8 + #define DPTC_SYS_TEMP_TRACKING 0xA + #define DPTC_VRM_CURRENT_LIMIT 0xb + #define DPTC_VRM_MAXIMUM_CURRENT_LIMIT 0xc + #define DPTC_VRM_LOW_POWER_THRESHOLD 0xd + #define DPTC_VRM_SOC_CURRENT_LIMIT 0xe + #define DPTC_VRM_SOC_LOW_POWER_THRESHOLD 0xf + #define DPTC_DGPU_CONTROL 0x10 -- To view, visit https://review.coreboot.org/c/coreboot/+/43408 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icae94103f254f8fdb84e6ee0f5404fb09fa97b2d Gerrit-Change-Number: 43408 Gerrit-PatchSet: 1 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [RFC|NEEDTEST] soc/intel: cnl,icl,elh,jsl,tgl: enable C6DRAM
by Michael Niewöhner (Code Review) 17 Sep '20

17 Sep '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45417 ) Change subject: [RFC|NEEDTEST] soc/intel: cnl,icl,elh,jsl,tgl: enable C6DRAM ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/45417/4//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45417/4//COMMIT_MSG@19 PS4, Line 19: Hopefully > Then... Why not keep it as a Kconfig option? Not everyone wants to enable it. […] I've already suggested that. see main comments -- To view, visit https://review.coreboot.org/c/coreboot/+/45417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I556dba59bc06c9101bdfdfd6aee00610aac516e3 Gerrit-Change-Number: 45417 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Andrew McRae <amcrae(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jonas Löffelholz <jonas.loeffelholz(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 17 Sep 2020 07:17:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: [RFC|NEEDTEST] soc/intel: cnl,icl,elh,jsl,tgl: enable C6DRAM
by Michael Niewöhner (Code Review) 17 Sep '20

17 Sep '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45417 ) Change subject: [RFC|NEEDTEST] soc/intel: cnl,icl,elh,jsl,tgl: enable C6DRAM ...................................................................... Patch Set 4: > Patch Set 4: > > > What about adding a Kconfig (default n) instead? > > How about removing the option entirely? We already have > enough unused options ;) Huh? Remove an option just because some ucode breaks it? This is a power-saving option we definitely should *not* remove entirely. -- To view, visit https://review.coreboot.org/c/coreboot/+/45417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I556dba59bc06c9101bdfdfd6aee00610aac516e3 Gerrit-Change-Number: 45417 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Andrew McRae <amcrae(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jonas Löffelholz <jonas.loeffelholz(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 17 Sep 2020 07:16:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/zork:Add dptc interface support
by chris wang (Code Review) 17 Sep '20

17 Sep '20

Hello Chris Wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45153 to review the following change. Change subject: mb/google/zork:Add dptc interface support ...................................................................... mb/google/zork:Add dptc interface support Add dptc interface in devicetree.the variants can set below power parameters in overridetree as below ex: dptc_enable = 1 dptc_fast_ppt_limit = 24000 dptc_slow_ppt_limit = 20000 dptc_sustained_power_limit = 6000 BUG=b:157943445 BRANCH=none TEST=Build. check the setting changed. Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: I4dac4b7e5157ad7ad407f42a6fc6b06eefbf3291 --- M src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb M src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb M src/mainboard/google/zork/variants/baseboard/include/baseboard/thermal.h 3 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/45153/1 diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index 42219d7..f240a7c 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -40,6 +40,8 @@ # End : OPN Performance Configuration + register "dptc_enable" = "0" + register "sd_emmc_config" = "SD_EMMC_EMMC_HS400" register "xhci0_force_gen1" = "0" diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index 1620643..50fadae 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -40,6 +40,8 @@ # End : OPN Performance Configuration + register "dptc_enable" = "0" + register "sd_emmc_config" = "SD_EMMC_EMMC_HS400" register "xhci0_force_gen1" = "0" diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/thermal.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/thermal.h index b3c951b..fd110cc 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/thermal.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/thermal.h @@ -3,6 +3,8 @@ #ifndef THERMAL_H #define THERMAL_H +#define DPTC_SUPPORT_ENABLE + /* * Picasso Thermal Requirements * TDP (W) 15 -- To view, visit https://review.coreboot.org/c/coreboot/+/45153 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4dac4b7e5157ad7ad407f42a6fc6b06eefbf3291 Gerrit-Change-Number: 45153 Gerrit-PatchSet: 1 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

5 19

Change in coreboot[master]: soc/intel/common/block: Do not die if PRMRR size unsupported
by Angel Pons (Code Review) 16 Sep '20

16 Sep '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45373 ) Change subject: soc/intel/common/block: Do not die if PRMRR size unsupported ...................................................................... soc/intel/common/block: Do not die if PRMRR size unsupported If a given PRMRR size is not supported, do NOT brick people's devices. We don't do that when PRMRRs aren't even supported anyway. Change-Id: Ib917be873aedbc5e789bb0894fca335b5ee9e2c2 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/common/block/cpu/cpulib.c 1 file changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/45373/1 diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 794c900..6ca7a53 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -369,10 +369,11 @@ valid_size = 0; } - /* die if we could not find a valid size within the limit */ - if (!valid_size) - die("Unsupported PRMRR size limit %i MiB, check your config!\n", + if (!valid_size) { + printk(BIOS_WARNING, "Unsupported PRMRR size of %i MiB, check your config!\n", CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_PRMRR_SIZE); + return 0; + } printk(BIOS_DEBUG, "PRMRR size set to %i MiB\n", valid_size); -- To view, visit https://review.coreboot.org/c/coreboot/+/45373 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib917be873aedbc5e789bb0894fca335b5ee9e2c2 Gerrit-Change-Number: 45373 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

5 19

Change in coreboot[master]: [RFC|NEEDTEST] soc/intel: cnl,icl,elh,jsl,tgl: enable C6DRAM
by Nico Huber (Code Review) 16 Sep '20

16 Sep '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45417 ) Change subject: [RFC|NEEDTEST] soc/intel: cnl,icl,elh,jsl,tgl: enable C6DRAM ...................................................................... Patch Set 4: > What about adding a Kconfig (default n) instead? How about removing the option entirely? We already have enough unused options ;) -- To view, visit https://review.coreboot.org/c/coreboot/+/45417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I556dba59bc06c9101bdfdfd6aee00610aac516e3 Gerrit-Change-Number: 45417 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Andrew McRae <amcrae(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jonas Löffelholz <jonas.loeffelholz(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 16 Sep 2020 21:19:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [RFC|NEEDTEST] soc/intel: cnl,icl,elh,jsl,tgl: enable C6DRAM
by Angel Pons (Code Review) 16 Sep '20

16 Sep '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45417 ) Change subject: [RFC|NEEDTEST] soc/intel: cnl,icl,elh,jsl,tgl: enable C6DRAM ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/45417/4//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45417/4//COMMIT_MSG@19 PS4, Line 19: Hopefully Then... Why not keep it as a Kconfig option? Not everyone wants to enable it. You can still have it enabled by default. -- To view, visit https://review.coreboot.org/c/coreboot/+/45417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I556dba59bc06c9101bdfdfd6aee00610aac516e3 Gerrit-Change-Number: 45417 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Andrew McRae <amcrae(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jonas Löffelholz <jonas.loeffelholz(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 16 Sep 2020 21:05:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: rename get_prmrr_size
by Nico Huber (Code Review) 16 Sep '20

16 Sep '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45414 ) Change subject: soc/intel: rename get_prmrr_size ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id243be50acb741f2c3118ddde082743d08983a53 Gerrit-Change-Number: 45414 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 16 Sep 2020 21:01:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/sgx: drop no-ops from PRMRR Kconfig
by Nico Huber (Code Review) 16 Sep '20

16 Sep '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45413 ) Change subject: soc/intel/common/block/sgx: drop no-ops from PRMRR Kconfig ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45413 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7a19c7223a0de2e03b7df9184cddf7c9fc87a68 Gerrit-Change-Number: 45413 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 16 Sep 2020 21:00:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/sgx: make PRMRR size setting depend on SGX
by Nico Huber (Code Review) 16 Sep '20

16 Sep '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45412 ) Change subject: soc/intel/common/block/sgx: make PRMRR size setting depend on SGX ...................................................................... Patch Set 2: Code-Review+1 Please also update get_prmrr_size() to bail out early if SGX is disabled (i.e. change the check `!..._BLOCK_SGX` to `!..._BLOCK_SGX_ENABLE`). -- To view, visit https://review.coreboot.org/c/coreboot/+/45412 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I551942fd9cb8e7123d00dbd752abffe24788148c Gerrit-Change-Number: 45412 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 16 Sep 2020 21:00:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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