coreboot-gerrit September 2020

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Change in coreboot[master]: Documentation/mainboard/index.md: Add link to x131e Documentation/mai...
by James Young (Code Review) 16 Sep '20

16 Sep '20

James Young has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45457 ) Change subject: Documentation/mainboard/index.md: Add link to x131e Documentation/mainboard/lenovo/x131e.md: Add page for x131e Signed-off-by: James Young <james(a)foreveryoung.id.au> Change-Id: Iff5aacf905ad6d3a3500d14551054defe0b10ef2 ...................................................................... Documentation/mainboard/index.md: Add link to x131e Documentation/mainboard/lenovo/x131e.md: Add page for x131e Signed-off-by: James Young <james(a)foreveryoung.id.au> Change-Id: Iff5aacf905ad6d3a3500d14551054defe0b10ef2 Change-Id: I3f00eaa1a98b9f80be8fc66cbc54028cc0773f62 --- M Documentation/mainboard/index.md A Documentation/mainboard/lenovo/x131e.md 2 files changed, 94 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/45457/1 diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 0eefee8..9e2f3d0 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -77,6 +77,7 @@ - [R60](lenovo/r60.md) - [T4xx common](lenovo/t4xx_series.md) - [X2xx common](lenovo/x2xx_series.md) +- [X131e](lenovo/X131e.md) - [vboot](lenovo/vboot.md) ### Arrandale series diff --git a/Documentation/mainboard/lenovo/x131e.md b/Documentation/mainboard/lenovo/x131e.md new file mode 100644 index 0000000..1b6135b --- /dev/null +++ b/Documentation/mainboard/lenovo/x131e.md @@ -0,0 +1,93 @@ +# Lenovo Ivy Bridge series + +This information is valid for X131e. + +## Flashing coreboot +```eval_rst ++---------------------+--------------------------------+ +| Type | Value | ++=====================+================================+ +| Socketed flash | no | ++---------------------+--------------------------------+ +| Size | 8 MiB + 4MiB | ++---------------------+--------------------------------+ +| In circuit flashing | Yes | ++---------------------+--------------------------------+ +| Package | SOIC-8 | ++---------------------+--------------------------------+ +| Write protection | No | ++---------------------+--------------------------------+ +| Dual BIOS feature | No | ++---------------------+--------------------------------+ +| Internal flashing | Yes | ++---------------------+--------------------------------+ +``` + +## Installation instructions +* Update the EC firmware, as there's no support for EC updates in coreboot. +* Do **NOT** accidently swap pins or power on the board while a SPI flasher + is connected. It will permanently brick your device. +* It's recommended to only flash the BIOS region. In that case you don't + need to extract blobs from vendor firmware. + If you want to flash the whole chip, you need blobs when building + coreboot. +* The *Flash layout* shows that by default 7MiB of space are available for + the use with coreboot. +* In that case you only want to use a part of the BIOS region that must not + exceed 4MiB in size, which means CONFIG_CBFS_SIZE must be smaller than 4MiB. +* ROM chip size should be set to 12MiB. + +```eval_rst +Please also have a look at :doc:`../../flash_tutorial/index`. +``` + +## Splitting the coreboot.rom + +To split the coreboot.rom into two images (one for the 8MiB and one for the +4 MiB flash IC), run the following commands: + +```bash +dd of=top.rom bs=1M if=build/coreboot.rom skip=8 +dd of=bottom.rom bs=1M if=build/coreboot.rom count=8 +``` + +That gives one ROM for each flash IC, where *top.rom* is the upper part of the +flash image, that resides on the 4 MiB flash and *bottom.rom* is the lower part +of the flash image, that resides on the 8 MiB flash. + +## Dumping a full ROM + +If you flash externally you need to read both flash chips to get two images +(one for the 8MiB and one for the 4 MiB flash IC), and then run the following +command to concatenate the files: + +```bash +cat bottom.rom top.rom > firmware.rom +``` + +## Flash layout +There's one 8MiB and one 4 MiB flash which contains IFD, GBE, ME and +BIOS region. These two flash ICs appear as a single 12MiB when flashing +internally. +On Lenovo's UEFI the EC firmware update is placed at the start of the BIOS +region. The update is then written into the EC once. + +![][fl] + +[fl]: flashlayout_Ivy_Bridge.svg + +## Reducing Intel Managment Engine firmware size + +It is possible to reduce the Intel ME firmware size to free additional +space for the `bios` region. This is usually referred to as *cleaning the ME* or +*stripping the ME*. +After reducing the Intel ME firmware size you must modify the original IFD, +[split the resulting coreboot ROM](#splitting-the-coreboot-rom) and then write +each ROM using an [external programmer]. +Have a look at [me_cleaner] for more information. + +Tests on Lenovo X131e showed no issues with a stripped and shrunken ME firmware. + + +[me_cleaner]: ../../northbridge/intel/sandybridge/me_cleaner.md +[external programmer]: ../../flash_tutorial/index.md -- To view, visit https://review.coreboot.org/c/coreboot/+/45457 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f00eaa1a98b9f80be8fc66cbc54028cc0773f62 Gerrit-Change-Number: 45457 Gerrit-PatchSet: 1 Gerrit-Owner: James Young Gerrit-MessageType: newchange

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Change in coreboot[master]: [RFC|NEEDTEST] soc/intel: cnl,icl,elh,jsl,tgl: enable C6DRAM
by Tim Wawrzynczak (Code Review) 16 Sep '20

16 Sep '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45417 ) Change subject: [RFC|NEEDTEST] soc/intel: cnl,icl,elh,jsl,tgl: enable C6DRAM ...................................................................... Patch Set 4: > Patch Set 3: > > > Patch Set 2: > > > > So I went back and reviewed the literature, and there have been instances on several chipsets where the c6dram feature was broken in certain ucode releases. > > Ouch. Can you provide more info on that like uc versions? Is that "literature" public? > I will try to dig up and share as much as I can. > > I think this is reason enough to leave this off by default, but leave the option open in the devicetree > > Then it's not good to have it in the devicetree, since the devicetree doesn't force any microcode, right? > > What about adding a Kconfig (default n) instead? SGTM -- To view, visit https://review.coreboot.org/c/coreboot/+/45417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I556dba59bc06c9101bdfdfd6aee00610aac516e3 Gerrit-Change-Number: 45417 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Andrew McRae <amcrae(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jonas Löffelholz <jonas.loeffelholz(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 16 Sep 2020 20:33:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] mb/system76/lemp9: move/rename to clevo/l140cu
by Michael Niewöhner (Code Review) 16 Sep '20

16 Sep '20

Michael Niewöhner has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/43632 ) Change subject: [WIP] mb/system76/lemp9: move/rename to clevo/l140cu ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/43632 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3903eaf100039f12e0bdc2b99abd28fb144d0d18 Gerrit-Change-Number: 43632 Gerrit-PatchSet: 21 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: region_file_update_data: Change API to accept array of structs
by Shelley Chen (Code Review) 16 Sep '20

16 Sep '20

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45407 ) Change subject: region_file_update_data: Change API to accept array of structs ...................................................................... region_file_update_data: Change API to accept array of structs Updating region_file_update_data to accept mutliple data buffers. This is useful for when we have the mrc_metadata and data in non-contiguous addresses, which is the case when we bypass the storing of mrc_cache data into the cbmem. BUG=b:150502246 BRANCH=None TEST=reboot from ec console. Make sure memory training happens. reboot from ec console. Make sure that we don't do training again. Change-Id: Ia530f7d428b9b07ce3a73e348016038d9daf4c15 Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/drivers/mrc_cache/mrc_cache.c M src/include/region_file.h M src/lib/region_file.c 3 files changed, 47 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/45407/1 diff --git a/src/drivers/mrc_cache/mrc_cache.c b/src/drivers/mrc_cache/mrc_cache.c index 0e42120..4cfd921 100644 --- a/src/drivers/mrc_cache/mrc_cache.c +++ b/src/drivers/mrc_cache/mrc_cache.c @@ -419,9 +419,13 @@ printk(BIOS_DEBUG, "MRC: cache data '%s' needs update.\n", cr->name); - if (region_file_update_data(&cache_file, - cbmem_entry_start(to_be_updated), - cbmem_entry_size(to_be_updated)) < 0) { + struct update_region_file_entry entries[1]; + struct update_region_file_entry cbmem_entry = { + .size = cbmem_entry_size(to_be_updated), + .data = cbmem_entry_start(to_be_updated), + }; + entries[0] = cbmem_entry; + if (region_file_update_data(&cache_file, entries, 1) < 0) { printk(BIOS_DEBUG, "MRC: failed to update '%s'.\n", cr->name); log_event_cache_update(cr->elog_slot, UPDATE_FAILURE); } else { @@ -544,7 +548,13 @@ /* Push an update that consists of 4 bytes that is smaller than the * MRC metadata as well as an invalid signature. */ - if (region_file_update_data(&cache_file, &invalid, sizeof(invalid)) < 0) + struct update_region_file_entry entries[1]; + struct update_region_file_entry invalid_entry = { + .size = sizeof(invalid), + .data = &invalid, + }; + entries[0] = invalid_entry; + if (region_file_update_data(&cache_file, entries, 1) < 0) printk(BIOS_ERR, "MRC: invalidation failed for '%s'.\n", name); } diff --git a/src/include/region_file.h b/src/include/region_file.h index 063e0e0..b5767d8 100644 --- a/src/include/region_file.h +++ b/src/include/region_file.h @@ -31,9 +31,21 @@ */ int region_file_data(const struct region_file *f, struct region_device *rdev); +/** + * Creating region file entry struct to insert multiple data buffers + * into the same region_file. + */ +struct update_region_file_entry { + /* size of this entry */ + int size; + /* data pointer */ + const void *data; +}; + /* Update region file with latest data. Returns < 0 on error, 0 on success. */ -int region_file_update_data(struct region_file *f, const void *buf, - size_t size); +int region_file_update_data(struct region_file *f, + struct update_region_file_entry *entries, + size_t num_entries); /* Declared here for easy object allocation. */ struct region_file { diff --git a/src/lib/region_file.c b/src/lib/region_file.c index ce2ed30..8fce3f9 100644 --- a/src/lib/region_file.c +++ b/src/lib/region_file.c @@ -365,12 +365,16 @@ return 0; } -static int commit_data(const struct region_file *f, const void *buf, - size_t size) +static int commit_data(const struct region_file *f, + struct update_region_file_entry *entries, + size_t num_entries) { size_t offset = block_to_bytes(region_file_data_begin(f)); - if (rdev_writeat(&f->rdev, buf, offset, size) < 0) - return -1; + for (int i = 0; i < num_entries; i++) { + if (rdev_writeat(&f->rdev, entries[i].data, offset, entries[i].size) < 0) + return -1; + offset += entries[i].size; + } return 0; } @@ -399,8 +403,9 @@ return 0; } -static int handle_update(struct region_file *f, size_t blocks, const void *buf, - size_t size) +static int handle_update(struct region_file *f, size_t blocks, + struct update_region_file_entry *entries, + size_t num_entries) { if (!update_can_fit(f, blocks)) { printk(BIOS_INFO, "REGF update can't fit. Will empty.\n"); @@ -413,7 +418,7 @@ return -1; } - if (commit_data(f, buf, size)) { + if (commit_data(f, entries, num_entries)) { printk(BIOS_ERR, "REGF failed to commit data.\n"); return -1; } @@ -421,11 +426,16 @@ return 0; } -int region_file_update_data(struct region_file *f, const void *buf, size_t size) +int region_file_update_data(struct region_file *f, + struct update_region_file_entry *entries, + size_t num_entries) { int ret; size_t blocks; + size_t size = 0; + for (int i = 0; i < num_entries; i++) + size += entries[i].size; blocks = bytes_to_block(ALIGN_UP(size, REGF_BLOCK_GRANULARITY)); while (1) { @@ -442,7 +452,7 @@ ret = -1; break; default: - ret = handle_update(f, blocks, buf, size); + ret = handle_update(f, blocks, entries, num_entries); break; } -- To view, visit https://review.coreboot.org/c/coreboot/+/45407 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia530f7d428b9b07ce3a73e348016038d9daf4c15 Gerrit-Change-Number: 45407 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso/data_fabric: include types.h
by Felix Held (Code Review) 16 Sep '20

16 Sep '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45429 ) Change subject: soc/amd/picasso/data_fabric: include types.h ...................................................................... soc/amd/picasso/data_fabric: include types.h data_fabric.c uses types from stdint.h, but doesn't include stdint.h directly, so replace the inclusion of stdbool.h with types.h which includes both stdbool.h and stdint.h. Change-Id: I4c1ea444e50218cf19fc8fff499929336265bd03 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/data_fabric.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/45429/1 diff --git a/src/soc/amd/picasso/data_fabric.c b/src/soc/amd/picasso/data_fabric.c index 23cb94c..daeca99 100644 --- a/src/soc/amd/picasso/data_fabric.c +++ b/src/soc/amd/picasso/data_fabric.c @@ -10,7 +10,7 @@ #include <soc/data_fabric.h> #include <soc/iomap.h> #include <soc/pci_devs.h> -#include <stdbool.h> +#include <types.h> static void disable_mmio_reg(int reg) { -- To view, visit https://review.coreboot.org/c/coreboot/+/45429 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c1ea444e50218cf19fc8fff499929336265bd03 Gerrit-Change-Number: 45429 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso/data_fabric: make register number parameter unsigned
by Felix Held (Code Review) 16 Sep '20

16 Sep '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45430 ) Change subject: soc/amd/picasso/data_fabric: make register number parameter unsigned ...................................................................... soc/amd/picasso/data_fabric: make register number parameter unsigned The register number is always non-negative, so it should be an unsigned type. Change-Id: I6b6df5a41fe58efc53eaa87c01b88426ea8daa6e Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/data_fabric.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/45430/1 diff --git a/src/soc/amd/picasso/data_fabric.c b/src/soc/amd/picasso/data_fabric.c index daeca99..ac4e23d 100644 --- a/src/soc/amd/picasso/data_fabric.c +++ b/src/soc/amd/picasso/data_fabric.c @@ -12,7 +12,7 @@ #include <soc/pci_devs.h> #include <types.h> -static void disable_mmio_reg(int reg) +static void disable_mmio_reg(unsigned int reg) { pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_CONTROL(reg), IOMS0_FABRIC_ID << MMIO_DST_FABRIC_ID_SHIFT); @@ -20,7 +20,7 @@ pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_LIMIT(reg), 0); } -static bool is_mmio_reg_disabled(int reg) +static bool is_mmio_reg_disabled(unsigned int reg) { uint32_t val = pci_read_config32(SOC_DF_F0_DEV, NB_MMIO_CONTROL(reg)); return !(val & ((MMIO_WE | MMIO_RE))); -- To view, visit https://review.coreboot.org/c/coreboot/+/45430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b6df5a41fe58efc53eaa87c01b88426ea8daa6e Gerrit-Change-Number: 45430 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: xeon_sp/skx: Reorder pci_devs.h
by Marc Jones (Code Review) 16 Sep '20

16 Sep '20

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45220 ) Change subject: xeon_sp/skx: Reorder pci_devs.h ...................................................................... xeon_sp/skx: Reorder pci_devs.h Reorder to be similar to cpx/include/soc/pci_devs.h. We may be able to merge the files in the future. Change-Id: I939707cc9e58e23f053156f40df4c21a6072570b Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h 1 file changed, 62 insertions(+), 62 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/45220/1 diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h index bce7738..6da3405 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h @@ -31,26 +31,6 @@ #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) #endif -#define MMAP_VTD_CFG_REG_DEVID 0x2024 -#define VTD_DEV 5 -#define VTD_FUNC 0 - -#define VTD_TOLM_CSR 0xd0 -#define VTD_TSEG_BASE_CSR 0xa8 -#define VTD_TSEG_LIMIT_CSR 0xac -#define VTD_EXT_CAP_LOW 0x10 -#define VTD_MMCFG_BASE_CSR 0x90 -#define VTD_MMCFG_LIMIT_CSR 0x98 -#define VTD_TOHM_CSR 0xd4 -#define VTD_MMIOL_CSR 0xdc -#define VTD_ME_BASE_CSR 0xf0 -#define VTD_ME_LIMIT_CSR 0xf8 -#define VTD_VERSION 0x00 -#define VTD_CAP 0x08 -#define VTD_CAP_LOW 0x08 -#define VTD_CAP_HIGH 0x0C -#define VTD_EXT_CAP_HIGH 0x14 - #define SAD_ALL_DEV 29 #define SAD_ALL_FUNC 0 #define SAD_ALL_PAM0123_CSR 0x40 @@ -71,6 +51,15 @@ #define MAX_NON_TURBO_LIM_RATIO_SHIFT 8 /* 8:15 */ #define MAX_NON_TURBO_LIM_RATIO_MASK (0xff << MAX_NON_TURBO_LIM_RATIO_SHIFT) +#define PCU_CR1_BIOS_MB_DATA_REG 0x8c + +#define PCU_CR1_BIOS_MB_INTERFACE_REG 0x90 +#define BIOS_MB_RUN_BUSY_MASK ((uint32_t)1 << 31) +#define BIOS_MB_CMD_MASK ((uint32_t)0xff) +#define BIOS_CMD_READ_PCU_MISC_CFG 0x5 +#define BIOS_CMD_WRITE_PCU_MISC_CFG 0x6 +#define BIOS_ERR_INVALID_CMD 0x01 + #define PCU_CR1_BIOS_RESET_CPL_REG 0x94 #define RST_CPL1_MASK ((uint32_t)1 << 1) #define RST_CPL2_MASK ((uint32_t)1 << 2) @@ -81,18 +70,30 @@ #define PCODE_INIT_DONE3_MASK ((uint32_t)1 << 11) #define PCODE_INIT_DONE4_MASK ((uint32_t)1 << 12) -#define PCU_CR1_BIOS_MB_DATA_REG 0x8c - -#define PCU_CR1_BIOS_MB_INTERFACE_REG 0x90 -#define BIOS_MB_RUN_BUSY_MASK ((uint32_t)1 << 31) -#define BIOS_MB_CMD_MASK ((uint32_t)0xff) -#define BIOS_CMD_READ_PCU_MISC_CFG 0x5 -#define BIOS_CMD_WRITE_PCU_MISC_CFG 0x6 -#define BIOS_ERR_INVALID_CMD 0x01 - #define PCU_CR1_DESIRED_CORES_CFG2_REG 0xa0 #define PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK ((uint32_t)1 << 31) +#define UBOX_DECS_BUS 0 +#define UBOX_DECS_DEV 8 +#define UBOX_DECS_FUNC 2 +#define UBOX_DECS_CPUBUSNO_CSR 0xcc + +#define VTD_TOLM_CSR 0xd0 +#define VTD_TSEG_BASE_CSR 0xa8 +#define VTD_TSEG_LIMIT_CSR 0xac +#define VTD_EXT_CAP_LOW 0x10 +#define VTD_MMCFG_BASE_CSR 0x90 +#define VTD_MMCFG_LIMIT_CSR 0x98 +#define VTD_TOHM_CSR 0xd4 +#define VTD_MMIOL_CSR 0xdc +#define VTD_ME_BASE_CSR 0xf0 +#define VTD_ME_LIMIT_CSR 0xf8 +#define VTD_VERSION 0x00 +#define VTD_CAP 0x08 +#define VTD_CAP_LOW 0x08 +#define VTD_CAP_HIGH 0x0C +#define VTD_EXT_CAP_HIGH 0x14 + #define PCU_CR1_C2C3TT_REG 0xdc #define PCU_CR1_PCIE_ILTR_OVRD 0xfc #define PCU_CR1_SAPMCTL 0xb0 @@ -111,30 +112,49 @@ #define PCU_CR2_PROCHOT_RESPONSE_RATIO_REG 0xb0 #define PROCHOT_RATIO 0xa /* bits 0:7 */ -#define UBOX_DECS_BUS 0 -#define UBOX_DECS_DEV 8 -#define UBOX_DECS_FUNC 2 -#define UBOX_DECS_CPUBUSNO_CSR 0xcc - #define CHA_UTIL_ALL_DEV 29 #define CHA_UTIL_ALL_FUNC 1 #define CHA_UTIL_ALL_MMCFG_CSR 0xc0 -#define CBDMA_DEV_NUM 0x04 -#define IIO_CBDMA_MMIO_SIZE 0x10000 //64kB for one CBDMA function -#define IIO_CBDMA_MMIO_ALIGNMENT 14 //2^14 - 16kB +/* PCH Device info */ -#define VMD_DEV_NUM 5 -#define VMD_FUNC_NUM 5 +#define XHCI_BUS_NUMBER 0x0 +#define PCH_DEV_SLOT_XHCI 0x14 +#define XHCI_FUNC_NUM 0x0 -#define APIC_DEV_NUM 5 -#define APIC_FUNC_NUM 0 +#define HPET_BUS_NUM 0x0 +#define HPET_DEV_NUM PCH_DEV_SLOT_LPC +#define HPET0_FUNC_NUM 0x00 + +#define MMAP_VTD_CFG_REG_DEVID 0x2024 +#define VTD_DEV 5 +#define VTD_FUNC 0 + +#define PCH_DEV_SLOT_LPC 0x1f +#define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0) +#define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1) +#define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2) +#define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5) +#define PCH_DEV_LPC _PCH_DEV(LPC, 0) +#define PCH_DEV_P2SB _PCH_DEV(LPC, 1) +#define PCH_DEV_PMC _PCH_DEV(LPC, 2) +#define PCH_DEV_SPI _PCH_DEV(LPC, 5) + + +#define CBDMA_DEV_NUM 0x04 +#define IIO_CBDMA_MMIO_SIZE 0x10000 //64kB for one CBDMA function + +#define VMD_DEV_NUM 0x05 +#define VMD_FUNC_NUM 0x05 + +#define APIC_DEV_NUM 0x05 +#define APIC_FUNC_NUM 0x04 #define PCH_IOAPIC_BUS_NUMBER 0xF0 #define PCH_IOAPIC_DEV_NUM 0x1F #define PCH_IOAPIC_FUNC_NUM 0x00 -// ================================== IOAPIC Definitions for DMAR/ACPI ==================== +// ========== IOAPIC Definitions for DMAR/ACPI ======== #define PCH_IOAPIC_ID 0x08 #define PC00_IOAPIC_ID 0x09 #define PC01_IOAPIC_ID 0x0A @@ -149,24 +169,4 @@ #define PC10_IOAPIC_ID 0x13 #define PC11_IOAPIC_ID 0x14 -/* PCH Device info */ - -#define XHCI_BUS_NUMBER 0x0 -#define PCH_DEV_SLOT_XHCI 0x14 -#define XHCI_FUNC_NUM 0x0 - -#define HPET_BUS_NUM 0x0 -#define HPET_DEV_NUM PCH_DEV_SLOT_LPC -#define HPET0_FUNC_NUM 0x00 - -#define PCH_DEV_SLOT_LPC 0x1f -#define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0) -#define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1) -#define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2) -#define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5) -#define PCH_DEV_LPC _PCH_DEV(LPC, 0) -#define PCH_DEV_P2SB _PCH_DEV(LPC, 1) -#define PCH_DEV_PMC _PCH_DEV(LPC, 2) -#define PCH_DEV_SPI _PCH_DEV(LPC, 5) - #endif /* _SOC_PCI_DEVS_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45220 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I939707cc9e58e23f053156f40df4c21a6072570b Gerrit-Change-Number: 45220 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 13

Change in coreboot[master]: xeon_sp/cpx/: Remove duplicate defines in pci_devs.h
by Marc Jones (Code Review) 16 Sep '20

16 Sep '20

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45219 ) Change subject: xeon_sp/cpx/: Remove duplicate defines in pci_devs.h ...................................................................... xeon_sp/cpx/: Remove duplicate defines in pci_devs.h Change-Id: I8fc4e07269175eb2f40655b828e340697a9a892a Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h 1 file changed, 0 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/45219/1 diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h index 17f801b..bcce308 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h @@ -75,19 +75,6 @@ #define VTD_DEV 5 #define VTD_FUNC 0 -#define VMD_DEV_NUM 0x05 -#define VMD_FUNC_NUM 0x05 - -#define APIC_DEV_NUM 0x05 -#define APIC_FUNC_NUM 0x04 - -#define CBDMA_DEV_NUM 0x04 -#define IIO_CBDMA_MMIO_SIZE 0x10000 //64kB for one CBDMA function - -#define PCH_IOAPIC_BUS_NUMBER 0x00 -#define PCH_IOAPIC_DEV_NUM 0x1F -#define PCH_IOAPIC_FUNC_NUM 0x00 - /* PCH Device info */ #define XHCI_BUS_NUMBER 0x0 @@ -114,7 +101,6 @@ #define PCH_DEV_PMC _PCH_DEV(LPC, 2) #define PCH_DEV_SPI _PCH_DEV(LPC, 5) - #define CBDMA_DEV_NUM 0x04 #define IIO_CBDMA_MMIO_SIZE 0x10000 //64kB for one CBDMA function -- To view, visit https://review.coreboot.org/c/coreboot/+/45219 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8fc4e07269175eb2f40655b828e340697a9a892a Gerrit-Change-Number: 45219 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: soc/intel/cannonlake: rename "RSVD" GPIOs to their correct names
by Subrata Banik (Code Review) 16 Sep '20

16 Sep '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45210 ) Change subject: soc/intel/cannonlake: rename "RSVD" GPIOs to their correct names ...................................................................... Patch Set 13: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45210 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59df09c8fd464e75f918455aa1972765abc51459 Gerrit-Change-Number: 45210 Gerrit-PatchSet: 13 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 16 Sep 2020 09:48:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/cannonlake: fix GPIO community numbering in ACPI
by Subrata Banik (Code Review) 16 Sep '20

16 Sep '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45209 ) Change subject: soc/intel/cannonlake: fix GPIO community numbering in ACPI ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f13a28d3e8f427859570a4d209304ae8444efd9 Gerrit-Change-Number: 45209 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 16 Sep 2020 09:47:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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