coreboot-gerrit September 2020

coreboot-gerrit@coreboot.org

1 participants
2628 discussions

Change in coreboot[master]: nb/intel/ironlake: Drop `heci_bar` field from raminit
by Angel Pons (Code Review) 17 Sep '20

17 Sep '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45361 ) Change subject: nb/intel/ironlake: Drop `heci_bar` field from raminit ...................................................................... nb/intel/ironlake: Drop `heci_bar` field from raminit This field is only written to, never read. Drop it from raminfo. Also, bump MRC_CACHE_VERSION as the saved data layout has changed. Change-Id: I83d6e69addff996e2f18472d3e1d4f7b9ba974fd Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/raminit.c 1 file changed, 1 insertion(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/45361/1 diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index 81ba450..6905cae 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -61,7 +61,7 @@ u8 largest; } timing_bounds_t[2][2][2][9]; -#define MRC_CACHE_VERSION 1 +#define MRC_CACHE_VERSION 2 struct ram_training { /* [TM][CHANNEL][SLOT][RANK][LANE] */ @@ -192,7 +192,6 @@ unsigned int interleaved_part_mb; unsigned int non_interleaved_part_mb; - u32 heci_bar; u64 heci_uma_addr; unsigned int memory_reserved_for_heci_mb; @@ -1469,9 +1468,6 @@ while (!(read8((u8 *)0xfed40000) & (1 << 7))) ; - if (!info->heci_bar) - gav(info->heci_bar = - pci_read_config32(HECIDEV, HECIBAR) & 0xFFFFFFF8); if (!info->memory_reserved_for_heci_mb) { /* Wait for ME to be ready */ intel_early_me_init(); @@ -1817,7 +1813,6 @@ if (!((reg44 & 0x10000) && !(pci_read_config32(HECIDEV, 0x40) & 0x20))) return; - info->heci_bar = pci_read_config32(HECIDEV, 0x10) & 0xFFFFFFF0; info->memory_reserved_for_heci_mb = reg44 & 0x3f; info->heci_uma_addr = ((u64) @@ -3727,7 +3722,6 @@ info.training.reg_178 = 0; info.training.reg_10b = 0; - info.heci_bar = 0; info.memory_reserved_for_heci_mb = 0; /* before SPD */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45361 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I83d6e69addff996e2f18472d3e1d4f7b9ba974fd Gerrit-Change-Number: 45361 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: mb/system76/lemp9: drop disabled registers from devicetree
by Felix Singer (Code Review) 17 Sep '20

17 Sep '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45491 ) Change subject: mb/system76/lemp9: drop disabled registers from devicetree ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/c/coreboot/+/45491/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45491/1//COMMIT_MSG@7 PS1, Line 7: registers options -- To view, visit https://review.coreboot.org/c/coreboot/+/45491 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a1a91778e83dc49c6dcf2d518cd3591f7ec4cfa Gerrit-Change-Number: 45491 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Comment-Date: Thu, 17 Sep 2020 22:19:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/system76/lemp9: enable SATA LPM
by Felix Singer (Code Review) 17 Sep '20

17 Sep '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45492 ) Change subject: mb/system76/lemp9: enable SATA LPM ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/c/coreboot/+/45492/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45492/1//COMMIT_MSG@11 PS1, Line 11: Tested successfully. How? -- To view, visit https://review.coreboot.org/c/coreboot/+/45492 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88de28cfb266af3fcd6e498a08a24b46c992cb9d Gerrit-Change-Number: 45492 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Comment-Date: Thu, 17 Sep 2020 22:19:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/system76/lemp9: enable SATA LPM
by Michael Niewöhner (Code Review) 17 Sep '20

17 Sep '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45492 ) Change subject: mb/system76/lemp9: enable SATA LPM ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/45492 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88de28cfb266af3fcd6e498a08a24b46c992cb9d Gerrit-Change-Number: 45492 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Comment-Date: Thu, 17 Sep 2020 22:13:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/system76/lemp9: drop disabled registers from devicetree
by Michael Niewöhner (Code Review) 17 Sep '20

17 Sep '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45491 ) Change subject: mb/system76/lemp9: drop disabled registers from devicetree ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/45491 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a1a91778e83dc49c6dcf2d518cd3591f7ec4cfa Gerrit-Change-Number: 45491 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Comment-Date: Thu, 17 Sep 2020 22:13:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: [WIP] mb/system76/lemp9: use the newly added CNL vGPIOs
by Michael Niewöhner (Code Review) 17 Sep '20

17 Sep '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45490 ) Change subject: [WIP] mb/system76/lemp9: use the newly added CNL vGPIOs ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/45490 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I635780b33b2c0549d0309a0c2ae158baffc8d3f5 Gerrit-Change-Number: 45490 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Thu, 17 Sep 2020 22:01:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/system76/lemp9: use the newly added CNL GPIOs
by Michael Niewöhner (Code Review) 17 Sep '20

17 Sep '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45489 ) Change subject: mb/system76/lemp9: use the newly added CNL GPIOs ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/45489 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a42f8af1da5d767add751cc24907bc8b12294f2 Gerrit-Change-Number: 45489 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Thu, 17 Sep 2020 22:00:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/system76/lemp9: convert GPP_D9 macro to shorter macro
by Michael Niewöhner (Code Review) 17 Sep '20

17 Sep '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45488 ) Change subject: mb/system76/lemp9: convert GPP_D9 macro to shorter macro ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/45488 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I147c82d738623bff54122ad5ef8ece028c562cab Gerrit-Change-Number: 45488 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 17 Sep 2020 21:59:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/system76/lemp9: enable eDP in Fsp
by Michael Niewöhner (Code Review) 17 Sep '20

17 Sep '20

Michael Niewöhner has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/45126 ) Change subject: mb/system76/lemp9: enable eDP in Fsp ...................................................................... Abandoned abandoned in favor of CB:45489 -- To view, visit https://review.coreboot.org/c/coreboot/+/45126 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice5f55e07ea9e028a0b6a904511eb59830351738 Gerrit-Change-Number: 45126 Gerrit-PatchSet: 7 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

1 0

Change in coreboot[master]: soc/intel/cannonlake: add missing special function pads
by Michael Niewöhner (Code Review) 17 Sep '20

17 Sep '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45211 ) Change subject: soc/intel/cannonlake: add missing special function pads ...................................................................... soc/intel/cannonlake: add missing special function pads The following parameters do nothing else than configuring the corresponding pads to native mode: - DdiPortEdp - DdiPort*Hpd - DdiPort*Ddc - GpioDdp* - SpiGpioAssign - I2c*GpioAssign - SerialIoUartDebugEnable - Gp*GpioAssign - Uart*GpioAssign - GpioEnableHdaLink - AudioLinkDmic* - AudioLinkSsp* - GpioEnableHdaSspMasterClock - AudioLinkSndw* - SmbAlertEnable Add the missing special function gpio pad groups for CNL, to be able to configure them via gpio.h instead having to set various FSP parameters. The groups and names are documented in the PCH EDS, in Linux (linux/drivers/pinctrl/intel/pinctrl-cannonlake.c) and other places. Also, see soc/intel/tigerlake for reference. Change-Id: Ia3bc1df1a14dbca7c7213577cb2d5b98bb0acf64 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45211 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/acpi/gpio.asl M src/soc/intel/cannonlake/gpio.c M src/soc/intel/cannonlake/gpio_cnp_h.c M src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h M src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h 5 files changed, 38 insertions(+), 30 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/acpi/gpio.asl b/src/soc/intel/cannonlake/acpi/gpio.asl index 71524de..2a45343 100644 --- a/src/soc/intel/cannonlake/acpi/gpio.asl +++ b/src/soc/intel/cannonlake/acpi/gpio.asl @@ -73,7 +73,7 @@ Subtract (Arg0, GPP_D0, Local1) } /* GPIO Community 2 */ - If (LAnd (LGreaterEqual (Arg0, GPD0), LLessEqual (Arg0, GPD11))) + If (LAnd (LGreaterEqual (Arg0, GPD0), LLessEqual (Arg0, DRAM_RESET_B))) { Store (PID_GPIOCOM2, Local0) Subtract (Arg0, GPD0, Local1) diff --git a/src/soc/intel/cannonlake/gpio.c b/src/soc/intel/cannonlake/gpio.c index 8e08a4b..3c70ad9 100644 --- a/src/soc/intel/cannonlake/gpio.c +++ b/src/soc/intel/cannonlake/gpio.c @@ -47,7 +47,7 @@ /* This community is not visible to the OS */ static const struct pad_group cnl_community2_groups[] = { - INTEL_GPP(GPD0, GPD0, GPD11), /* GPD */ + INTEL_GPP(GPD0, GPD0, DRAM_RESET_B), /* GPD */ }; /* This community is not visible to the OS */ @@ -108,7 +108,7 @@ [COMM_2] = { .port = PID_GPIOCOM2, .first_pad = GPD0, - .last_pad = GPD11, + .last_pad = DRAM_RESET_B, .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, diff --git a/src/soc/intel/cannonlake/gpio_cnp_h.c b/src/soc/intel/cannonlake/gpio_cnp_h.c index a7b1781e..06e344d 100644 --- a/src/soc/intel/cannonlake/gpio_cnp_h.c +++ b/src/soc/intel/cannonlake/gpio_cnp_h.c @@ -47,7 +47,7 @@ /* This community is not visible to the OS */ static const struct pad_group cnl_community2_groups[] = { - INTEL_GPP(GPD0, GPD0, GPD11), /* GPD */ + INTEL_GPP(GPD0, GPD0, DRAM_RESET_B), /* GPD */ }; static const struct pad_group cnl_community3_groups[] = { @@ -110,7 +110,7 @@ [COMM_2] = { .port = PID_GPIOCOM2, .first_pad = GPD0, - .last_pad = GPD11, + .last_pad = DRAM_RESET_B, .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, diff --git a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h index b5d34dc..48cbacb 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h @@ -183,7 +183,7 @@ #define GPP_H21 138 #define GPP_H22 139 #define GPP_H23 140 -/* Group VGPIO */ +/* Group VGPIO 0 */ #define CNV_BTEN 141 #define CNV_GNEN 142 #define CNV_WFEN 143 @@ -216,6 +216,7 @@ #define vISH_UART1_RTS_B 170 #define vCNV_BT_I2S_BCLK 171 #define vCNV_BT_I2S_WS_SYNC 172 +/* Group VGPIO 1 */ #define vCNV_BT_I2S_SDO 173 #define vCNV_BT_I2S_SDI 174 #define vSSP2_SCLK 175 @@ -310,35 +311,38 @@ #define GPD9 253 #define GPD10 254 #define GPD11 255 +#define SLP_LAN_B 256 +#define SLP_SUS_B 257 +#define WAKE_B 258 +#define DRAM_RESET_B 259 -#define NUM_GPIO_COM2_PADS (GPD11 - GPD0 + 1) - +#define NUM_GPIO_COM2_PADS (DRAM_RESET_B - GPD0 + 1) /* Group AZA */ -#define HDA_BCLK 256 -#define HDA_RST_B 257 -#define HDA_SYNC 258 -#define HDA_SDO 259 -#define HDA_SDI0 260 -#define HDA_SDI1 261 -#define I2S1_SFRM 262 -#define I2S1_TXD 263 +#define HDA_BCLK 260 +#define HDA_RST_B 261 +#define HDA_SYNC 262 +#define HDA_SDO 263 +#define HDA_SDI0 264 +#define HDA_SDI1 265 +#define I2S1_SFRM 266 +#define I2S1_TXD 267 /* Group CPU */ -#define HDACPU_SDI 264 -#define HDACPU_SDO 265 -#define HDACPU_SCLK 266 -#define PM_SYNC 267 -#define PECI_IO 268 -#define CPUPWRGD 269 -#define THRMTRIP_B 270 -#define PLTRST_CPU_B 271 -#define PM_DOWN 272 -#define TRIGGER_IN 273 -#define TRIGGER_OUT 274 +#define HDACPU_SDI 268 +#define HDACPU_SDO 269 +#define HDACPU_SCLK 270 +#define PM_SYNC 271 +#define PECI_IO 272 +#define CPUPWRGD 273 +#define THRMTRIP_B 274 +#define PLTRST_CPU_B 275 +#define PM_DOWN 276 +#define TRIGGER_IN 277 +#define TRIGGER_OUT 278 #define NUM_GPIO_COM3_PADS (TRIGGER_OUT - HDA_BCLK + 1) -#define TOTAL_PADS 275 +#define TOTAL_PADS 279 #define SD_PWR_EN_PIN GPP_A17 diff --git a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h index dc332d1..9396c0b 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h @@ -381,10 +381,14 @@ #define GPD9 308 #define GPD10 309 #define GPD11 310 +#define SLP_LAN_B 311 +#define SLP_SUS_B 312 +#define WAKE_B 313 +#define DRAM_RESET_B 314 -#define NUM_GPIO_COM2_PADS (GPD11 - GPD0 + 1) +#define NUM_GPIO_COM2_PADS (DRAM_RESET_B - GPD0 + 1) -#define TOTAL_PADS (GPD11 + 1) +#define TOTAL_PADS (DRAM_RESET_B + 1) #define COMM_0 0 #define COMM_1 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/45211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia3bc1df1a14dbca7c7213577cb2d5b98bb0acf64 Gerrit-Change-Number: 45211 Gerrit-PatchSet: 13 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit September 2020