coreboot-gerrit September 2020

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Change in coreboot[master]: volteer: set GSPI CS to deasserted by default
by Tim Wawrzynczak (Code Review) 15 Sep '20

15 Sep '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45384 ) Change subject: volteer: set GSPI CS to deasserted by default ...................................................................... Patch Set 1: Code-Review+2 (1 comment) https://review.coreboot.org/c/coreboot/+/45384/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45384/1//COMMIT_MSG@9 PS1, Line 9: This sets the state of GSPI chip select to 1 (deasserted). GSPI 0 and Could you mention this is set by the FSP? -- To view, visit https://review.coreboot.org/c/coreboot/+/45384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47aa5db429d75e66095d58a1eb77963dcfc3b9f3 Gerrit-Change-Number: 45384 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Andrey Pronin <apronin(a)chromium.org> Gerrit-Reviewer: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 15 Sep 2020 16:35:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: console: Allow VPD to disable an otherwise enabled coreboot console
by Patrick Georgi (Code Review) 15 Sep '20

15 Sep '20

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45208 ) Change subject: console: Allow VPD to disable an otherwise enabled coreboot console ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/45208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f1f5c45e5ea889176d04e0db438ca2aa7c536ee Gerrit-Change-Number: 45208 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Dossym Nurmukhanov <dossym(a)google.com> Gerrit-Reviewer: Greg Edelston <gredelston(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 15 Sep 2020 16:10:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/jasperlake_rvp: Fix wrong comments for ECT
by Subrata Banik (Code Review) 15 Sep '20

15 Sep '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45338 ) Change subject: mb/intel/jasperlake_rvp: Fix wrong comments for ECT ...................................................................... mb/intel/jasperlake_rvp: Fix wrong comments for ECT Disable -> Enable Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Change-Id: Iccefb02fa9bf9507b9e679b3fba35c5c28d677a1 --- M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/45338/1 diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c index 434e9dd..46499f4 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c @@ -42,7 +42,7 @@ /* Baseboard Rcomp target values */ .rcomp_targets = {0, 0, 0, 0, 0}, - /* Disable Early Command Training */ + /* Enable Early Command Training */ .ect = 1, /* Set Board Type */ @@ -87,7 +87,7 @@ */ .rcomp_targets = {80, 40, 40, 40, 30}, - /* Disable Early Command Training */ + /* Enable Early Command Training */ .ect = 1, /* Set Board Type */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45338 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccefb02fa9bf9507b9e679b3fba35c5c28d677a1 Gerrit-Change-Number: 45338 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake/romstage: Do initial SoC commit till romstage
by Subrata Banik (Code Review) 15 Sep '20

15 Sep '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45192 ) Change subject: soc/intel/alderlake/romstage: Do initial SoC commit till romstage ...................................................................... soc/intel/alderlake/romstage: Do initial SoC commit till romstage List of changes: 1. Add required SoC programming till bootblock 2. Include only required headers into include/soc 3. Add SA EDS document number and chapter number 4. Fill required FSP-M UPD to call FSP-M API Change-Id: I4473aed27363c22e92e66cc6770cb55aae83e75c Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/include/soc/iomap.h A src/soc/intel/alderlake/include/soc/msr.h A src/soc/intel/alderlake/include/soc/romstage.h A src/soc/intel/alderlake/include/soc/soc_chip.h A src/soc/intel/alderlake/include/soc/systemagent.h A src/soc/intel/alderlake/romstage/Makefile.inc A src/soc/intel/alderlake/romstage/fsp_params.c A src/soc/intel/alderlake/romstage/pch.c A src/soc/intel/alderlake/romstage/romstage.c A src/soc/intel/alderlake/romstage/systemagent.c 11 files changed, 521 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/45192/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index b873a03..0c5c13c 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -8,15 +8,21 @@ config CPU_SPECIFIC_OPTIONS def_bool y select ARCH_BOOTBLOCK_X86_32 + select ARCH_ROMSTAGE_X86_32 + select ARCH_VERSTAGE_X86_32 select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES + select CACHE_MRC_SETTINGS + select FSP_M_XIP select INTEL_DESCRIPTOR_MODE_CAPABLE select IDT_IN_EVERY_STAGE select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED + select MRC_SETTINGS_PROTECT select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_2 select SOC_INTEL_COMMON select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_SA @@ -120,6 +126,13 @@ config CHROMEOS select CHROMEOS_RAMOOPS_DYNAMIC +config VBOOT + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_MUST_REQUEST_DISPLAY + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_VBNV_CMOS + select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH + config C_ENV_BOOTBLOCK_SIZE hex default 0xC000 @@ -139,4 +152,20 @@ string depends on FSP_USE_REPO default "3rdparty/fsp/AlderLakeFspBinPkg/Fsp.fd" + +config SOC_INTEL_ALDERLAKE_DEBUG_CONSENT + int "Debug Consent for ADL" + # USB DBC is more common for developers so make this default to 3 if + # SOC_INTEL_DEBUG_CONSENT=y + default 3 if SOC_INTEL_DEBUG_CONSENT + default 0 + help + This is to control debug interface on SOC. + Setting non-zero value will allow to use DBC or DCI to debug SOC. + PlatformDebugConsent in FspmUpd.h has the details. + + Desired platform debug type are + 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), + 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), + 6:Enable (2-wire DCI OOB), 7:Manual endif diff --git a/src/soc/intel/alderlake/include/soc/iomap.h b/src/soc/intel/alderlake/include/soc/iomap.h index e71ddb5..88fab6f 100644 --- a/src/soc/intel/alderlake/include/soc/iomap.h +++ b/src/soc/intel/alderlake/include/soc/iomap.h @@ -38,6 +38,27 @@ #define EDRAM_BASE_ADDRESS 0xfed80000 #define EDRAM_BASE_SIZE 0x4000 +#define TBT0_BASE_ADDRESS 0xfed84000 +#define TBT0_BASE_SIZE 0x1000 + +#define TBT1_BASE_ADDRESS 0xfed85000 +#define TBT1_BASE_SIZE 0x1000 + +#define TBT2_BASE_ADDRESS 0xfed86000 +#define TBT2_BASE_SIZE 0x1000 + +#define TBT3_BASE_ADDRESS 0xfed87000 +#define TBT3_BASE_SIZE 0x1000 + +#define GFXVT_BASE_ADDRESS 0xfed90000 +#define GFXVT_BASE_SIZE 0x1000 + +#define IPUVT_BASE_ADDRESS 0xfed92000 +#define IPUVT_BASE_SIZE 0x1000 + +#define VTVC0_BASE_ADDRESS 0xfed91000 +#define VTVC0_BASE_SIZE 0x1000 + #define REG_BASE_ADDRESS 0xfb000000 #define REG_BASE_SIZE 0x1000 diff --git a/src/soc/intel/alderlake/include/soc/msr.h b/src/soc/intel/alderlake/include/soc/msr.h new file mode 100644 index 0000000..67e09dc --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/msr.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_MSR_H_ +#define _SOC_MSR_H_ + +#include <intelblocks/msr.h> + +#define MSR_PIC_MSG_CONTROL 0x2e +#define MSR_VR_MISC_CONFIG2 0x636 + +#endif diff --git a/src/soc/intel/alderlake/include/soc/romstage.h b/src/soc/intel/alderlake/include/soc/romstage.h new file mode 100644 index 0000000..baa35c5 --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/romstage.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_ROMSTAGE_H_ +#define _SOC_ROMSTAGE_H_ + +#include <fsp/api.h> + +/* Provide a callback to allow mainboard to override the DRAM part number. */ +bool mainboard_get_dram_part_num(const char **part_num, size_t *len); +void mainboard_memory_init_params(FSPM_UPD *mupd); +void systemagent_early_init(void); +void romstage_pch_init(void); + +/* Board type */ +enum board_type { + BOARD_TYPE_MOBILE = 0, + BOARD_TYPE_DESKTOP = 1, + BOARD_TYPE_ULT_ULX = 5, + BOARD_TYPE_SERVER = 7 +}; + +#endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/soc/intel/alderlake/include/soc/soc_chip.h b/src/soc/intel/alderlake/include/soc/soc_chip.h new file mode 100644 index 0000000..584eda2 --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/soc_chip.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_ALDERLAKE_SOC_CHIP_H_ +#define _SOC_ALDERLAKE_SOC_CHIP_H_ + +#include "../../chip.h" + +#endif /* _SOC_ALDERLAKE_SOC_CHIP_H_ */ diff --git a/src/soc/intel/alderlake/include/soc/systemagent.h b/src/soc/intel/alderlake/include/soc/systemagent.h new file mode 100644 index 0000000..8798f1d --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/systemagent.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on Intel Alder Lake Processor SA Datasheet + * Document number: 619503 + * Chapter number: 3 + */ + +#ifndef SOC_ALDERLAKE_SYSTEMAGENT_H +#define SOC_ALDERLAKE_SYSTEMAGENT_H + +#include <intelblocks/systemagent.h> + +/* Device 0:0.0 PCI configuration space */ + +#define EPBAR 0x40 +#define DMIBAR 0x68 +#define CAPID0_A 0xe4 +#define VTD_DISABLE (1 << 23) + +#define BIOS_RESET_CPL 0x5da8 +#define GFXVTBAR 0x5400 +#define EDRAMBAR 0x5408 +#define VTVC0BAR 0x5410 +#define REGBAR 0x5420 +#define IPUVTBAR 0x7880 +#define TBT0BAR 0x7888 +#define TBT1BAR 0x7890 +#define TBT2BAR 0x7898 +#define TBT3BAR 0x78A0 +#define MAX_TBT_PCIE_PORT 4 + +#define VTBAR_ENABLED 0x01 +#define VTBAR_MASK 0x7ffffff000ull + +#define MCH_PKG_POWER_LIMIT_LO 0x59a0 +#define MCH_PKG_POWER_LIMIT_HI 0x59a4 +#define MCH_DDR_POWER_LIMIT_LO 0x58e0 +#define MCH_DDR_POWER_LIMIT_HI 0x58e4 + +#define IMRBASE 0x6A40 +#define IMRLIMIT 0x6A48 + +static const struct sa_mmio_descriptor soc_vtd_resources[] = { + { GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" }, + { IPUVTBAR, IPUVT_BASE_ADDRESS, IPUVT_BASE_SIZE, "IPUVTBAR" }, + { TBT0BAR, TBT0_BASE_ADDRESS, TBT0_BASE_SIZE, "TBT0BAR" }, + { TBT1BAR, TBT1_BASE_ADDRESS, TBT1_BASE_SIZE, "TBT1BAR" }, + { TBT2BAR, TBT2_BASE_ADDRESS, TBT2_BASE_SIZE, "TBT2BAR" }, + { TBT3BAR, TBT3_BASE_ADDRESS, TBT3_BASE_SIZE, "TBT3BAR" }, + { VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" }, +}; + +#define V_P2SB_CFG_IBDF_BUS 0 +#define V_P2SB_CFG_IBDF_DEV 30 +#define V_P2SB_CFG_IBDF_FUNC 7 +#define V_P2SB_CFG_HBDF_BUS 0 +#define V_P2SB_CFG_HBDF_DEV 30 +#define V_P2SB_CFG_HBDF_FUNC 6 + +#endif diff --git a/src/soc/intel/alderlake/romstage/Makefile.inc b/src/soc/intel/alderlake/romstage/Makefile.inc new file mode 100644 index 0000000..a1a6c66 --- /dev/null +++ b/src/soc/intel/alderlake/romstage/Makefile.inc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + +romstage-y += fsp_params.c +romstage-y += ../../../../cpu/intel/car/romstage.c +romstage-y += romstage.c +romstage-y += pch.c +romstage-y += systemagent.c diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c new file mode 100644 index 0000000..6624a19 --- /dev/null +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -0,0 +1,174 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <device/device.h> +#include <fsp/util.h> +#include <intelblocks/cpulib.h> +#include <intelblocks/mp_init.h> +#include <soc/gpio_soc_defs.h> +#include <soc/iomap.h> +#include <soc/msr.h> +#include <soc/pci_devs.h> +#include <soc/romstage.h> +#include <soc/soc_chip.h> +#include <string.h> + +static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_alderlake_dev_config *config) +{ + unsigned int i; + uint32_t mask = 0; + const struct device *dev; + + /* + * If IGD is enabled, set IGD stolen size to 60MB. + * Otherwise, skip IGD init in FSP. + */ + dev = pcidev_path_on_root(SA_DEVFN_IGD); + m_cfg->InternalGfx = is_dev_enabled(dev); + m_cfg->IgdDvmt50PreAlloc = m_cfg->InternalGfx ? 0xFE : 0; + + m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; + m_cfg->SaGv = config->SaGv; + m_cfg->UserBd = BOARD_TYPE_ULT_ULX; + m_cfg->RMT = config->RMT; + + /* CpuRatio Settings */ + if (config->cpu_ratio_override) { + m_cfg->CpuRatio = config->cpu_ratio_override; + } else { + /* Set CpuRatio to match existing MSR value */ + msr_t flex_ratio; + flex_ratio = rdmsr(MSR_FLEX_RATIO); + m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; + } + + for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { + if (config->PcieRpEnable[i]) + mask |= (1 << i); + } + m_cfg->PcieRpEnableMask = mask; + + memcpy(m_cfg->PcieClkSrcUsage, config->PcieClkSrcUsage, + sizeof(config->PcieClkSrcUsage)); + + memcpy(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq, + sizeof(config->PcieClkSrcClkReq)); + + m_cfg->PrmrrSize = get_prmrr_size(); + m_cfg->EnableC6Dram = config->enable_c6dram; + /* Disable BIOS Guard */ + m_cfg->BiosGuard = 0; + + /* UART Debug Log */ + m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ? + DEBUG_INTERFACE_UART_8250IO : DEBUG_INTERFACE_LPSS_SERIAL_IO; + if (CONFIG(DRIVERS_UART_8250IO)) + m_cfg->PcdIsaSerialUartBase = 0x0; + m_cfg->SerialIoUartDebugMode = PchSerialIoSkipInit; + m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; + + /* DP port config */ + m_cfg->DdiPortAConfig = config->DdiPortAConfig; + m_cfg->DdiPortBConfig = config->DdiPortBConfig; + m_cfg->DdiPortAHpd = config->DdiPortAHpd; + m_cfg->DdiPortBHpd = config->DdiPortBHpd; + m_cfg->DdiPortCHpd = config->DdiPortCHpd; + m_cfg->DdiPort1Hpd = config->DdiPort1Hpd; + m_cfg->DdiPort2Hpd = config->DdiPort2Hpd; + m_cfg->DdiPort3Hpd = config->DdiPort3Hpd; + m_cfg->DdiPort4Hpd = config->DdiPort4Hpd; + m_cfg->DdiPortADdc = config->DdiPortADdc; + m_cfg->DdiPortBDdc = config->DdiPortBDdc; + m_cfg->DdiPortCDdc = config->DdiPortCDdc; + m_cfg->DdiPort1Ddc = config->DdiPort1Ddc; + m_cfg->DdiPort2Ddc = config->DdiPort2Ddc; + m_cfg->DdiPort3Ddc = config->DdiPort3Ddc; + m_cfg->DdiPort4Ddc = config->DdiPort4Ddc; + + /* Image clock: disable all clocks for bypassing FSP pin mux */ + memset(m_cfg->ImguClkOutEn, 0, sizeof(m_cfg->ImguClkOutEn)); + + /* Enable Hyper Threading */ + m_cfg->HyperThreading = 1; + /* Disable Lock PCU Thermal Management registers */ + m_cfg->LockPTMregs = 0; + /* Channel Hash Mask:0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum) */ + m_cfg->ChHashMask = 0x30CC; + /* Enable SMBus controller based on config */ + m_cfg->SmbusEnable = config->SmbusEnable; + /* Set debug probe type */ + m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ALDERLAKE_DEBUG_CONSENT; + + /* Audio: HDAUDIO_LINK_MODE I2S/SNDW */ + m_cfg->PchHdaDspEnable = config->PchHdaDspEnable; + m_cfg->PchHdaAudioLinkHdaEnable = config->PchHdaAudioLinkHdaEnable; + memcpy(m_cfg->PchHdaAudioLinkDmicEnable, config->PchHdaAudioLinkDmicEnable, + sizeof(m_cfg->PchHdaAudioLinkDmicEnable)); + memcpy(m_cfg->PchHdaAudioLinkSspEnable, config->PchHdaAudioLinkSspEnable, + sizeof(m_cfg->PchHdaAudioLinkSspEnable)); + memcpy(m_cfg->PchHdaAudioLinkSndwEnable, config->PchHdaAudioLinkSndwEnable, + sizeof(m_cfg->PchHdaAudioLinkSndwEnable)); + m_cfg->PchHdaIDispLinkTmode = config->PchHdaIDispLinkTmode; + m_cfg->PchHdaIDispLinkFrequency = config->PchHdaIDispLinkFrequency; + m_cfg->PchHdaIDispCodecDisconnect = config->PchHdaIDispCodecDisconnect; + + /* ISH */ + dev = pcidev_path_on_root(PCH_DEVFN_ISH); + m_cfg->PchIshEnable = is_dev_enabled(dev); + + /* Tcss USB */ + m_cfg->TcssXhciEn = config->TcssXhciEn; + m_cfg->TcssXdciEn = config->TcssXdciEn; + + /* TCSS DMA */ + dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA0); + m_cfg->TcssDma0En = is_dev_enabled(dev); + + dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA1); + m_cfg->TcssDma1En = is_dev_enabled(dev); + + /* USB4/TBT */ + dev = pcidev_path_on_root(SA_DEVFN_TBT0); + m_cfg->TcssItbtPcie0En = is_dev_enabled(dev); + + dev = pcidev_path_on_root(SA_DEVFN_TBT1); + m_cfg->TcssItbtPcie1En = is_dev_enabled(dev); + + dev = pcidev_path_on_root(SA_DEVFN_TBT2); + m_cfg->TcssItbtPcie2En = is_dev_enabled(dev); + + dev = pcidev_path_on_root(SA_DEVFN_TBT3); + m_cfg->TcssItbtPcie3En = is_dev_enabled(dev); + + /* Vt-D config */ + /* Disable VT-d support for pre-QS platform */ + m_cfg->VtdDisable = 1; + + /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ + m_cfg->VmxEnable = CONFIG(ENABLE_VMX); + /* Skip CPU replacement check */ + m_cfg->SkipCpuReplacementCheck = !config->CpuReplacementCheck; + + /* Skip CPU side PCIe enablement in FSP if device is disabled in devicetree */ + dev = pcidev_path_on_root(SA_DEVFN_CPU_PCIE); + m_cfg->CpuPcieRpEnableMask = dev && dev->enabled; +} + +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) +{ + const struct soc_intel_alderlake_dev_config *config; + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + + config = config_of_soc(); + + soc_memory_init_params(m_cfg, config); + mainboard_memory_init_params(mupd); +} + +__weak void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} diff --git a/src/soc/intel/alderlake/romstage/pch.c b/src/soc/intel/alderlake/romstage/pch.c new file mode 100644 index 0000000..d3c2554 --- /dev/null +++ b/src/soc/intel/alderlake/romstage/pch.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <intelblocks/smbus.h> +#include <soc/romstage.h> + +void romstage_pch_init(void) +{ + /* Program SMBUS_BASE_ADDRESS and Enable it */ + smbus_common_init(); +} diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c new file mode 100644 index 0000000..db014ea --- /dev/null +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -0,0 +1,143 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/romstage.h> +#include <cbmem.h> +#include <console/console.h> +#include <fsp/util.h> +#include <intelblocks/cfg.h> +#include <intelblocks/cse.h> +#include <intelblocks/pmclib.h> +#include <memory_info.h> +#include <soc/intel/common/smbios.h> +#include <soc/iomap.h> +#include <soc/pm.h> +#include <soc/romstage.h> +#include <soc/soc_chip.h> +#include <string.h> + +#define FSP_SMBIOS_MEMORY_INFO_GUID \ +{ \ + 0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \ + 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ +} + +bool __weak mainboard_get_dram_part_num(const char **part_num, size_t *len) +{ + /* Default weak implementation, no need to override part number. */ + return false; +} + +/* Save the DIMM information for SMBIOS table 17 */ +static void save_dimm_info(void) +{ + int node, channel, dimm, dimm_max, index; + size_t hob_size; + const CONTROLLER_INFO *ctrlr_info; + const CHANNEL_INFO *channel_info; + const DIMM_INFO *src_dimm; + struct dimm_info *dest_dimm; + struct memory_info *mem_info; + const MEMORY_INFO_DATA_HOB *meminfo_hob; + const uint8_t smbios_memory_info_guid[16] = + FSP_SMBIOS_MEMORY_INFO_GUID; + const uint8_t *serial_num; + const char *dram_part_num = NULL; + size_t dram_part_num_len; + bool is_dram_part_overridden = false; + + /* Locate the memory info HOB, presence validated by raminit */ + meminfo_hob = fsp_find_extension_hob_by_guid( + smbios_memory_info_guid, + &hob_size); + if (meminfo_hob == NULL || hob_size == 0) { + printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n"); + return; + } + + /* + * Allocate CBMEM area for DIMM information used to populate SMBIOS + * table 17 + */ + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); + if (mem_info == NULL) { + printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n"); + return; + } + memset(mem_info, 0, sizeof(*mem_info)); + + /* Allow mainboard to override DRAM part number. */ + is_dram_part_overridden = mainboard_get_dram_part_num(&dram_part_num, + &dram_part_num_len); + + /* Save available DIMM information */ + index = 0; + dimm_max = ARRAY_SIZE(mem_info->dimm); + for (node = 0; node < MAX_NODE; node++) { + ctrlr_info = &meminfo_hob->Controller[node]; + for (channel = 0; channel < MAX_CH && index < dimm_max; + channel++) { + channel_info = &ctrlr_info->ChannelInfo[channel]; + if (channel_info->Status != CHANNEL_PRESENT) + continue; + + for (dimm = 0; dimm < MAX_DIMM && index < dimm_max; + dimm++) { + src_dimm = &channel_info->DimmInfo[dimm]; + dest_dimm = &mem_info->dimm[index]; + if (src_dimm->Status != DIMM_PRESENT) + continue; + + /* If there is no DRAM part number overridden by + * mainboard then use original one. */ + if (!is_dram_part_overridden) { + dram_part_num_len = sizeof(src_dimm->ModulePartNum); + dram_part_num = (const char *) + &src_dimm->ModulePartNum[0]; + } + + u8 memProfNum = meminfo_hob->MemoryProfile; + serial_num = src_dimm->SpdSave + + SPD_SAVE_OFFSET_SERIAL; + + /* Populate the DIMM information */ + dimm_info_fill(dest_dimm, + src_dimm->DimmCapacity, + meminfo_hob->MemoryType, + meminfo_hob->ConfiguredMemoryClockSpeed, + src_dimm->RankInDimm, + channel_info->ChannelId, + src_dimm->DimmId, + dram_part_num, + dram_part_num_len, + serial_num, + meminfo_hob->DataWidth, + meminfo_hob->VddVoltage[memProfNum], + meminfo_hob->EccSupport, + src_dimm->MfgId, + src_dimm->SpdModuleType); + index++; + } + } + } + mem_info->dimm_cnt = index; + printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); +} + +void mainboard_romstage_entry(void) +{ + bool s3wake; + struct chipset_power_state *ps = pmc_get_power_state(); + + /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ + systemagent_early_init(); + /* Program PCH init */ + romstage_pch_init(); + /* initialize Heci interface */ + heci_init(HECI1_BASE_ADDRESS); + + s3wake = pmc_fill_power_state(ps) == ACPI_S3; + fsp_memory_init(s3wake); + pmc_set_disb(); + if (!s3wake) + save_dimm_info(); +} diff --git a/src/soc/intel/alderlake/romstage/systemagent.c b/src/soc/intel/alderlake/romstage/systemagent.c new file mode 100644 index 0000000..150ffb5 --- /dev/null +++ b/src/soc/intel/alderlake/romstage/systemagent.c @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on Intel Alder Lake Processor SA Datasheet + * Document number: 619503 + * Chapter number: 3 + */ + +#include <intelblocks/systemagent.h> +#include <soc/iomap.h> +#include <soc/romstage.h> +#include <soc/systemagent.h> + +void systemagent_early_init(void) +{ + static const struct sa_mmio_descriptor soc_fixed_pci_resources[] = { + { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, + { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, + { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" }, + }; + + static const struct sa_mmio_descriptor soc_fixed_mch_resources[] = { + { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" }, + { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" }, + }; + + /* Set Fixed MMIO address into PCI configuration space */ + sa_set_pci_bar(soc_fixed_pci_resources, + ARRAY_SIZE(soc_fixed_pci_resources)); + /* Set Fixed MMIO address into MCH base address */ + sa_set_mch_bar(soc_fixed_mch_resources, + ARRAY_SIZE(soc_fixed_mch_resources)); + /* Enable PAM registers */ + enable_pam_region(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/45192 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4473aed27363c22e92e66cc6770cb55aae83e75c Gerrit-Change-Number: 45192 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

5 27

Change in coreboot[master]: /src/acpi: Correct sizes for ACPI data fields
by Jason Glenesk (Code Review) 15 Sep '20

15 Sep '20

Hello Jason Glenesk, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45339 to review the following change. Change subject: /src/acpi: Correct sizes for ACPI data fields ...................................................................... /src/acpi: Correct sizes for ACPI data fields Correct sizes of Count, Type, and Latency data field in _CST object to integer, byte, word, respectively. Correct size of NumEntries data field in _CSD object to integer. BUG=b:155307433 TEST=Boot Morphius and dump SSDT _CST and _CSD objects. Confirm that sizes written conform to ACPI_6_3_May16.pdf ACPI specification. BRANCH=Zork Change-Id: I356b46f2fa787e18442a66280b6545a3b525a08b Signed-off-by: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> --- M src/acpi/acpigen.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/45339/1 diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index 44f9106..7910cbc 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -850,8 +850,8 @@ { acpigen_write_package(4); acpigen_write_register_resource(&cstate->resource); - acpigen_write_dword(cstate->ctype); - acpigen_write_dword(cstate->latency); + acpigen_write_byte(cstate->ctype); + acpigen_write_word(cstate->latency); acpigen_write_dword(cstate->power); acpigen_pop_len(); } @@ -861,7 +861,7 @@ int i; acpigen_write_name("_CST"); acpigen_write_package(nentries+1); - acpigen_write_dword(nentries); + acpigen_write_integer(nentries); for (i = 0; i < nentries; i++) acpigen_write_CST_package_entry(cstate + i); @@ -875,7 +875,7 @@ acpigen_write_name("_CSD"); acpigen_write_package(1); acpigen_write_package(6); - acpigen_write_byte(6); // 6 values + acpigen_write_integer(6); // 6 values acpigen_write_byte(0); // revision 0 acpigen_write_dword(domain); acpigen_write_dword(coordtype); -- To view, visit https://review.coreboot.org/c/coreboot/+/45339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I356b46f2fa787e18442a66280b6545a3b525a08b Gerrit-Change-Number: 45339 Gerrit-PatchSet: 1 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

6 10

Change in coreboot[master]: soc/intel/fsp_baytrail: using designware I2C driver
by uwe taz (Code Review) 15 Sep '20

15 Sep '20

uwe taz has removed Werner Zeh from this change. ( https://review.coreboot.org/c/coreboot/+/33021 ) Change subject: soc/intel/fsp_baytrail: using designware I2C driver ...................................................................... Removed reviewer Werner Zeh with the following votes: * Code-Review+1 by Werner Zeh <werner.zeh(a)siemens.com> -- To view, visit https://review.coreboot.org/c/coreboot/+/33021 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f447007320b4adec774778f3f3d1d21a86175be Gerrit-Change-Number: 33021 Gerrit-PatchSet: 2 Gerrit-Owner: uwe taz Gerrit-Reviewer: Name of user not set #1003096 Gerrit-Reviewer: uwe taz Gerrit-MessageType: deleteReviewer

1 0

Change in coreboot[master]: mb/lenovo/x60: Enable TPM
by Masanori Ogino (Code Review) 15 Sep '20

15 Sep '20

Masanori Ogino has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/13410 ) Change subject: mb/lenovo/x60: Enable TPM ...................................................................... Patch Set 10: For reference, I use the following script to collect some data: #!/bin/sh # Extract the last component of coreboot version string. # ex1. coreboot-4.12-2704-g1ba86f685b -> g1ba86f685b # ex2. coreboot-4.12-2704-g1ba86f685b-wip -> wip tag=$(cbmem -1 | head | grep '^coreboot' | cut -d' ' -f1 | awk '{ cnt = split($0, arr, "-"); print arr[cnt] }') rev=$(uname -r) echo "Gathering information on ${tag} with Linux ${rev}..." echo datadir="${HOME}/data/${tag}-${rev}" mkdir -p "${datadir}" echo "ACPI:" acpidump > "${datadir}/acpidump.txt" cat /sys/firmware/acpi/tables/DSDT > "${datadir}/dsdt.dat" cat /sys/firmware/acpi/tables/SSDT > "${datadir}/ssdt.dat" echo echo "dmesg before modprobe:" dmesg | grep -i tpm | tee "${datadir}/dmesg.log" echo echo "modprobe tpm_tis force=1..." modprobe -r tpm_tis modprobe tpm_tis force=1 echo echo "dmesg after modprobe:" dmesg | grep -i tpm | tee "${datadir}/dmesg.force.log" echo if [ -d "/sys/class/tpm/tpm0" ]; then echo "tpm0 found on sysfs" echo echo "/sys/class/tpm/tpm0/caps:" cat /sys/class/tpm/tpm0/caps | tee "${datadir}/tpm.caps.log" echo echo "/sys/class/tpm/tpm0/durations:" cat /sys/class/tpm/tpm0/durations | tee "${datadir}/tpm.durations.log" echo echo "/sys/class/tpm/tpm0/timeouts:" cat /sys/class/tpm/tpm0/timeouts | tee "${datadir}/tpm.timeouts.log" else echo "tpm0 not found" fi echo echo "done." -- To view, visit https://review.coreboot.org/c/coreboot/+/13410 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e65b37507c111af1c0c56822327d5497f58f085 Gerrit-Change-Number: 13410 Gerrit-PatchSet: 10 Gerrit-Owner: Denis Carikli <GNUtoo(a)no-log.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Denis 'GNUtoo' Carikli <GNUtoo(a)cyberdimension.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Masanori Ogino <mogino(a)acm.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 15 Sep 2020 11:47:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: security/tpm/tss/tcg-2.0: add const to marshalling functions
by Caveh Jalali (Code Review) 15 Sep '20

15 Sep '20

Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45409 ) Change subject: security/tpm/tss/tcg-2.0: add const to marshalling functions ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/45409 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I099bf46c928733aff2c1d1c134deec35da6309ba Gerrit-Change-Number: 45409 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 15 Sep 2020 11:00:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel: cnl,icl,elh,jsl,tgl: enable C6DRAM
by Michael Niewöhner (Code Review) 15 Sep '20

15 Sep '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45417 ) Change subject: soc/intel: cnl,icl,elh,jsl,tgl: enable C6DRAM ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/45417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I556dba59bc06c9101bdfdfd6aee00610aac516e3 Gerrit-Change-Number: 45417 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Tue, 15 Sep 2020 10:52:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel: rename get_prmrr_size
by Michael Niewöhner (Code Review) 15 Sep '20

15 Sep '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45414 ) Change subject: soc/intel: rename get_prmrr_size ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/45414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id243be50acb741f2c3118ddde082743d08983a53 Gerrit-Change-Number: 45414 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph Gerrit-Comment-Date: Tue, 15 Sep 2020 10:24:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit September 2020