coreboot-gerrit September 2020

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Change in coreboot[master]: drivers/spi/tpm: Improve error checking
by Jes Klinke (Code Review) 14 Sep '20

14 Sep '20

Jes Klinke has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45232 ) Change subject: drivers/spi/tpm: Improve error checking ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8a1202000abce1857ee694b06b1478e6b045069 Gerrit-Change-Number: 45232 Gerrit-PatchSet: 3 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 14 Sep 2020 15:39:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block: Use pci_dev_request_bus_master for BM enabling
by Subrata Banik (Code Review) 14 Sep '20

14 Sep '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45320 ) Change subject: soc/intel/common/block: Use pci_dev_request_bus_master for BM enabling ...................................................................... soc/intel/common/block: Use pci_dev_request_bus_master for BM enabling Replace static sata_final() implementation for BM enabling with generic pci_dev_request_bus_master() function. TEST=Able to boot to OS from sata device on CML platform. Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Change-Id: Icd086184fd6fa9c03c806c857f13fad5a9e78a3e --- M src/soc/intel/common/block/sata/sata.c 1 file changed, 1 insertion(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/45320/1 diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c index 1889700..7b234a9 100644 --- a/src/soc/intel/common/block/sata/sata.c +++ b/src/soc/intel/common/block/sata/sata.c @@ -4,17 +4,11 @@ #include <device/pci.h> #include <device/pci_ids.h> -static void sata_final(struct device *dev) -{ - /* Set Bus Master */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); -} - static struct device_operations sata_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .final = sata_final, + .final = pci_dev_request_bus_master, .ops_pci = &pci_dev_ops_pci, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/45320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd086184fd6fa9c03c806c857f13fad5a9e78a3e Gerrit-Change-Number: 45320 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/cbfstool: extend includes in commonlib
by Idwer Vollering (Code Review) 14 Sep '20

14 Sep '20

Idwer Vollering has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38648 ) Change subject: util/cbfstool: extend includes in commonlib ...................................................................... util/cbfstool: extend includes in commonlib Certain non-Linux OSes require an include file in different places. Build tested on Linux, FreeBSD. Change-Id: Icd81c2a96c608589ce2ec8f4b883fd4e584776b1 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- M src/commonlib/bsd/lz4_wrapper.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38648/1 diff --git a/src/commonlib/bsd/lz4_wrapper.c b/src/commonlib/bsd/lz4_wrapper.c index 2367afc..d07fc98 100644 --- a/src/commonlib/bsd/lz4_wrapper.c +++ b/src/commonlib/bsd/lz4_wrapper.c @@ -2,7 +2,11 @@ #include <commonlib/bsd/compression.h> #include <commonlib/bsd/helpers.h> +#if defined(__FreeBSD__) +#include <sys/endian.h> +#else #include <endian.h> +#endif #include <stdint.h> #include <string.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/38648 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd81c2a96c608589ce2ec8f4b883fd4e584776b1 Gerrit-Change-Number: 38648 Gerrit-PatchSet: 1 Gerrit-Owner: Idwer Vollering <vidwer(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Move sd_emmc_config into emmc_config struct
by Raul Rangel (Code Review) 14 Sep '20

14 Sep '20

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45095 ) Change subject: soc/amd/picasso: Move sd_emmc_config into emmc_config struct ...................................................................... soc/amd/picasso: Move sd_emmc_config into emmc_config struct I plan on adding another eMMC parameter. This refactor keeps the config contained in a single struct. BUG=b:159823235 TEST=Build test Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I4b57d651ab44d6c1cad661d620bffd4207dfebd4 --- M src/mainboard/amd/mandolin/mainboard.c M src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb M src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb M src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb M src/mainboard/google/zork/variants/dalboz/variant.c M src/mainboard/google/zork/variants/ezkinil/variant.c M src/soc/amd/picasso/chip.h M src/soc/amd/picasso/fsp_params.c 8 files changed, 42 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/45095/1 diff --git a/src/mainboard/amd/mandolin/mainboard.c b/src/mainboard/amd/mandolin/mainboard.c index c22ed34..247616c 100644 --- a/src/mainboard/amd/mandolin/mainboard.c +++ b/src/mainboard/amd/mandolin/mainboard.c @@ -112,7 +112,7 @@ struct soc_amd_picasso_config *cfg = config_of_soc(); if (!CONFIG(PICASSO_LPC_IOMUX)) - cfg->sd_emmc_config = SD_EMMC_EMMC_HS400; + cfg->emmc_config.timing = SD_EMMC_EMMC_HS400; mainboard_program_gpios(); diff --git a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb index c603130..7ccec27 100644 --- a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb @@ -7,7 +7,9 @@ register "fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042" register "fadt_flags" = "ACPI_FADT_SLEEP_BUTTON" # See table 5-34 ACPI 6.3 spec - register "sd_emmc_config" = "SD_EMMC_DISABLE" + register "emmc_config" = "{ + .timing = SD_EMMC_DISABLE, + }" register "has_usb2_phy_tune_params" = "1" diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index 42219d7..4edbfa4 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -40,7 +40,9 @@ # End : OPN Performance Configuration - register "sd_emmc_config" = "SD_EMMC_EMMC_HS400" + register "emmc_config" = "{ + .timing = SD_EMMC_EMMC_HS400, + }" register "xhci0_force_gen1" = "0" diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index 1620643..05bee6b 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -40,7 +40,9 @@ # End : OPN Performance Configuration - register "sd_emmc_config" = "SD_EMMC_EMMC_HS400" + register "emmc_config" = "{ + .timing = SD_EMMC_EMMC_HS400, + }" register "xhci0_force_gen1" = "0" diff --git a/src/mainboard/google/zork/variants/dalboz/variant.c b/src/mainboard/google/zork/variants/dalboz/variant.c index 5138782..21aaec8 100644 --- a/src/mainboard/google/zork/variants/dalboz/variant.c +++ b/src/mainboard/google/zork/variants/dalboz/variant.c @@ -134,10 +134,10 @@ * So we keep the speed low here, with the intent that * other variants implement these corrections. */ - cfg->sd_emmc_config = SD_EMMC_EMMC_HS200; + cfg->emmc_config.timing = SD_EMMC_EMMC_HS200; } } else { - cfg->sd_emmc_config = SD_EMMC_DISABLE; + cfg->emmc_config.timing = SD_EMMC_DISABLE; } update_audio_configuration(); diff --git a/src/mainboard/google/zork/variants/ezkinil/variant.c b/src/mainboard/google/zork/variants/ezkinil/variant.c index 29a50bc..f76ab62 100644 --- a/src/mainboard/google/zork/variants/ezkinil/variant.c +++ b/src/mainboard/google/zork/variants/ezkinil/variant.c @@ -15,5 +15,5 @@ * Enable eMMC if eMMC bit is set in FW_CONFIG or device is unprovisioned. */ if (!(variant_has_emmc() || boot_is_factory_unprovisioned())) - cfg->sd_emmc_config = SD_EMMC_DISABLE; + cfg->emmc_config.timing = SD_EMMC_DISABLE; } diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index ac1a12c..efac418 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -126,20 +126,34 @@ uint32_t telemetry_vddcr_soc_slope; uint32_t telemetry_vddcr_soc_offset; - enum { - SD_EMMC_DISABLE, - SD_EMMC_SD_LOW_SPEED, - SD_EMMC_SD_HIGH_SPEED, - SD_EMMC_SD_UHS_I_SDR_50, - SD_EMMC_SD_UHS_I_DDR_50, - SD_EMMC_SD_UHS_I_SDR_104, - SD_EMMC_EMMC_SDR_26, - SD_EMMC_EMMC_SDR_52, - SD_EMMC_EMMC_DDR_52, - SD_EMMC_EMMC_HS200, - SD_EMMC_EMMC_HS400, - SD_EMMC_EMMC_HS300, - } sd_emmc_config; + struct { + /* + * SDHCI doesn't directly support eMMC. There is an implicit mapping between + * eMMC timing modes and SDHCI UHS-I timing modes defined in the linux + * kernel. + * + * HS -> UHS_SDR12 (0x00) + * DDR52 -> UHS_DDR50 (0x04) + * HS200 -> UHS_SDR104 (0x03) + * HS400 -> NONE (0x05) + * + * The kernel driver uses a heuristic to determine if HS400 is supported. + */ + enum { + SD_EMMC_DISABLE, + SD_EMMC_SD_LOW_SPEED, + SD_EMMC_SD_HIGH_SPEED, + SD_EMMC_SD_UHS_I_SDR_50, + SD_EMMC_SD_UHS_I_DDR_50, + SD_EMMC_SD_UHS_I_SDR_104, + SD_EMMC_EMMC_SDR_26, + SD_EMMC_EMMC_SDR_52, + SD_EMMC_EMMC_DDR_52, + SD_EMMC_EMMC_HS200, + SD_EMMC_EMMC_HS400, + SD_EMMC_EMMC_HS300, + } timing; + } emmc_config; uint8_t xhci0_force_gen1; diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c index 1dbb8e5..1e4f2a5 100644 --- a/src/soc/amd/picasso/fsp_params.c +++ b/src/soc/amd/picasso/fsp_params.c @@ -12,7 +12,7 @@ { int val = SD_DISABLE; - switch (cfg->sd_emmc_config) { + switch (cfg->emmc_config.timing) { case SD_EMMC_DISABLE: val = SD_DISABLE; break; -- To view, visit https://review.coreboot.org/c/coreboot/+/45095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b57d651ab44d6c1cad661d620bffd4207dfebd4 Gerrit-Change-Number: 45095 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/octopus/variants/fleex: Add G2Touch touchscreen support
by John Su (Code Review) 14 Sep '20

14 Sep '20

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44980 ) Change subject: mb/google/octopus/variants/fleex: Add G2Touch touchscreen support ...................................................................... mb/google/octopus/variants/fleex: Add G2Touch touchscreen support BUG=b:167297664 TEST=build fleex, and check touchscreen can work Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Change-Id: I910681c258ff5487830e795a8bd08c66be69b1d4 --- M src/mainboard/google/octopus/variants/fleex/overridetree.cb 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/44980/1 diff --git a/src/mainboard/google/octopus/variants/fleex/overridetree.cb b/src/mainboard/google/octopus/variants/fleex/overridetree.cb index 1d1a67a..0b81752 100644 --- a/src/mainboard/google/octopus/variants/fleex/overridetree.cb +++ b/src/mainboard/google/octopus/variants/fleex/overridetree.cb @@ -156,6 +156,20 @@ register "hid_desc_reg_offset" = "0x20" device i2c 2c on end end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7503"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "generic.reset_delay_ms" = "50" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end end # - I2C 7 end -- To view, visit https://review.coreboot.org/c/coreboot/+/44980 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I910681c258ff5487830e795a8bd08c66be69b1d4 Gerrit-Change-Number: 44980 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: copy local info to transfer buf
by Kangheui Won (Code Review) 14 Sep '20

14 Sep '20

Kangheui Won has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44751 ) Change subject: soc/amd/picasso: copy local info to transfer buf ...................................................................... soc/amd/picasso: copy local info to transfer buf buffer_info is local variable, we need to copy it to _transfer_buffer before we hand it over to PSP. BUG=b:159220781 TEST=check transfer_info_struct is correctly populated on romstage Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: I14bc34e6af501240a6f633db3999a7759e88d60b --- M src/soc/amd/picasso/psp_verstage/psp_verstage.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/44751/1 diff --git a/src/soc/amd/picasso/psp_verstage/psp_verstage.c b/src/soc/amd/picasso/psp_verstage/psp_verstage.c index 005c8b0..ef4884f 100644 --- a/src/soc/amd/picasso/psp_verstage/psp_verstage.c +++ b/src/soc/amd/picasso/psp_verstage/psp_verstage.c @@ -186,6 +186,8 @@ buffer_info.workbuf_offset = (uint32_t)((uintptr_t)_fmap_cache - (uintptr_t)_vboot2_work); + memcpy(_transfer_buffer, &buffer_info, sizeof(buffer_info)); + retval = svc_save_uapp_data(UAPP_COPYBUF_CHROME_WORKBUF, (void *)_transfer_buffer, buffer_size); if (retval) { -- To view, visit https://review.coreboot.org/c/coreboot/+/44751 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14bc34e6af501240a6f633db3999a7759e88d60b Gerrit-Change-Number: 44751 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/boten: Add audio configuration
by 9elements QA (Code Review) 14 Sep '20

14 Sep '20

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44920 ) Change subject: mb/google/dedede/var/boten: Add audio configuration ...................................................................... Patch Set 4: Automatic boot test returned (PASS/FAIL/TOTAL): 8/1/9 "QEMU x86 q35/ich9" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/19166 "QEMU x86 q35/ich9" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/19165 "QEMU x86 i440fx/piix4" (x86_64) using payload SeaBIOS : FAIL : https://lava.9esec.io/r/19164 "QEMU x86 i440fx/piix4" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/19163 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/19162 "HP Z220 SFF Workstation" (x86_32) using payload LinuxBoot_BusyBox_kexec : SUCCESS : https://lava.9esec.io/r/19170 "HP Z220 SFF Workstation" (x86_32) using payload LinuxBoot_BusyBox_kexec : SUCCESS : https://lava.9esec.io/r/19169 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/19168 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/19167 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/44920 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I835db854543e6282c102c86a7073b432fd89d0a5 Gerrit-Change-Number: 44920 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Ben Zhang <benzh(a)google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 14 Sep 2020 12:48:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: include/superio/hwm5_conf.h: Fix copy-pasted comments
by Angel Pons (Code Review) 14 Sep '20

14 Sep '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45226 ) Change subject: include/superio/hwm5_conf.h: Fix copy-pasted comments ...................................................................... include/superio/hwm5_conf.h: Fix copy-pasted comments Comments say `port, but the actual function signature uses `base`. Change-Id: I28a2f24a9701aec2fb990ca2f38e5f2794e15f0c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/include/superio/hwm5_conf.h 1 file changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/45226/1 diff --git a/src/include/superio/hwm5_conf.h b/src/include/superio/hwm5_conf.h index 9102de2..2cf13c6 100644 --- a/src/include/superio/hwm5_conf.h +++ b/src/include/superio/hwm5_conf.h @@ -12,14 +12,14 @@ * of the corresponding IO address region, but at offset 5 and 6. */ /* - * u8 pnp_read_hwm5_index(u16 port, u8 reg) + * u8 pnp_read_hwm5_index(u16 base, u8 reg) * Description: * This routine reads indexed I/O registers. The reg byte is written - * to the index register at I/O address = port + 5. The result is then - * read from the data register at I/O address = port + 6. + * to the index register at I/O address = base + 5. The result is then + * read from the data register at I/O address = base + 6. * * Parameters: - * @param[in] u16 base = The I/O address of the port index register. + * @param[in] u16 base = The I/O address of the base index register. * @param[in] u8 reg = The offset within the indexed space. * @param[out] u8 result = The value read back from the data register. */ @@ -29,14 +29,14 @@ } /* - * void pnp_write_hwm5_index(u16 port, u8 reg, u8 value) + * void pnp_write_hwm5_index(u16 base, u8 reg, u8 value) * Description: * This routine writes indexed I/O registers. The reg byte is written - * to the index register at I/O address = port + 5. The value byte is then - * written to the data register at I/O address = port + 6. + * to the index register at I/O address = base + 5. The value byte is then + * written to the data register at I/O address = base + 6. * * Parameters: - * @param[in] u16 base = The address of the port index register. + * @param[in] u16 base = The address of the base index register. * @param[in] u8 reg = The offset within the indexed space. * @param[in] u8 value = The value to be written to the data register. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45226 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28a2f24a9701aec2fb990ca2f38e5f2794e15f0c Gerrit-Change-Number: 45226 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/{cnl,icl,jsl,tgl}: Clean up chip.h
by Subrata Banik (Code Review) 14 Sep '20

14 Sep '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45322 ) Change subject: soc/intel/{cnl,icl,jsl,tgl}: Clean up chip.h ...................................................................... soc/intel/{cnl,icl,jsl,tgl}: Clean up chip.h Removed unused header files in chip.h Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Change-Id: Idb9b1ed23df3dbb9dad4d36651064c21a4d913fc --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/icelake/chip.h M src/soc/intel/jasperlake/chip.h M src/soc/intel/tigerlake/chip.h 4 files changed, 0 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/45322/1 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 9e7aa45..6a083c6 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -10,7 +10,6 @@ #include <intelblocks/lpc_lib.h> #include <intelblocks/power_limit.h> #include <stdint.h> -#include <soc/gpio.h> #include <soc/pch.h> #include <soc/pci_devs.h> #include <soc/pm.h> diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index 2b190cd..d60791b 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -9,7 +9,6 @@ #include <intelblocks/gspi.h> #include <stdint.h> #include <soc/gpe.h> -#include <soc/gpio.h> #include <soc/pch.h> #include <soc/gpio_defs.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 70fbbc3..3f0b910 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -9,8 +9,6 @@ #include <intelblocks/gspi.h> #include <intelblocks/power_limit.h> #include <soc/gpe.h> -#include <soc/gpio.h> -#include <soc/gpio_defs.h> #include <soc/pch.h> #include <soc/pci_devs.h> #include <soc/pmc.h> diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 2da63ed..dc8697b 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -9,8 +9,6 @@ #include <intelblocks/gspi.h> #include <intelblocks/power_limit.h> #include <soc/gpe.h> -#include <soc/gpio.h> -#include <soc/gpio_defs.h> #include <soc/pch.h> #include <soc/pci_devs.h> #include <soc/pmc.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/45322 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb9b1ed23df3dbb9dad4d36651064c21a4d913fc Gerrit-Change-Number: 45322 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP]arch/arm: Implement FIT support
by Arthur Heymans (Code Review) 14 Sep '20

14 Sep '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35410 ) Change subject: [WIP]arch/arm: Implement FIT support ...................................................................... [WIP]arch/arm: Implement FIT support Untested Change-Id: Ifae3cbae85bcd1c35f31278f76f4d97700979da3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M payloads/Kconfig M src/arch/arm/Makefile.inc A src/arch/arm/fit_payload.c 3 files changed, 152 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/35410/1 diff --git a/payloads/Kconfig b/payloads/Kconfig index 46cfaf5..04566cc 100644 --- a/payloads/Kconfig +++ b/payloads/Kconfig @@ -30,7 +30,7 @@ config PAYLOAD_FIT bool "A FIT payload" - depends on ARCH_ARM64 || ARCH_RISCV + depends on ARCH_ARM || ARCH_ARM64 || ARCH_RISCV select PAYLOAD_FIT_SUPPORT help Select this option if you have a payload image (a FIT file) which @@ -100,7 +100,7 @@ bool "FIT support" default n default y if PAYLOAD_LINUX && (ARCH_ARM || ARCH_ARM64 || ARCH_RISCV) - depends on ARCH_ARM64 || ARCH_RISCV + depends on ARCH_ARM || ARCH_ARM64 || ARCH_RISCV select FLATTENED_DEVICE_TREE help Select this option if your payload is of type FIT. diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc index 508b0a8..83c698a 100644 --- a/src/arch/arm/Makefile.inc +++ b/src/arch/arm/Makefile.inc @@ -131,6 +131,7 @@ ramstage-y += memcpy.S ramstage-y += memmove.S ramstage-y += clock.c +ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit_payload.c rmodules_arm-y += memset.S rmodules_arm-y += memcpy.S diff --git a/src/arch/arm/fit_payload.c b/src/arch/arm/fit_payload.c new file mode 100644 index 0000000..5792dfb --- /dev/null +++ b/src/arch/arm/fit_payload.c @@ -0,0 +1,149 @@ +/* + * Copyright 2013 Google Inc. + * Copyright 2018 Facebook, Inc. + * Copyright 2019 9elements Agency GmbH <patrick.rudolph(a)9elements.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <bootmem.h> +#include <stdlib.h> +#include <program_loading.h> +#include <string.h> +#include <commonlib/compression.h> +#include <commonlib/cbfs_serialized.h> +#include <lib.h> +#include <fit.h> +#include <endian.h> + +#define MAX_KERNEL_SIZE (64*MiB) +#define SECTION_ALIGN 64 + +static size_t get_kernel_size(const struct fit_image_node *node) +{ + /* + * Since we don't have a way to determine the uncompressed size of the + * kernel, we have to keep as much memory as possible free for use by + * the kernel immediately after the end of the kernel image. The amount + * of space required will vary depending on selected features, and is + * effectively unbound. + */ + + printk(BIOS_INFO, + "FIT: Leaving additional %u MiB of free space after kernel.\n", + MAX_KERNEL_SIZE >> 20); + + return node->size + MAX_KERNEL_SIZE; +} + +/** + * Place the region in free memory range. + * + * The caller has to set region->offset to the minimum allowed address. + */ +static bool fit_place_mem(const struct range_entry *r, void *arg) +{ + struct region *region = arg; + resource_t start; + + if (range_entry_tag(r) != BM_MEM_RAM) + return true; + + /* Section must be aligned at page boundary */ + start = ALIGN_UP(MAX(region->offset, range_entry_base(r)), SECTION_ALIGN); + + if (start + region->size < range_entry_end(r)) { + region->offset = (size_t)start; + return false; + } + + return true; +} + +static uint32_t arm_kernel_args[3]; + +bool fit_payload_arch(struct prog *payload, struct fit_config_node *config, + struct region *kernel, + struct region *fdt, + struct region *initrd) +{ + size_t lower_mem; + + if (!config->fdt || !fdt) { + printk(BIOS_CRIT, "CRIT: Providing a valid FDT is mandatory to " + "boot a RISC-V kernel!\n"); + return false; + /* TODO: Fall back to the ROM FDT? */ + } + + /* Update kernel size from image header, if possible */ + kernel->size = get_kernel_size(config->kernel); + printk(BIOS_DEBUG, "FIT: Using kernel size of 0x%zx bytes\n", + kernel->size); + + /* + * The code assumes that bootmem_walk provides a sorted list of memory + * regions, starting from the lowest address. + * The order of the calls here doesn't matter, as the placement is + * enforced in the called functions. + * For details check code on top. + */ + kernel->offset = 0; + if (!bootmem_walk(fit_place_mem, kernel)) + return false; + + /* + * The kernel documentation recommends place the image 32M above to avoid + * the need to relocate prior to compression. + */ + lower_mem = kernel->offset; + kernel->offset += 32 * MiB; + + /* Mark as reserved for future allocations. */ + bootmem_add_range(kernel->offset, kernel->size, BM_MEM_PAYLOAD); + + /* Place FDT and INITRD after kernel. */ + + /* Place INITRD and FDT: + * The Kernel documentation recommends the safe location of 128M above + * the start of ram to avoid being overwritten by the kernel + * decompressor. + */ + if (config->ramdisk) { + initrd->offset = lower_mem + 128 * MiB; + + if (!bootmem_walk(fit_place_mem, initrd)) + return false; + /* Mark as reserved for future allocations. */ + bootmem_add_range(initrd->offset, initrd->size, BM_MEM_PAYLOAD); + } + + /* Place FDT */ + fdt->offset = lower_mem + 128 * MiB; + + if (!bootmem_walk(fit_place_mem, fdt)) + return false; + /* Mark as reserved for future allocations. */ + bootmem_add_range(fdt->offset, fdt->size, BM_MEM_PAYLOAD); + + /* Kernel expects FDT as argument */ + arm_kernel_args[0] = 0; + /* All ones for FDT */ + arm_kernel_args[1] = ~0; + arm_kernel_args[2] = fdt->offset; + + prog_set_entry(payload, (void *)kernel->offset, (void *)arm_kernel_args); + + bootmem_dump_ranges(); + + return true; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/35410 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifae3cbae85bcd1c35f31278f76f4d97700979da3 Gerrit-Change-Number: 35410 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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