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Change in coreboot[master]: src/vendorcode/intel/fsp/fsp2_0/cpx-sp: add prev boot error info HOB ...
by Jonathan Zhang (Code Review) 14 Sep '20

14 Sep '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44973 ) Change subject: src/vendorcode/intel/fsp/fsp2_0/cpx-sp: add prev boot error info HOB header file ...................................................................... src/vendorcode/intel/fsp/fsp2_0/cpx-sp: add prev boot error info HOB header file PREV_BOOT_ERR_SRC_HOB is generated by CPX-SP FSP by interrogating error status registered (such as MCA MSRs) to list fatal errors happened during the previous boot session. The header file supports 3 different error source types. CPX-SP FSP supports only McBankType. Change-Id: I9b88af17075b98e88c7e94e55fea37627ec03cd0 Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> --- A src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_prevbooterr.h 1 file changed, 83 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/44973/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_prevbooterr.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_prevbooterr.h new file mode 100644 index 0000000..9241692 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_prevbooterr.h @@ -0,0 +1,83 @@ +/** +Copyright (c) 2019-2020, Intel Corporation. All rights reserved.<BR> + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + +**/ + + +#ifndef _PREV_BOOT_ERR_SRC_GUID_H_ +#define _PREV_BOOT_ERR_SRC_GUID_H_ + +#define FSP_PREV_BOOT_ERR_SRC_HOB_GUID { \ + 0xc5, 0xb5, 0x38, 0x51, 0x69, 0x93, 0xec, 0x48, 0x5b, 0x97, \ + 0x38, 0xa2, 0xf7, 0x09, 0x66, 0x75 \ + } + +#define PREV_BOOT_ERR_SRC_HOB_SIZE 1000 + +typedef struct { +UINT16 Length; // Actual size of the error sources used in the HOB +UINT8 HobData[PREV_BOOT_ERR_SRC_HOB_SIZE -2]; // List of Error source structures of format //MCBANK_ERR_INFO or CSR_ERR_INFO +}PREV_BOOT_ERR_SRC_HOB; + +typedef struct{ +UINT8 Type; // McBankType = 1; +UINT8 Segment; +UINT8 Socket; +UINT16 ApicId; // ApicId is Needed only if it a core McBank. +UINT16 McBankNum; +UINT64 McBankStatus; +UINT64 McbankAddr; +UINT64 McBankMisc; +} MCBANK_ERR_INFO; + +typedef struct { +UINT8 Type; // PciExType =2 ; +UINT8 Segment; +UINT8 Bus; +UINT8 Device; +UINT8 Function; +UINT32 AerUncErrSts; +UINT8 AerHdrLogData[16]; +} PCI_EX_ERR_INFO; + +typedef struct { +UINT8 Type; // Other Csr error type =3 ; +UINT8 Segment; +UINT8 Bus; +UINT8 Device; +UINT8 Function; +UINT16 offset; +UINT32 Value; +} CSR_ERR_INFO; + +typedef enum { + McBankType = 1, + PciExType, + CsrOtherType +} ERROR_ACCESS_TYPE; + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/44973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b88af17075b98e88c7e94e55fea37627ec03cd0 Gerrit-Change-Number: 44973 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: coreinfo: Use SPDX license identifiers
by Jacob Garber (Code Review) 14 Sep '20

14 Sep '20

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45178 ) Change subject: coreinfo: Use SPDX license identifiers ...................................................................... coreinfo: Use SPDX license identifiers - Remove copyright notices and add unlisted authors to AUTHORS - Use SPDX license identifiers for all files - Add coreinfo to the license header lint Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Change-Id: Ib0c5328a4027849b1eda4f57141a898335230726 --- M AUTHORS M payloads/coreinfo/Kconfig M payloads/coreinfo/Makefile M payloads/coreinfo/bootlog_module.c M payloads/coreinfo/cbfs_module.c M payloads/coreinfo/coreboot_module.c M payloads/coreinfo/coreinfo.c M payloads/coreinfo/coreinfo.h M payloads/coreinfo/cpuid.S M payloads/coreinfo/cpuinfo_module.c M payloads/coreinfo/multiboot_module.c M payloads/coreinfo/nvram_module.c M payloads/coreinfo/pci_module.c M payloads/coreinfo/ramdump_module.c M payloads/coreinfo/timestamps_module.c M util/lint/lint-stable-000-license-headers 16 files changed, 18 insertions(+), 169 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/45178/1 diff --git a/AUTHORS b/AUTHORS index 8b1cb22..a642da7 100644 --- a/AUTHORS +++ b/AUTHORS @@ -46,6 +46,7 @@ Custom Ideas Damien Zammit Dave Airlie +Dave Jones David Brownell David Greenman David Hendricks diff --git a/payloads/coreinfo/Kconfig b/payloads/coreinfo/Kconfig index 3b69c0c..eafb879 100644 --- a/payloads/coreinfo/Kconfig +++ b/payloads/coreinfo/Kconfig @@ -1,7 +1,3 @@ -## -## -## Copyright (C) 2008 Uwe Hermann <uwe(a)hermann-uwe.de> -## ## SPDX-License-Identifier: GPL-2.0-only # For a description of the syntax of this configuration file, diff --git a/payloads/coreinfo/Makefile b/payloads/coreinfo/Makefile index 898b12b..d842b46 100644 --- a/payloads/coreinfo/Makefile +++ b/payloads/coreinfo/Makefile @@ -1,8 +1,3 @@ -## -## -## Copyright (C) 2008 Advanced Micro Devices, Inc. -## Copyright (C) 2008 Uwe Hermann <uwe(a)hermann-uwe.de> -## ## SPDX-License-Identifier: GPL-2.0-only src := $(CURDIR) diff --git a/payloads/coreinfo/bootlog_module.c b/payloads/coreinfo/bootlog_module.c index da9860a..280ea51 100644 --- a/payloads/coreinfo/bootlog_module.c +++ b/payloads/coreinfo/bootlog_module.c @@ -1,16 +1,4 @@ -/* - * - * Copyright (C) 2008 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include "coreinfo.h" diff --git a/payloads/coreinfo/cbfs_module.c b/payloads/coreinfo/cbfs_module.c index f22453e..adbe277 100644 --- a/payloads/coreinfo/cbfs_module.c +++ b/payloads/coreinfo/cbfs_module.c @@ -1,16 +1,4 @@ -/* - * - * Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include "coreinfo.h" #include "endian.h" diff --git a/payloads/coreinfo/coreboot_module.c b/payloads/coreinfo/coreboot_module.c index 074d73a..87032d5 100644 --- a/payloads/coreinfo/coreboot_module.c +++ b/payloads/coreinfo/coreboot_module.c @@ -1,16 +1,4 @@ -/* - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include "coreinfo.h" #include <coreboot_tables.h> diff --git a/payloads/coreinfo/coreinfo.c b/payloads/coreinfo/coreinfo.c index 35e5016..b357f97 100644 --- a/payloads/coreinfo/coreinfo.c +++ b/payloads/coreinfo/coreinfo.c @@ -1,16 +1,4 @@ -/* - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include "coreinfo.h" diff --git a/payloads/coreinfo/coreinfo.h b/payloads/coreinfo/coreinfo.h index 004a5e9..b96af89 100644 --- a/payloads/coreinfo/coreinfo.h +++ b/payloads/coreinfo/coreinfo.h @@ -1,16 +1,4 @@ -/* - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef COREINFO_H_ #define COREINFO_H_ diff --git a/payloads/coreinfo/cpuid.S b/payloads/coreinfo/cpuid.S index b004052..84cdc77 100644 --- a/payloads/coreinfo/cpuid.S +++ b/payloads/coreinfo/cpuid.S @@ -1,18 +1,6 @@ -/* - * - * It is derived from the x86info project, which is GPLv2-licensed. - * - * Copyright (C) 2001-2007 Dave Jones <davej(a)codemonkey.org.uk> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* It is derived from the x86info project, which is GPLv2-licensed. */ /* calling syntax: docpuid(idx,eax,ebx,ecx,edx) */ diff --git a/payloads/coreinfo/cpuinfo_module.c b/payloads/coreinfo/cpuinfo_module.c index 96c495a..b937e4c 100644 --- a/payloads/coreinfo/cpuinfo_module.c +++ b/payloads/coreinfo/cpuinfo_module.c @@ -1,19 +1,6 @@ -/* - * - * It is derived from the x86info project, which is GPLv2-licensed. - * - * Copyright (C) 2001-2007 Dave Jones <davej(a)codemonkey.org.uk> - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* It is derived from the x86info project, which is GPLv2-licensed. */ #include "coreinfo.h" diff --git a/payloads/coreinfo/multiboot_module.c b/payloads/coreinfo/multiboot_module.c index dd5ce36..2ec9929 100644 --- a/payloads/coreinfo/multiboot_module.c +++ b/payloads/coreinfo/multiboot_module.c @@ -1,16 +1,4 @@ -/* - * - * Copyright (C) 2008 Jordan Crouse <jordan(a)cosmicpenguin.net> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include <multiboot_tables.h> #include "coreinfo.h" diff --git a/payloads/coreinfo/nvram_module.c b/payloads/coreinfo/nvram_module.c index 9ac734a..99c6e9b 100644 --- a/payloads/coreinfo/nvram_module.c +++ b/payloads/coreinfo/nvram_module.c @@ -1,16 +1,4 @@ -/* - * - * Copyright (C) 2008 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include "coreinfo.h" diff --git a/payloads/coreinfo/pci_module.c b/payloads/coreinfo/pci_module.c index 019f8d0..0385e9d 100644 --- a/payloads/coreinfo/pci_module.c +++ b/payloads/coreinfo/pci_module.c @@ -1,16 +1,4 @@ -/* - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/io.h> #include <pci.h> diff --git a/payloads/coreinfo/ramdump_module.c b/payloads/coreinfo/ramdump_module.c index abb8472..762707f 100644 --- a/payloads/coreinfo/ramdump_module.c +++ b/payloads/coreinfo/ramdump_module.c @@ -1,16 +1,4 @@ -/* - * - * Copyright (C) 2008 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include "coreinfo.h" diff --git a/payloads/coreinfo/timestamps_module.c b/payloads/coreinfo/timestamps_module.c index c8b8df2..3a24930 100644 --- a/payloads/coreinfo/timestamps_module.c +++ b/payloads/coreinfo/timestamps_module.c @@ -1,14 +1,4 @@ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include "coreinfo.h" #include <commonlib/timestamp_serialized.h> diff --git a/util/lint/lint-stable-000-license-headers b/util/lint/lint-stable-000-license-headers index 9da4a9a..518b232 100755 --- a/util/lint/lint-stable-000-license-headers +++ b/util/lint/lint-stable-000-license-headers @@ -6,4 +6,4 @@ # Top level util/lint/lint-000-license-headers "src/acpi src/arch src/commonlib src/console \ src/cpu src/device src/drivers src/ec src/mainboard src/northbridge \ - src/security src/soc src/southbridge src/superio tests/" + src/security src/soc src/southbridge src/superio tests payloads/coreinfo" -- To view, visit https://review.coreboot.org/c/coreboot/+/45178 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0c5328a4027849b1eda4f57141a898335230726 Gerrit-Change-Number: 45178 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

6 9

Change in coreboot[master]: mb/google/volteer: Fix GPP_E12 definition
by Patrick Georgi (Code Review) 14 Sep '20

14 Sep '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45197 ) Change subject: mb/google/volteer: Fix GPP_E12 definition ...................................................................... mb/google/volteer: Fix GPP_E12 definition GPP_E12 should not be defined in the baseboard as its use is determined by the variant. For legacy reasons, we still have GPP_E12 defined in early_gpio but should not. Malefor and volteer* have the same GPP_E12 definition, but that is a misconfiguration. I think that was a copy-paste that slipped through the reviews. BUG=b:157597158 TEST=volteer2 boots to the OS Change-Id: Ic3ef864827aa94b0b96e335565119f3d5d008837 Signed-off-by: Caveh Jalali <caveh(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45197 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/volteer/variants/baseboard/gpio.c M src/mainboard/google/volteer/variants/malefor/gpio.c M src/mainboard/google/volteer/variants/volteer/gpio.c M src/mainboard/google/volteer/variants/volteer2/gpio.c 4 files changed, 0 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Nick Vaccaro: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/volteer/variants/baseboard/gpio.c b/src/mainboard/google/volteer/variants/baseboard/gpio.c index c938b28..5d367e7 100644 --- a/src/mainboard/google/volteer/variants/baseboard/gpio.c +++ b/src/mainboard/google/volteer/variants/baseboard/gpio.c @@ -422,9 +422,6 @@ /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), - /* E12 : SPI1_MISO_IO1 ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_E12, 1, DEEP), - /* F11 : THC1_SPI2_CLK ==> EN_PP3300_WWAN */ PAD_CFG_GPO(GPP_F11, 1, DEEP), }; diff --git a/src/mainboard/google/volteer/variants/malefor/gpio.c b/src/mainboard/google/volteer/variants/malefor/gpio.c index 22dec73..90ad354 100644 --- a/src/mainboard/google/volteer/variants/malefor/gpio.c +++ b/src/mainboard/google/volteer/variants/malefor/gpio.c @@ -186,9 +186,6 @@ /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ PAD_CFG_GPO(GPP_D16, 1, DEEP), - /* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */ - PAD_CFG_GPO(GPP_E12, 1, DEEP), - /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ PAD_CFG_GPO(GPP_H11, 1, DEEP), }; diff --git a/src/mainboard/google/volteer/variants/volteer/gpio.c b/src/mainboard/google/volteer/variants/volteer/gpio.c index bd84585..422764e 100644 --- a/src/mainboard/google/volteer/variants/volteer/gpio.c +++ b/src/mainboard/google/volteer/variants/volteer/gpio.c @@ -234,9 +234,6 @@ /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ PAD_NC(GPP_D16, UP_20K), - /* E12 : SPI1_MISO_IO1 ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_E12, 1, DEEP), - /* F11 : THC1_SPI2_CLK ==> EN_PP3300_WWAN */ PAD_CFG_GPO(GPP_F11, 1, DEEP), /* F12 : GSXDOUT ==> WWAN_RST_ODL diff --git a/src/mainboard/google/volteer/variants/volteer2/gpio.c b/src/mainboard/google/volteer/variants/volteer2/gpio.c index 7255423..124f220 100644 --- a/src/mainboard/google/volteer/variants/volteer2/gpio.c +++ b/src/mainboard/google/volteer/variants/volteer2/gpio.c @@ -234,9 +234,6 @@ /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ PAD_NC(GPP_D16, UP_20K), - /* E12 : SPI1_MISO_IO1 ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_E12, 1, DEEP), - /* F11 : THC1_SPI2_CLK ==> EN_PP3300_WWAN */ PAD_CFG_GPO(GPP_F11, 1, DEEP), /* F12 : GSXDOUT ==> WWAN_RST_ODL -- To view, visit https://review.coreboot.org/c/coreboot/+/45197 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3ef864827aa94b0b96e335565119f3d5d008837 Gerrit-Change-Number: 45197 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/volteer/var/voxel: Update DPTF parameters and TCC offset
by David Wu (Code Review) 14 Sep '20

14 Sep '20

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45111 ) Change subject: mb/google/volteer/var/voxel: Update DPTF parameters and TCC offset ...................................................................... mb/google/volteer/var/voxel: Update DPTF parameters and TCC offset 1. Set tcc offset to 5 degree celsius 2. Apply the DPTF parameters receive from the thermal team. BUG=b:167523658 TEST=build and verify by thermal team Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I01a6fc5bd959798c8dd423df3907c69c883733e8 --- M src/mainboard/google/volteer/variants/voxel/overridetree.cb 1 file changed, 100 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/45111/1 diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index 43296d5..0e7f4fd 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -1,5 +1,105 @@ chip soc/intel/tigerlake + register "tcc_offset" = "5" # TCC of 95 + + register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ + .tdp_pl1_override = 18, + .tdp_pl2_override = 51, + .tdp_pl4 = 105, + }" + device domain 0 on + device pci 04.0 on + # Default DPTF Policy for all Volteer boards if not overridden + chip drivers/intel/dptf + ## Active Policy + register "policies.active[0]" = "{.target=DPTF_CPU, + .thresholds={TEMP_PCT(94, 100), + TEMP_PCT(0, 0), + TEMP_PCT(0, 0), + TEMP_PCT(0, 0), + TEMP_PCT(0, 0),}}" + register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, + .thresholds={TEMP_PCT(0, 0), + TEMP_PCT(0, 0), + TEMP_PCT(0, 0), + TEMP_PCT(0, 0), + TEMP_PCT(0, 0),}}" + register "policies.active[2]" = "{.target=DPTF_TEMP_SENSOR_1, + .thresholds={TEMP_PCT(0, 0), + TEMP_PCT(0, 0), + TEMP_PCT(0, 0), + TEMP_PCT(0, 0), + TEMP_PCT(0, 0),}}" + register "policies.active[3]" = "{.target=DPTF_TEMP_SENSOR_2, + .thresholds={TEMP_PCT(64, 100), + TEMP_PCT(60, 90), + TEMP_PCT(56, 80), + TEMP_PCT(52, 70), + TEMP_PCT(48, 60), + TEMP_PCT(44, 50), + TEMP_PCT(40, 40),}}" + register "policies.active[4]" = "{.target=DPTF_TEMP_SENSOR_3, + .thresholds={TEMP_PCT(0, 0), + TEMP_PCT(0, 0), + TEMP_PCT(0, 0), + TEMP_PCT(0, 0), + TEMP_PCT(0, 0),}}" + + ## Passive Policy + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 65, 6000)" + register "policies.passive[2]" = "DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 65, 6000)" + register "policies.passive[3]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 54, 6000)" + register "policies.passive[4]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 65, 6000)" + + ## Critical Policy + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)" + register "policies.critical[2]" = "DPTF_CRITICAL(TEMP_SENSOR_1, 75, SHUTDOWN)" + register "policies.critical[3]" = "DPTF_CRITICAL(TEMP_SENSOR_2, 75, SHUTDOWN)" + register "policies.critical[4]" = "DPTF_CRITICAL(TEMP_SENSOR_3, 75, SHUTDOWN)" + + ## Power Limits Control + # 12-18W PL1 in 200mW increments, avg over 28-32s interval + # PL2 is fixed at 51W, avg over 28-32s interval + register "controls.power_limits.pl1" = "{ + .min_power = 12000, + .max_power = 18000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 15000, + .max_power = 51000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf[0]" = "{ 255, 1700 }" + register "controls.charger_perf[1]" = "{ 24, 1500 }" + register "controls.charger_perf[2]" = "{ 16, 1000 }" + register "controls.charger_perf[3]" = "{ 8, 500 }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" + register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" + register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" + register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" + register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" + register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" + register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" + register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" + register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" + register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" + + # Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 on end + end + end # DPTF 0x9A03 device pci 15.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" -- To view, visit https://review.coreboot.org/c/coreboot/+/45111 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01a6fc5bd959798c8dd423df3907c69c883733e8 Gerrit-Change-Number: 45111 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

5 12

Change in coreboot[master]: mb/google/volteer: Refactor baseboard devicetree
by Patrick Georgi (Code Review) 14 Sep '20

14 Sep '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45179 ) Change subject: mb/google/volteer: Refactor baseboard devicetree ...................................................................... mb/google/volteer: Refactor baseboard devicetree Clean up the DPTF section of the baseboard devicetree; this makes overrides simpler, as not necessarily all of the fields need to be overridden. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Iad46fd02f7602c9419d7c3674b0d2b6f5add9a93 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45179 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: Caveh Jalali <caveh(a)chromium.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 70 insertions(+), 66 deletions(-) Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved Caveh Jalali: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 1b8b0d6..582f44a 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -282,84 +282,88 @@ # Default DPTF Policy for all Volteer boards if not overridden chip drivers/intel/dptf ## Active Policy - register "policies.active[0]" = "{.target=DPTF_CPU, - .thresholds={TEMP_PCT(85, 90), - TEMP_PCT(80, 69), - TEMP_PCT(75, 56), - TEMP_PCT(70, 46), - TEMP_PCT(65, 36),}}" - register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, - .thresholds={TEMP_PCT(50, 90), - TEMP_PCT(47, 69), - TEMP_PCT(45, 56), - TEMP_PCT(42, 46), - TEMP_PCT(39, 36),}}" - register "policies.active[2]" = "{.target=DPTF_TEMP_SENSOR_1, - .thresholds={TEMP_PCT(50, 90), - TEMP_PCT(47, 69), - TEMP_PCT(45, 56), - TEMP_PCT(42, 46), - TEMP_PCT(39, 36),}}" - register "policies.active[3]" = "{.target=DPTF_TEMP_SENSOR_2, - .thresholds={TEMP_PCT(50, 90), - TEMP_PCT(47, 69), - TEMP_PCT(45, 56), - TEMP_PCT(42, 46), - TEMP_PCT(39, 36),}}" - register "policies.active[4]" = "{.target=DPTF_TEMP_SENSOR_3, - .thresholds={TEMP_PCT(50, 90), - TEMP_PCT(47, 69), - TEMP_PCT(45, 56), - TEMP_PCT(42, 46), - TEMP_PCT(39, 36),}}" + register "policies.active" = "{ + [0] = {.target = DPTF_CPU, + .thresholds = {TEMP_PCT(85, 90), + TEMP_PCT(80, 69), + TEMP_PCT(75, 56), + TEMP_PCT(70, 46), + TEMP_PCT(65, 36),}}, + [1] = {.target = DPTF_TEMP_SENSOR_0, + .thresholds = {TEMP_PCT(50, 90), + TEMP_PCT(47, 69), + TEMP_PCT(45, 56), + TEMP_PCT(42, 46), + TEMP_PCT(39, 36),}}, + [2] = {.target = DPTF_TEMP_SENSOR_1, + .thresholds = {TEMP_PCT(50, 90), + TEMP_PCT(47, 69), + TEMP_PCT(45, 56), + TEMP_PCT(42, 46), + TEMP_PCT(39, 36),}}, + [3] = {.target = DPTF_TEMP_SENSOR_2, + .thresholds = {TEMP_PCT(50, 90), + TEMP_PCT(47, 69), + TEMP_PCT(45, 56), + TEMP_PCT(42, 46), + TEMP_PCT(39, 36),}}, + [4] = {.target = DPTF_TEMP_SENSOR_3, + .thresholds = {TEMP_PCT(50, 90), + TEMP_PCT(47, 69), + TEMP_PCT(45, 56), + TEMP_PCT(42, 46), + TEMP_PCT(39, 36),}}}" ## Passive Policy - register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)" - register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 65, 6000)" - register "policies.passive[2]" = "DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 65, 6000)" - register "policies.passive[3]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 65, 6000)" - register "policies.passive[4]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 65, 6000)" + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 65, 6000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 65, 6000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 65, 6000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 65, 6000)}" ## Critical Policy - register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 105, SHUTDOWN)" - register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)" - register "policies.critical[2]" = "DPTF_CRITICAL(TEMP_SENSOR_1, 75, SHUTDOWN)" - register "policies.critical[3]" = "DPTF_CRITICAL(TEMP_SENSOR_2, 75, SHUTDOWN)" - register "policies.critical[4]" = "DPTF_CRITICAL(TEMP_SENSOR_3, 75, SHUTDOWN)" + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 75, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 75, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 75, SHUTDOWN)}" ## Power Limits Control # 10-15W PL1 in 200mW increments, avg over 28-32s interval # PL2 is fixed at 64W, avg over 28-32s interval - register "controls.power_limits.pl1" = "{ - .min_power = 3000, - .max_power = 15000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 200,}" - register "controls.power_limits.pl2" = "{ - .min_power = 15000, - .max_power = 60000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 1000,}" + register "controls.power_limits" = "{ + .pl1 = {.min_power = 3000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}, + .pl2 = {.min_power = 15000, + .max_power = 60000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}}" ## Charger Performance Control (Control, mA) - register "controls.charger_perf[0]" = "{ 255, 1700 }" - register "controls.charger_perf[1]" = "{ 24, 1500 }" - register "controls.charger_perf[2]" = "{ 16, 1000 }" - register "controls.charger_perf[3]" = "{ 8, 500 }" + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 }}" ## Fan Performance Control (Percent, Speed, Noise, Power) - register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" - register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" - register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" - register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" - register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" - register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" - register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" - register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" - register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" - register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" + register "controls.fan_perf" = "{ + [0] = { 90, 6700, 220, 2200, }, + [1] = { 80, 5800, 180, 1800, }, + [2] = { 70, 5000, 145, 1450, }, + [3] = { 60, 4900, 115, 1150, }, + [4] = { 50, 3838, 90, 900, }, + [5] = { 40, 2904, 55, 550, }, + [6] = { 30, 2337, 30, 300, }, + [7] = { 20, 1608, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, }}" # Fan options register "options.fan.fine_grained_control" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/45179 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad46fd02f7602c9419d7c3674b0d2b6f5add9a93 Gerrit-Change-Number: 45179 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/dedede/variants/drawcia: update PL2 value
by Sumeet R Pawnikar (Code Review) 14 Sep '20

14 Sep '20

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45162 ) Change subject: mb/google/dedede/variants/drawcia: update PL2 value ...................................................................... mb/google/dedede/variants/drawcia: update PL2 value Update PL2 (Power Limit2) value. BRANCH=None BUG=b:166656373 TEST=Built and tested on drawlat system Change-Id: I82d6792907bb1c88cc9dd57d1eaeda8421c12fb2 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/45162/1 diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index faded0e..1157eb8 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -41,7 +41,7 @@ register "power_limits_config" = "{ .tdp_pl1_override = 6, - .tdp_pl2_override = 15, + .tdp_pl2_override = 20, }" register "tcc_offset" = "20" # TCC of 85C @@ -75,7 +75,7 @@ .granularity = 200,}" register "controls.power_limits.pl2" = "{ .min_power = 6000, - .max_power = 15000, + .max_power = 20000, .time_window_min = 1 * MSECS_PER_SEC, .time_window_max = 1 * MSECS_PER_SEC, .granularity = 1000,}" -- To view, visit https://review.coreboot.org/c/coreboot/+/45162 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82d6792907bb1c88cc9dd57d1eaeda8421c12fb2 Gerrit-Change-Number: 45162 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode
by Patrick Georgi (Code Review) 14 Sep '20

14 Sep '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43494 ) Change subject: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode ...................................................................... soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode Update the COS mask calculation to accomodate the RW data as per SoC configuration. Currently only one way is allocated for RW data and configured for non-eviction. For earlier platform this served fine, and could accomodate a RW data up to 256Kb. Starting TGL and JSL, the DCACHE_RAM_SIZE is configured for 512Kb, which cannot be mapped to a single way. Hence update the number of ways to be configured for non- eviction as per total LLC size. The total LLC size/ number of ways gives the way size. DCACHE_RAM_SIZE/ way size gives the number of ways that need to be configured for non- eviction, instead of harcoding it to 1. TGL uses MSR IA32_CR_SF_QOS_MASK_1(0x1891) and IA32_CR_SF_QOS_MASK_2(0x1892) as COS mask selection register and hence needs to be progarmmed accordingly. Also JSL and TGL platforms the COS mask selection is mapped to bit 32:33 of MSR IA32_PQR_ASSOC(0xC8F) and need to be updated in edx(maps 63:32) before MSR write instead of eax(maps 31:0). This implementation corrects that as well. BUG=b:149273819 TEST= Boot waddledoo(JSL), hatch(CML), Volteer(TGL)with NEM enhanced CAR configuration. Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> Change-Id: I54e047161853bfc70516c1d607aa479e68836d04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43494 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/include/cpu/x86/msr.h M src/soc/intel/cannonlake/Kconfig M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/skylake/Kconfig 7 files changed, 119 insertions(+), 43 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Shreesh Chhabbi: Looks good to me, but someone else must approve diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index c761bc0..1573eef 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -90,6 +90,9 @@ #define IA32_L3_MASK_1 0xc91 #define IA32_L3_MASK_2 0xc92 +#define IA32_CR_SF_QOS_MASK_1 0x1891 +#define IA32_CR_SF_QOS_MASK_2 0x1892 + #ifndef __ASSEMBLER__ #include <types.h> diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 9ff2827..596de41 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -310,7 +310,7 @@ config USE_CANNONLAKE_CAR_NEM_ENHANCED bool "Enhanced Non-evict mode" select SOC_INTEL_COMMON_BLOCK_CAR - select INTEL_CAR_NEM_ENHANCED + select USE_CAR_NEM_ENHANCED_V1 help A current limitation of NEM (Non-Evict mode) is that code and data sizes are derived from the requirement to not write out any modified diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 3c29b24..1351cb8 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -51,6 +51,28 @@ ENHANCED NEM guarantees that modified data is always kept in cache while clean data is replaced. +config USE_CAR_NEM_ENHANCED_V1 + bool + select INTEL_CAR_NEM_ENHANCED + help + This config supports INTEL_CAR_NEM_ENHANCED mode on + SKL, KBL, CNL, WHL, CML and ICL and JSL platforms. + +config USE_CAR_NEM_ENHANCED_V2 + bool + select INTEL_CAR_NEM_ENHANCED + select COS_MAPPED_TO_MSB + help + This config supports INTEL_CAR_NEM_ENHANCED mode on + TGL platform. + +config COS_MAPPED_TO_MSB + bool + depends on INTEL_CAR_NEM_ENHANCED + help + On TGL and JSL platform the class of service configuration + is mapped to MSB of MSR IA32_PQR_ASSOC. + config USE_INTEL_FSP_MP_INIT bool "Perform MP Initialization by FSP" default n diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 69ed174..5af1fc6 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -351,54 +351,96 @@ jnz find_llc_subleaf /* - * Set MSR 0xC91 IA32_L3_MASK_1 = 0xE/0xFE/0xFFE/0xFFFE - * for 4/8/16 way of LLC - */ + * Calculate the total LLC size + * (Line_Size + 1) * (Sets + 1) * (Partitions + 1) * (Ways + 1) + * (EBX[11:0] + 1) * (ECX + 1) * (EBX[21:12] + 1) * EBX[31:22] + 1) + */ + + mov %ebx, %eax + and $0xFFF, %eax + inc %eax + inc %ecx + mul %ecx + mov %eax, %ecx + mov %ebx, %eax + shr $12, %eax + and $0x3FF, %eax + inc %eax + mul %ecx shr $22, %ebx inc %ebx - /* Calculate n-way associativity of LLC */ - mov %bl, %cl + mov %ebx, %edx + mul %ebx /* eax now holds total LLC size */ /* - * Maximizing RO cacheability while locking in the CAR to a - * single way since that particular way won't be victim candidate - * for evictions. - * This has been done after programming LLC_WAY_MASK_1 MSR - * with desired LLC way as mentioned below. - * - * Hence create Code and Data Size as per request - * Code Size (RO) : Up to 16M - * Data Size (RW) : Up to 256K + * The number of the ways that we want to protect from eviction + * can be calculated as RW data stack size / way size where way + * size is Total LLC size / Total number of LLC ways. */ - movl $0x01, %eax + div %ebx /* way size */ + mov %eax, %ecx + /* - * LLC Ways -> LLC_WAY_MASK_1: - * 4: 0x000E - * 8: 0x00FE - * 12: 0x0FFE - * 16: 0xFFFE - * - * These MSRs contain one bit per each way of LLC + * Check if way size if bigger than the cache ram size. + * Then we need to allocate just one way for non-eviction + * of RW data. + */ + movl $0x01, %eax + cmp $CONFIG_DCACHE_RAM_SIZE, %ecx + jnc set_eviction_mask + + /* + * RW data size / way size is equal to number of + * ways to be configured for non-eviction + */ + mov $CONFIG_DCACHE_RAM_SIZE, %eax + div %ecx + mov %eax, %ecx + movl $0x01, %eax + shl %cl, %eax + subl $0x01, %eax + +set_eviction_mask: + mov %ebx, %ecx /* back up the number of ways */ + mov %eax, %ebx /* back up the non-eviction mask*/ + /* + * Set MSR 0xC91 IA32_L3_MASK_1 or MSR 0x1891 IA32_CR_SF_QOS_MASK_1 + * This MSR contain one bit per each way of LLC * - If this bit is '0' - the way is protected from eviction * - If this bit is '1' - the way is not protected from eviction */ - shl %cl, %eax - subl $0x02, %eax + mov $0x1, %eax + shl %cl, %eax + subl $0x01, %eax + mov %eax, %ecx + mov %ebx, %eax + + xor $~0, %eax /* invert 32 bits */ + and %ecx, %eax +#if CONFIG(USE_CAR_NEM_ENHANCED_V1) movl $IA32_L3_MASK_1, %ecx +#elif CONFIG(USE_CAR_NEM_ENHANCED_V2) + movl $IA32_CR_SF_QOS_MASK_1, %ecx +#endif + xorl %edx, %edx + wrmsr + + /* + * Set MSR 0xC92 IA32_L3_MASK_1 or MSR 0x1892 IA32_CR_SF_QOS_MASK_2 + * This MSR contain one bit per each way of LLC + * - If this bit is '0' - the way is protected from eviction + * - If this bit is '1' - the way is not protected from eviction + */ + mov %ebx, %eax +#if CONFIG(USE_CAR_NEM_ENHANCED_V1) + movl $IA32_L3_MASK_2, %ecx +#elif CONFIG(USE_CAR_NEM_ENHANCED_V2) + movl $IA32_CR_SF_QOS_MASK_2, %ecx +#endif xorl %edx, %edx wrmsr /* - * Set MSR 0xC92 IA32_L3_MASK_2 = 0x1 - * - * For SKL SOC, data size remains 256K consistently. - * Hence, creating 1-way associative cache for Data - */ - mov $IA32_L3_MASK_2, %ecx - mov $0x01, %eax - xorl %edx, %edx - wrmsr - /* - * Set IA32_PQR_ASSOC = 0x02 + * Set IA32_PQR_ASSOC * * Possible values: * 0: Default value, no way mask should be applied @@ -407,8 +449,13 @@ * 3: Shouldn't be use in NEM Mode */ movl $IA32_PQR_ASSOC, %ecx - movl $0x02, %eax + xorl %eax, %eax xorl %edx, %edx +#if CONFIG(COS_MAPPED_TO_MSB) + movl $0x02, %edx +#else + movl $0x02, %eax +#endif wrmsr movl $CONFIG_DCACHE_RAM_BASE, %edi @@ -418,13 +465,17 @@ cld rep stosl /* - * Set IA32_PQR_ASSOC = 0x01 + * Set IA32_PQR_ASSOC * At this stage we apply LLC_WAY_MASK_1 to the cache. - * i.e. way 0 is protected from eviction. */ movl $IA32_PQR_ASSOC, %ecx - movl $0x01, %eax + xorl %eax, %eax xorl %edx, %edx +#if CONFIG(COS_MAPPED_TO_MSB) + movl $0x01, %edx +#else + movl $0x01, %eax +#endif wrmsr post_code(0x27) diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 33635b3..91b45dc 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -161,7 +161,7 @@ depends on !FSP_CAR default y select SOC_INTEL_COMMON_BLOCK_CAR - select INTEL_CAR_NEM_ENHANCED + select USE_CAR_NEM_ENHANCED_V1 help A current limitation of NEM (Non-Evict mode) is that code and data sizes are derived from the requirement to not write out any modified cache line. diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 1230675..1e66e97 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -52,7 +52,6 @@ select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_BLOCK_CAR - select INTEL_CAR_NEM_ENHANCED select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER @@ -61,6 +60,7 @@ select DISPLAY_FSP_VERSION_INFO select HECI_DISABLE_USING_SMM select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI + select USE_CAR_NEM_ENHANCED_V1 config DCACHE_RAM_BASE default 0xfef00000 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 9f9cb18..db0f688 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -35,7 +35,6 @@ select HAVE_FSP_LOGO_SUPPORT select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER - select INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select HAVE_INTEL_FSP_REPO @@ -79,6 +78,7 @@ select TSC_SYNC_MFENCE select UDELAY_TSC select UDK_2015_BINDING + select USE_CAR_NEM_ENHANCED_V1 config FSP_HYPERTHREADING bool "Enable Hyper-Threading" -- To view, visit https://review.coreboot.org/c/coreboot/+/43494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54e047161853bfc70516c1d607aa479e68836d04 Gerrit-Change-Number: 43494 Gerrit-PatchSet: 8 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-MessageType: merged

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Change in coreboot[master]: device/pnp_device.c: Use 'PNP_IDX_EN' instead of magic number
by HAOUAS Elyes (Code Review) 14 Sep '20

14 Sep '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45327 ) Change subject: device/pnp_device.c: Use 'PNP_IDX_EN' instead of magic number ...................................................................... device/pnp_device.c: Use 'PNP_IDX_EN' instead of magic number Change-Id: I9c3050698f66e91e3b57c27c1755b47520f245ab Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/device/pnp_device.c 1 file changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/45327/1 diff --git a/src/device/pnp_device.c b/src/device/pnp_device.c index cd7adf3..9fa032e 100644 --- a/src/device/pnp_device.c +++ b/src/device/pnp_device.c @@ -5,6 +5,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <device/pnp_def.h> /* PNP config mode wrappers */ @@ -56,7 +57,7 @@ { u8 tmp, bitpos; - tmp = pnp_read_config(dev, 0x30); + tmp = pnp_read_config(dev, PNP_IDX_EN); /* Handle virtual devices, which share the same LDN register. */ bitpos = (dev->path.pnp.device >> 8) & 0x7; @@ -66,14 +67,14 @@ else tmp &= ~(1 << bitpos); - pnp_write_config(dev, 0x30, tmp); + pnp_write_config(dev, PNP_IDX_EN, tmp); } int pnp_read_enable(struct device *dev) { u8 tmp, bitpos; - tmp = pnp_read_config(dev, 0x30); + tmp = pnp_read_config(dev, PNP_IDX_EN); /* Handle virtual devices, which share the same LDN register. */ bitpos = (dev->path.pnp.device >> 8) & 0x7; -- To view, visit https://review.coreboot.org/c/coreboot/+/45327 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c3050698f66e91e3b57c27c1755b47520f245ab Gerrit-Change-Number: 45327 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: include/device/pnp_ops.h: Use 'PNP_IDX_EN' instead of magic number
by HAOUAS Elyes (Code Review) 14 Sep '20

14 Sep '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45328 ) Change subject: include/device/pnp_ops.h: Use 'PNP_IDX_EN' instead of magic number ...................................................................... include/device/pnp_ops.h: Use 'PNP_IDX_EN' instead of magic number Change-Id: I8edfbadc83e48e3a74dbb8d85fc2857d6f4283d4 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/include/device/pnp_ops.h 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/45328/1 diff --git a/src/include/device/pnp_ops.h b/src/include/device/pnp_ops.h index 0cfdd61..18b35be 100644 --- a/src/include/device/pnp_ops.h +++ b/src/include/device/pnp_ops.h @@ -6,6 +6,7 @@ #include <stdint.h> #include <arch/io.h> #include <device/pnp.h> +#include <device/pnp_def.h> #include <device/pnp_type.h> #if ENV_PNP_SIMPLE_DEVICE @@ -32,13 +33,13 @@ static __always_inline void pnp_set_enable(pnp_devfn_t dev, int enable) { - pnp_write_config(dev, 0x30, enable?0x1:0x0); + pnp_write_config(dev, PNP_IDX_EN, enable?0x1:0x0); } static __always_inline int pnp_read_enable(pnp_devfn_t dev) { - return !!pnp_read_config(dev, 0x30); + return !!pnp_read_config(dev, PNP_IDX_EN); } static __always_inline -- To view, visit https://review.coreboot.org/c/coreboot/+/45328 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8edfbadc83e48e3a74dbb8d85fc2857d6f4283d4 Gerrit-Change-Number: 45328 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation: Add ASan documentation
by Arthur Heymans (Code Review) 14 Sep '20

14 Sep '20

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44814 ) Change subject: Documentation: Add ASan documentation ...................................................................... Patch Set 7: Code-Review+1 (2 comments) https://review.coreboot.org/c/coreboot/+/44814/7/Documentation/technotes/as… File Documentation/technotes/asan.md: https://review.coreboot.org/c/coreboot/+/44814/7/Documentation/technotes/as… PS7, Line 248: additional steps need to be taken to enable ASan in : romstage on the platform Maybe suggest playing around with CONFIG_DCACHE_RAM_SIZE (and CONFIG_DCACHE_RAM_BASE)? https://review.coreboot.org/c/coreboot/+/44814/7/Documentation/technotes/as… PS7, Line 283: 1/8th of the : program memory It might be worth explaining somewhere why it has to be this way (in the code or in the docs)? -- To view, visit https://review.coreboot.org/c/coreboot/+/44814 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I710ea495798597189941620c7e48fd5aa7476781 Gerrit-Change-Number: 44814 Gerrit-PatchSet: 7 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 14 Sep 2020 06:16:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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