coreboot-gerrit September 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: lenovo/x60: Enable TPM
by Denis 'GNUtoo' Carikli (Code Review) 13 Sep '20

13 Sep '20

Denis 'GNUtoo' Carikli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/13410 ) Change subject: lenovo/x60: Enable TPM ...................................................................... Patch Set 8: > Patch Set 8: > > I have rebased this, adjusted Kconfig to address comment by Philipp, and remove romstage.c as it is no longer needed. > It compiles and boots, but does not work yet. (I got the very same log as Arthur had commented.) > > Would you mind if I upload new revision? Thanks a lot for working on this. That would be great! In general anyone should free to pickup any of my unfinished work as what's most important for me is to have the work done regardless on how it's done or who does it. Denis. -- To view, visit https://review.coreboot.org/c/coreboot/+/13410 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e65b37507c111af1c0c56822327d5497f58f085 Gerrit-Change-Number: 13410 Gerrit-PatchSet: 8 Gerrit-Owner: Denis Carikli <GNUtoo(a)no-log.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Denis 'GNUtoo' Carikli <GNUtoo(a)cyberdimension.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Masanori Ogino <mogino(a)acm.org> Gerrit-Comment-Date: Sun, 13 Sep 2020 11:20:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: lenovo/x60: Enable TPM
by Masanori Ogino (Code Review) 13 Sep '20

13 Sep '20

Masanori Ogino has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/13410 ) Change subject: lenovo/x60: Enable TPM ...................................................................... Patch Set 8: I have rebased this, adjusted Kconfig to address comment by Philipp, and remove romstage.c as it is no longer needed. It compiles and boots, but does not work yet. (I got the very same log as Arthur had commented.) Would you mind if I upload new revision? -- To view, visit https://review.coreboot.org/c/coreboot/+/13410 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e65b37507c111af1c0c56822327d5497f58f085 Gerrit-Change-Number: 13410 Gerrit-PatchSet: 8 Gerrit-Owner: Denis Carikli <GNUtoo(a)no-log.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Denis 'GNUtoo' Carikli <GNUtoo(a)cyberdimension.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Masanori Ogino <mogino(a)acm.org> Gerrit-Comment-Date: Sun, 13 Sep 2020 09:42:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: .gitmodules: Clean up names and paths.
by Masanori Ogino (Code Review) 13 Sep '20

13 Sep '20

Masanori Ogino has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45319 ) Change subject: .gitmodules: Clean up names and paths. ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/45319 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56b457e6d7fa9e51ee5066136df44083487504d1 Gerrit-Change-Number: 45319 Gerrit-PatchSet: 1 Gerrit-Owner: Masanori Ogino <mogino(a)acm.org> Gerrit-Comment-Date: Sun, 13 Sep 2020 04:50:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso/chip: fix typo in acp_pme_enable
by Felix Held (Code Review) 13 Sep '20

13 Sep '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45300 ) Change subject: soc/amd/picasso/chip: fix typo in acp_pme_enable ...................................................................... soc/amd/picasso/chip: fix typo in acp_pme_enable That devicetree setting is about the Audio Co-Processor and not ACPI. BRANCH=zork Change-Id: I7f376371ee094392d4434340c77f0fc8d0d8e4e1 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb M src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb M src/mainboard/google/zork/variants/baseboard/ramstage_common.c M src/soc/amd/picasso/acp.c M src/soc/amd/picasso/chip.h 5 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/45300/1 diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index 42219d7..a0f6636 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -8,7 +8,7 @@ register "acp_pin_cfg" = "I2S_PINS_I2S_TDM" register "acp_i2s_wake_enable" = "0" - register "acpi_pme_enable" = "0" + register "acp_pme_enable" = "0" # Start : OPN Performance Configuration # (Configuratin that is common for all variants) diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index 1620643..1694519 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -8,7 +8,7 @@ register "acp_pin_cfg" = "I2S_PINS_I2S_TDM" register "acp_i2s_wake_enable" = "0" - register "acpi_pme_enable" = "0" + register "acp_pme_enable" = "0" # Start : OPN Performance Configuration # (Configuratin that is common for all variants) diff --git a/src/mainboard/google/zork/variants/baseboard/ramstage_common.c b/src/mainboard/google/zork/variants/baseboard/ramstage_common.c index 664f659..c2a0294 100644 --- a/src/mainboard/google/zork/variants/baseboard/ramstage_common.c +++ b/src/mainboard/google/zork/variants/baseboard/ramstage_common.c @@ -71,7 +71,7 @@ */ soc_cfg = config_of_soc(); soc_cfg->acp_i2s_wake_enable = 1; - soc_cfg->acpi_pme_enable = 1; + soc_cfg->acp_pme_enable = 1; } static void update_dmic_gpio(void) diff --git a/src/soc/amd/picasso/acp.c b/src/soc/amd/picasso/acp.c index 8e6f4cf..9ee29551 100644 --- a/src/soc/amd/picasso/acp.c +++ b/src/soc/amd/picasso/acp.c @@ -45,7 +45,7 @@ /* Enable ACP_PME_EN and ACP_I2S_WAKE_EN for I2S_WAKE event */ acp_update32(bar, ACP_I2S_WAKE_EN, WAKE_EN_MASK, !!cfg->acp_i2s_wake_enable); - acp_update32(bar, ACP_PME_EN, PME_EN_MASK, !!cfg->acpi_pme_enable); + acp_update32(bar, ACP_PME_EN, PME_EN_MASK, !!cfg->acp_pme_enable); if (cfg->acp_pin_cfg == I2S_PINS_I2S_TDM) sb_clk_output_48Mhz(); /* Internal connection to I2S */ diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index ac1a12c..ad492e0 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -63,7 +63,7 @@ /* Enable ACP I2S wake feature (0 = disable, 1 = enable) */ u8 acp_i2s_wake_enable; /* Enable ACP PME (0 = disable, 1 = enable) */ - u8 acpi_pme_enable; + u8 acp_pme_enable; /** * IRQ 0 - 15 have a default trigger of edge and default polarity of high. -- To view, visit https://review.coreboot.org/c/coreboot/+/45300 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f376371ee094392d4434340c77f0fc8d0d8e4e1 Gerrit-Change-Number: 45300 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso/aoac: make AOAC device number unsigned
by Felix Held (Code Review) 13 Sep '20

13 Sep '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45308 ) Change subject: soc/amd/picasso/aoac: make AOAC device number unsigned ...................................................................... soc/amd/picasso/aoac: make AOAC device number unsigned The AOAC device number is never negative, so make it unsigned. BRANCH=zork Change-Id: I3e0d15a646f02da5767504471961d5d9f8f28bea Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/aoac.c M src/soc/amd/picasso/include/soc/southbridge.h 2 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/45308/1 diff --git a/src/soc/amd/picasso/aoac.c b/src/soc/amd/picasso/aoac.c index f31afbf..f7996e6 100644 --- a/src/soc/amd/picasso/aoac.c +++ b/src/soc/amd/picasso/aoac.c @@ -29,7 +29,7 @@ FCH_AOAC_DEV_ESPI, }; -void power_on_aoac_device(int dev) +void power_on_aoac_device(unsigned int dev) { uint8_t byte; @@ -41,7 +41,7 @@ aoac_write8(AOAC_DEV_D3_CTL(dev), byte); } -void power_off_aoac_device(int dev) +void power_off_aoac_device(unsigned int dev) { uint8_t byte; @@ -51,7 +51,7 @@ aoac_write8(AOAC_DEV_D3_CTL(dev), byte); } -bool is_aoac_device_enabled(int dev) +bool is_aoac_device_enabled(unsigned int dev) { uint8_t byte; @@ -63,7 +63,7 @@ return false; } -void wait_for_aoac_enabled(int dev) +void wait_for_aoac_enabled(unsigned int dev) { while (!is_aoac_device_enabled(dev)) udelay(100); diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 168b2b2..547f602 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -269,10 +269,10 @@ } __packed aoac_devs_t; void enable_aoac_devices(void); -bool is_aoac_device_enabled(int dev); -void power_on_aoac_device(int dev); -void power_off_aoac_device(int dev); -void wait_for_aoac_enabled(int dev); +bool is_aoac_device_enabled(unsigned int dev); +void power_on_aoac_device(unsigned int dev); +void power_off_aoac_device(unsigned int dev); +void wait_for_aoac_enabled(unsigned int dev); void sb_clk_output_48Mhz(void); void sb_enable(struct device *dev); void southbridge_final(void *chip_info); -- To view, visit https://review.coreboot.org/c/coreboot/+/45308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e0d15a646f02da5767504471961d5d9f8f28bea Gerrit-Change-Number: 45308 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso/uart: make AOAC device ID in uart_enable unsigned
by Felix Held (Code Review) 13 Sep '20

13 Sep '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45310 ) Change subject: soc/amd/picasso/uart: make AOAC device ID in uart_enable unsigned ...................................................................... soc/amd/picasso/uart: make AOAC device ID in uart_enable unsigned This change is separate from CB:45308 to only have the directly UART- related changes in this patch train. BRANCH=zork Change-Id: Ie587fdbd1e6229c1374fce3568c6a361577dc6c4 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/uart.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/45310/1 diff --git a/src/soc/amd/picasso/uart.c b/src/soc/amd/picasso/uart.c index 881bc3e..2ef1979 100644 --- a/src/soc/amd/picasso/uart.c +++ b/src/soc/amd/picasso/uart.c @@ -97,7 +97,7 @@ /* Even though this is called enable, it gets called for both enabled and disabled devices. */ static void uart_enable(struct device *dev) { - int dev_id; + unsigned int dev_id; switch (dev->path.mmio.addr) { case APU_UART0_BASE: -- To view, visit https://review.coreboot.org/c/coreboot/+/45310 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie587fdbd1e6229c1374fce3568c6a361577dc6c4 Gerrit-Change-Number: 45310 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso/uart: add missing types.h include
by Felix Held (Code Review) 13 Sep '20

13 Sep '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45309 ) Change subject: soc/amd/picasso/uart: add missing types.h include ...................................................................... soc/amd/picasso/uart: add missing types.h include BRANCH=zork Change-Id: I51923d72a2ad8dceeef11e15fb6765262dd514d9 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/uart.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/45309/1 diff --git a/src/soc/amd/picasso/uart.c b/src/soc/amd/picasso/uart.c index 0bf7eb8..881bc3e 100644 --- a/src/soc/amd/picasso/uart.c +++ b/src/soc/amd/picasso/uart.c @@ -9,6 +9,7 @@ #include <soc/southbridge.h> #include <soc/gpio.h> #include <soc/uart.h> +#include <types.h> static const struct _uart_info { uintptr_t base; -- To view, visit https://review.coreboot.org/c/coreboot/+/45309 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51923d72a2ad8dceeef11e15fb6765262dd514d9 Gerrit-Change-Number: 45309 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: 3rdparty/vboot: Update to latest master
by Idwer Vollering (Code Review) 12 Sep '20

12 Sep '20

Idwer Vollering has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45299 ) Change subject: 3rdparty/vboot: Update to latest master ...................................................................... 3rdparty/vboot: Update to latest master This includes several portability fixes, https://chromium-review.googlesource.com/2382790 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> Change-Id: I0efef2f0ab6ecb89c8132cca2bd4ab7f71e85ced --- M 3rdparty/vboot 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/45299/1 diff --git a/3rdparty/vboot b/3rdparty/vboot index fefcaa6..4bb06cc 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit fefcaa653f2c7a79aa0270d8b2ef7cb290a6f225 +Subproject commit 4bb06cc1b73c738acf056d7fc0a96c4690e8ef8a -- To view, visit https://review.coreboot.org/c/coreboot/+/45299 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0efef2f0ab6ecb89c8132cca2bd4ab7f71e85ced Gerrit-Change-Number: 45299 Gerrit-PatchSet: 1 Gerrit-Owner: Idwer Vollering <vidwer(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cnl: Add ACPI support for PMC core OS driver
by Angel Pons (Code Review) 12 Sep '20

12 Sep '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45318 ) Change subject: soc/intel/cnl: Add ACPI support for PMC core OS driver ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/45318 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf7c8ba7449df15c2ca30d23791e17fc878204f2 Gerrit-Change-Number: 45318 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 12 Sep 2020 20:50:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: rename "RSVD" GPIOs to their correct names
by Michael Niewöhner (Code Review) 12 Sep '20

12 Sep '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Patrick Georgi, Paul Menzel, Subrata Banik, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45210 to look at the new patch set (#10). Change subject: soc/intel/cannonlake: rename "RSVD" GPIOs to their correct names ...................................................................... soc/intel/cannonlake: rename "RSVD" GPIOs to their correct names The names of the GPIO_RSVD_* are documented in the PCH EDS, in Linux (linux/drivers/pinctrl/intel/pinctrl-cannonlake.c) and other places. Also, see soc/intel/tigerlake for reference. Change-Id: I59df09c8fd464e75f918455aa1972765abc51459 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/cannonlake/acpi/gpio.asl M src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl M src/soc/intel/cannonlake/gpio.c M src/soc/intel/cannonlake/gpio_cnp_h.c M src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h M src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h 6 files changed, 130 insertions(+), 130 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/45210/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/45210 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59df09c8fd464e75f918455aa1972765abc51459 Gerrit-Change-Number: 45210 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit September 2020