coreboot-gerrit September 2020

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Change in coreboot[master]: soc/intel/cannonlake: rename "RSVD" GPIOs to their correct names
by Michael Niewöhner (Code Review) 12 Sep '20

12 Sep '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Patrick Georgi, Paul Menzel, Subrata Banik, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45210 to look at the new patch set (#9). Change subject: soc/intel/cannonlake: rename "RSVD" GPIOs to their correct names ...................................................................... soc/intel/cannonlake: rename "RSVD" GPIOs to their correct names The names of the GPIO_RSVD_* are documented in the PCH EDS, in Linux (linux/drivers/pinctrl/intel/pinctrl-cannonlake.c) and other places. Also, see soc/intel/tigerlake for reference. Change-Id: I59df09c8fd464e75f918455aa1972765abc51459 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/cannonlake/acpi/gpio.asl M src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl M src/soc/intel/cannonlake/gpio.c M src/soc/intel/cannonlake/gpio_cnp_h.c M src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h M src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h 6 files changed, 130 insertions(+), 130 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/45210/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/45210 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59df09c8fd464e75f918455aa1972765abc51459 Gerrit-Change-Number: 45210 Gerrit-PatchSet: 9 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/cnl: Add ACPI support for PMC core OS driver
by Michael Niewöhner (Code Review) 12 Sep '20

12 Sep '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45318 ) Change subject: soc/intel/cnl: Add ACPI support for PMC core OS driver ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/45318/1/src/soc/intel/cannonlake/a… File src/soc/intel/cannonlake/acpi/southbridge.asl: https://review.coreboot.org/c/coreboot/+/45318/1/src/soc/intel/cannonlake/a… PS1, Line 49: */ > missing a space Done -- To view, visit https://review.coreboot.org/c/coreboot/+/45318 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf7c8ba7449df15c2ca30d23791e17fc878204f2 Gerrit-Change-Number: 45318 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 12 Sep 2020 20:23:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cnl: Add ACPI support for PMC core OS driver
by Michael Niewöhner (Code Review) 12 Sep '20

12 Sep '20

Hello Felix Singer, Nico Huber, Paul Menzel, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45318 to look at the new patch set (#2). Change subject: soc/intel/cnl: Add ACPI support for PMC core OS driver ...................................................................... soc/intel/cnl: Add ACPI support for PMC core OS driver PMC core OS driver (intel_pmc_core.c in linux kernel) provides debug hooks to developers and end users to quickly figure out why their platform is not entering a deeper idle state such as S0ix. Include the common pmc.asl added in commit 957481c. Change-Id: Ibf7c8ba7449df15c2ca30d23791e17fc878204f2 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/cannonlake/acpi/southbridge.asl 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/45318/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45318 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf7c8ba7449df15c2ca30d23791e17fc878204f2 Gerrit-Change-Number: 45318 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/cnl: Add ACPI support for PMC core OS driver
by Angel Pons (Code Review) 12 Sep '20

12 Sep '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45318 ) Change subject: soc/intel/cnl: Add ACPI support for PMC core OS driver ...................................................................... Patch Set 1: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/45318/1/src/soc/intel/cannonlake/a… File src/soc/intel/cannonlake/acpi/southbridge.asl: https://review.coreboot.org/c/coreboot/+/45318/1/src/soc/intel/cannonlake/a… PS1, Line 49: */ missing a space -- To view, visit https://review.coreboot.org/c/coreboot/+/45318 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf7c8ba7449df15c2ca30d23791e17fc878204f2 Gerrit-Change-Number: 45318 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 12 Sep 2020 20:11:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cnl: Add ACPI support for PMC core OS driver
by Michael Niewöhner (Code Review) 12 Sep '20

12 Sep '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45318 ) Change subject: soc/intel/cnl: Add ACPI support for PMC core OS driver ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/45318 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf7c8ba7449df15c2ca30d23791e17fc878204f2 Gerrit-Change-Number: 45318 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 12 Sep 2020 20:01:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/denverton_ns/uart_debug: include header for uart_platform_base
by Felix Held (Code Review) 12 Sep '20

12 Sep '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45295 ) Change subject: soc/intel/denverton_ns/uart_debug: include header for uart_platform_base ...................................................................... soc/intel/denverton_ns/uart_debug: include header for uart_platform_base Include console/uart.h for the declaration of uart_platform_base instead of declaring the function in the source file. Change-Id: Ib72d8884f27e93cec058dbcda404dd6908de1981 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/intel/denverton_ns/uart_debug.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/45295/1 diff --git a/src/soc/intel/denverton_ns/uart_debug.c b/src/soc/intel/denverton_ns/uart_debug.c index acd1f03..7f804c7 100644 --- a/src/soc/intel/denverton_ns/uart_debug.c +++ b/src/soc/intel/denverton_ns/uart_debug.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <stdint.h> +#include <console/uart.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include <soc/uart.h> @@ -8,8 +9,6 @@ #define MY_PCI_DEV(SEGBUS, DEV, FN) \ ((((SEGBUS)&0xFFF) << 20) | (((DEV)&0x1F) << 15) | (((FN)&0x07) << 12)) -uintptr_t uart_platform_base(unsigned int idx); - uintptr_t uart_platform_base(unsigned int idx) { return (uintptr_t)pci_io_read_config32( -- To view, visit https://review.coreboot.org/c/coreboot/+/45295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib72d8884f27e93cec058dbcda404dd6908de1981 Gerrit-Change-Number: 45295 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/ocp/deltalake: Enable TPM2
by Christian Walter (Code Review) 12 Sep '20

12 Sep '20

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45268 ) Change subject: mb/ocp/deltalake: Enable TPM2 ...................................................................... mb/ocp/deltalake: Enable TPM2 Change-Id: I6eaaf80dd2bd69096574ab967ec0c6738b05903b Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M src/mainboard/ocp/deltalake/Kconfig M src/mainboard/ocp/deltalake/devicetree.cb 2 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/45268/1 diff --git a/src/mainboard/ocp/deltalake/Kconfig b/src/mainboard/ocp/deltalake/Kconfig index b229c94..adce988 100644 --- a/src/mainboard/ocp/deltalake/Kconfig +++ b/src/mainboard/ocp/deltalake/Kconfig @@ -14,6 +14,8 @@ select VPD select VPD_SMBIOS_VERSION select IPMI_OCP + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM2 config POWER_STATE_DEFAULT_ON_AFTER_FAILURE default n diff --git a/src/mainboard/ocp/deltalake/devicetree.cb b/src/mainboard/ocp/deltalake/devicetree.cb index 1773f9f..d51391d 100644 --- a/src/mainboard/ocp/deltalake/devicetree.cb +++ b/src/mainboard/ocp/deltalake/devicetree.cb @@ -89,6 +89,9 @@ chip drivers/ipmi/ocp # OCP specific IPMI porting device pnp ca2.1 on end end + chip drivers/pc80/tpm # TPM + device pnp 0c31.0 on end + end end # ISA bridge: Intel Device a245 device pci 1f.1 on end # p2sb device pci 1f.2 on end # Memory controller: Intel Device a221 -- To view, visit https://review.coreboot.org/c/coreboot/+/45268 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6eaaf80dd2bd69096574ab967ec0c6738b05903b Gerrit-Change-Number: 45268 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: include/console/uart: make index parameter unsigned
by Felix Held (Code Review) 12 Sep '20

12 Sep '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45294 ) Change subject: include/console/uart: make index parameter unsigned ...................................................................... include/console/uart: make index parameter unsigned The UART index is never negative, so make it unsigned and drop the checks for the index to be non-negative. Change-Id: I64bd60bd2a3b82552cb3ac6524792b9ac6c09a94 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/drivers/uart/oxpcie_early.c M src/drivers/uart/pl011.c M src/drivers/uart/sifive.c M src/drivers/uart/uart8250io.c M src/drivers/uart/uart8250mem.c M src/include/console/uart.h M src/mainboard/emulation/qemu-aarch64/mmio.c M src/mainboard/emulation/qemu-armv7/mmio.c M src/mainboard/emulation/qemu-power8/uart.c M src/mainboard/emulation/qemu-riscv/uart.c M src/mainboard/emulation/spike-riscv/uart.c M src/soc/amd/picasso/uart_console.c M src/soc/amd/stoneyridge/uart.c M src/soc/cavium/cn81xx/uart.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/denverton_ns/uart_debug.c M src/soc/intel/quark/uart_common.c M src/soc/mediatek/common/uart.c M src/soc/nvidia/tegra124/uart.c M src/soc/nvidia/tegra210/uart.c M src/soc/qualcomm/ipq40xx/uart.c M src/soc/qualcomm/ipq806x/uart.c M src/soc/qualcomm/qcs405/uart.c M src/soc/qualcomm/sc7180/qupv3_uart.c M src/soc/qualcomm/sc7180/uart_bitbang.c M src/soc/qualcomm/sdm845/uart_bitbang.c M src/soc/rockchip/common/uart.c M src/soc/samsung/exynos5250/uart.c M src/soc/samsung/exynos5420/uart.c M src/soc/sifive/fu540/uart.c M src/soc/ti/am335x/uart.c M src/southbridge/amd/pi/hudson/uart.c 32 files changed, 98 insertions(+), 98 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/45294/1 diff --git a/src/drivers/uart/oxpcie_early.c b/src/drivers/uart/oxpcie_early.c index b012c5a..ff7d0cf 100644 --- a/src/drivers/uart/oxpcie_early.c +++ b/src/drivers/uart/oxpcie_early.c @@ -55,9 +55,9 @@ return oxpcie_present; } -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { - if ((idx >= 0) && (idx < 8) && oxpcie_uart_active()) + if ((idx < 8) && oxpcie_uart_active()) return uart0_base + idx * 0x200; return 0; } diff --git a/src/drivers/uart/pl011.c b/src/drivers/uart/pl011.c index 2b81e76..0a73d82 100644 --- a/src/drivers/uart/pl011.c +++ b/src/drivers/uart/pl011.c @@ -5,11 +5,11 @@ #include <console/uart.h> #include <drivers/uart/pl011.h> -void uart_init(int idx) +void uart_init(unsigned int idx) { } -void uart_tx_byte(int idx, unsigned char data) +void uart_tx_byte(unsigned int idx, unsigned char data) { struct pl011_uart *regs = uart_platform_baseptr(idx); @@ -17,7 +17,7 @@ uart_tx_flush(idx); } -void uart_tx_flush(int idx) +void uart_tx_flush(unsigned int idx) { struct pl011_uart *regs = uart_platform_baseptr(idx); @@ -26,7 +26,7 @@ ; } -unsigned char uart_rx_byte(int idx) +unsigned char uart_rx_byte(unsigned int idx) { struct pl011_uart *regs = uart_platform_baseptr(idx); diff --git a/src/drivers/uart/sifive.c b/src/drivers/uart/sifive.c index 0c94c6a..31181aa 100644 --- a/src/drivers/uart/sifive.c +++ b/src/drivers/uart/sifive.c @@ -45,7 +45,7 @@ write32(&regs->rxctrl, RXCTRL_RXEN|RXCTRL_RXCNT(0)); } -void uart_init(int idx) +void uart_init(unsigned int idx) { unsigned int div; div = uart_baudrate_divisor(get_uart_baudrate(), @@ -58,7 +58,7 @@ return !(read32(&regs->txdata) & TXDATA_FULL); } -void uart_tx_byte(int idx, unsigned char data) +void uart_tx_byte(unsigned int idx, unsigned char data) { struct sifive_uart_registers *regs = uart_platform_baseptr(idx); @@ -68,7 +68,7 @@ write32(&regs->txdata, data); } -void uart_tx_flush(int idx) +void uart_tx_flush(unsigned int idx) { struct sifive_uart_registers *regs = uart_platform_baseptr(idx); uint32_t ip; @@ -79,7 +79,7 @@ } while (!(ip & IP_TXWM)); } -unsigned char uart_rx_byte(int idx) +unsigned char uart_rx_byte(unsigned int idx) { struct sifive_uart_registers *regs = uart_platform_baseptr(idx); uint32_t rxdata; diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index 22b79e8..d0841de 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -77,14 +77,14 @@ static const unsigned int bases[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { if (idx < ARRAY_SIZE(bases)) return bases[idx]; return 0; } -void uart_init(int idx) +void uart_init(unsigned int idx) { if (!CONFIG(DRIVERS_UART_8250IO_SKIP_INIT)) { unsigned int div; @@ -94,17 +94,17 @@ } } -void uart_tx_byte(int idx, unsigned char data) +void uart_tx_byte(unsigned int idx, unsigned char data) { uart8250_tx_byte(uart_platform_base(idx), data); } -unsigned char uart_rx_byte(int idx) +unsigned char uart_rx_byte(unsigned int idx) { return uart8250_rx_byte(uart_platform_base(idx)); } -void uart_tx_flush(int idx) +void uart_tx_flush(unsigned int idx) { uart8250_tx_flush(uart_platform_base(idx)); } diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index 8d73272..1834095 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -97,7 +97,7 @@ uart8250_write(base, UART8250_LCR, CONFIG_TTYS0_LCS); } -void uart_init(int idx) +void uart_init(unsigned int idx) { void *base = uart_platform_baseptr(idx); if (!base) @@ -109,7 +109,7 @@ uart8250_mem_init(base, div); } -void uart_tx_byte(int idx, unsigned char data) +void uart_tx_byte(unsigned int idx, unsigned char data) { void *base = uart_platform_baseptr(idx); if (!base) @@ -117,7 +117,7 @@ uart8250_mem_tx_byte(base, data); } -unsigned char uart_rx_byte(int idx) +unsigned char uart_rx_byte(unsigned int idx) { void *base = uart_platform_baseptr(idx); if (!base) @@ -125,7 +125,7 @@ return uart8250_mem_rx_byte(base); } -void uart_tx_flush(int idx) +void uart_tx_flush(unsigned int idx) { void *base = uart_platform_baseptr(idx); if (!base) diff --git a/src/include/console/uart.h b/src/include/console/uart.h index 9d37886..6126a89 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -35,14 +35,14 @@ /* Bitbang out one byte on an 8n1 UART through the output function set_tx(). */ void uart_bitbang_tx_byte(unsigned char data, void (*set_tx)(int line_state)); -void uart_init(int idx); -void uart_tx_byte(int idx, unsigned char data); -void uart_tx_flush(int idx); -unsigned char uart_rx_byte(int idx); +void uart_init(unsigned int idx); +void uart_tx_byte(unsigned int idx, unsigned char data); +void uart_tx_flush(unsigned int idx); +unsigned char uart_rx_byte(unsigned int idx); -uintptr_t uart_platform_base(int idx); +uintptr_t uart_platform_base(unsigned int idx); -static inline void *uart_platform_baseptr(int idx) +static inline void *uart_platform_baseptr(unsigned int idx) { return (void *)uart_platform_base(idx); } diff --git a/src/mainboard/emulation/qemu-aarch64/mmio.c b/src/mainboard/emulation/qemu-aarch64/mmio.c index 0cffc28..0fac64d 100644 --- a/src/mainboard/emulation/qemu-aarch64/mmio.c +++ b/src/mainboard/emulation/qemu-aarch64/mmio.c @@ -3,7 +3,7 @@ #include <console/uart.h> #include <mainboard/addressmap.h> -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { return VIRT_UART_BASE; } diff --git a/src/mainboard/emulation/qemu-armv7/mmio.c b/src/mainboard/emulation/qemu-armv7/mmio.c index 3f239153..0f07e7f 100644 --- a/src/mainboard/emulation/qemu-armv7/mmio.c +++ b/src/mainboard/emulation/qemu-armv7/mmio.c @@ -4,7 +4,7 @@ #define VEXPRESS_UART0_IO_ADDRESS (0x10009000) -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { return VEXPRESS_UART0_IO_ADDRESS; } diff --git a/src/mainboard/emulation/qemu-power8/uart.c b/src/mainboard/emulation/qemu-power8/uart.c index c6d7e40..4b1bf32 100644 --- a/src/mainboard/emulation/qemu-power8/uart.c +++ b/src/mainboard/emulation/qemu-power8/uart.c @@ -5,26 +5,26 @@ #include <boot/coreboot_tables.h> static uint8_t *buf = (void *)0; -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { return (uintptr_t) buf; } -void uart_init(int idx) +void uart_init(unsigned int idx) { } -unsigned char uart_rx_byte(int idx) +unsigned char uart_rx_byte(unsigned int idx) { return 0; } -void uart_tx_byte(int idx, unsigned char data) +void uart_tx_byte(unsigned int idx, unsigned char data) { } -void uart_tx_flush(int idx) +void uart_tx_flush(unsigned int idx) { } diff --git a/src/mainboard/emulation/qemu-riscv/uart.c b/src/mainboard/emulation/qemu-riscv/uart.c index 4eee12b..19a2b00 100644 --- a/src/mainboard/emulation/qemu-riscv/uart.c +++ b/src/mainboard/emulation/qemu-riscv/uart.c @@ -4,7 +4,7 @@ #include <console/uart.h> #include <mainboard/addressmap.h> -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { return (uintptr_t) QEMU_VIRT_UART0; } diff --git a/src/mainboard/emulation/spike-riscv/uart.c b/src/mainboard/emulation/spike-riscv/uart.c index d6e0510..efefc52 100644 --- a/src/mainboard/emulation/spike-riscv/uart.c +++ b/src/mainboard/emulation/spike-riscv/uart.c @@ -3,7 +3,7 @@ #include <types.h> #include <console/uart.h> -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { return (uintptr_t) 0x02100000; } diff --git a/src/soc/amd/picasso/uart_console.c b/src/soc/amd/picasso/uart_console.c index 3ab2a70..b5c5159 100644 --- a/src/soc/amd/picasso/uart_console.c +++ b/src/soc/amd/picasso/uart_console.c @@ -8,7 +8,7 @@ * be provided exactly once and only by the UART that is used for console. */ -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { return get_uart_base(idx); } diff --git a/src/soc/amd/stoneyridge/uart.c b/src/soc/amd/stoneyridge/uart.c index ab129c5..73346ab6 100644 --- a/src/soc/amd/stoneyridge/uart.c +++ b/src/soc/amd/stoneyridge/uart.c @@ -3,7 +3,7 @@ #include <console/uart.h> #include <soc/southbridge.h> -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { if (CONFIG_UART_FOR_CONSOLE < 0 || CONFIG_UART_FOR_CONSOLE > 1) return 0; diff --git a/src/soc/cavium/cn81xx/uart.c b/src/soc/cavium/cn81xx/uart.c index 03f94d5..4e5fd82 100644 --- a/src/soc/cavium/cn81xx/uart.c +++ b/src/soc/cavium/cn81xx/uart.c @@ -94,7 +94,7 @@ return uart_hclk(uart); } -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; } diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 5507663..142a936 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -37,7 +37,7 @@ } #if CONFIG(INTEL_LPSS_UART_FOR_CONSOLE) -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { if (idx == CONFIG_UART_FOR_CONSOLE) return CONFIG_CONSOLE_UART_BASE_ADDRESS; diff --git a/src/soc/intel/denverton_ns/uart_debug.c b/src/soc/intel/denverton_ns/uart_debug.c index 8ee02cc..acd1f03 100644 --- a/src/soc/intel/denverton_ns/uart_debug.c +++ b/src/soc/intel/denverton_ns/uart_debug.c @@ -8,9 +8,9 @@ #define MY_PCI_DEV(SEGBUS, DEV, FN) \ ((((SEGBUS)&0xFFF) << 20) | (((DEV)&0x1F) << 15) | (((FN)&0x07) << 12)) -uintptr_t uart_platform_base(int idx); +uintptr_t uart_platform_base(unsigned int idx); -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { return (uintptr_t)pci_io_read_config32( MY_PCI_DEV(0, CONFIG_HSUART_DEV, idx), diff --git a/src/soc/intel/quark/uart_common.c b/src/soc/intel/quark/uart_common.c index 8696277..19ca745 100644 --- a/src/soc/intel/quark/uart_common.c +++ b/src/soc/intel/quark/uart_common.c @@ -8,7 +8,7 @@ return 44236800; } -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { return UART_BASE_ADDRESS; } diff --git a/src/soc/mediatek/common/uart.c b/src/soc/mediatek/common/uart.c index 99cba13..ba3c71a 100644 --- a/src/soc/mediatek/common/uart.c +++ b/src/soc/mediatek/common/uart.c @@ -139,22 +139,22 @@ return (read8(&uart_ptr->lsr) & UART8250_LSR_DR) == UART8250_LSR_DR; } -void uart_init(int idx) +void uart_init(unsigned int idx) { mtk_uart_init(); } -unsigned char uart_rx_byte(int idx) +unsigned char uart_rx_byte(unsigned int idx) { return mtk_uart_rx_byte(); } -void uart_tx_byte(int idx, unsigned char data) +void uart_tx_byte(unsigned int idx, unsigned char data) { mtk_uart_tx_byte(data); } -void uart_tx_flush(int idx) +void uart_tx_flush(unsigned int idx) { mtk_uart_tx_flush(); } diff --git a/src/soc/nvidia/tegra124/uart.c b/src/soc/nvidia/tegra124/uart.c index d016cc2..4f24c0d 100644 --- a/src/soc/nvidia/tegra124/uart.c +++ b/src/soc/nvidia/tegra124/uart.c @@ -76,12 +76,12 @@ return (read8(&uart_ptr->lsr) & UART8250_LSR_DR) == UART8250_LSR_DR; } -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { //Default to UART A unsigned int base = 0x70006000; //UARTs A - E are mapped as index 0 - 4 - if ((idx < 5) && (idx >= 0)) { + if ((idx < 5)) { if (idx != 1) { //not UART B base += idx * 0x100; } else { @@ -91,25 +91,25 @@ return base; } -void uart_init(int idx) +void uart_init(unsigned int idx) { struct tegra124_uart *uart_ptr = uart_platform_baseptr(idx); tegra124_uart_init(uart_ptr); } -unsigned char uart_rx_byte(int idx) +unsigned char uart_rx_byte(unsigned int idx) { struct tegra124_uart *uart_ptr = uart_platform_baseptr(idx); return tegra124_uart_rx_byte(uart_ptr); } -void uart_tx_byte(int idx, unsigned char data) +void uart_tx_byte(unsigned int idx, unsigned char data) { struct tegra124_uart *uart_ptr = uart_platform_baseptr(idx); tegra124_uart_tx_byte(uart_ptr, data); } -void uart_tx_flush(int idx) +void uart_tx_flush(unsigned int idx) { struct tegra124_uart *uart_ptr = uart_platform_baseptr(idx); tegra124_uart_tx_flush(uart_ptr); diff --git a/src/soc/nvidia/tegra210/uart.c b/src/soc/nvidia/tegra210/uart.c index 865e1fa..7dbaf7b 100644 --- a/src/soc/nvidia/tegra210/uart.c +++ b/src/soc/nvidia/tegra210/uart.c @@ -82,22 +82,22 @@ return (read8(&uart_ptr->lsr) & UART8250_LSR_DR) == UART8250_LSR_DR; } -void uart_init(int idx) +void uart_init(unsigned int idx) { tegra210_uart_init(); } -void uart_tx_byte(int idx, unsigned char data) +void uart_tx_byte(unsigned int idx, unsigned char data) { tegra210_uart_tx_byte(data); } -void uart_tx_flush(int idx) +void uart_tx_flush(unsigned int idx) { tegra210_uart_tx_flush(); } -unsigned char uart_rx_byte(int idx) +unsigned char uart_rx_byte(unsigned int idx) { return tegra210_uart_rx_byte(); } diff --git a/src/soc/qualcomm/ipq40xx/uart.c b/src/soc/qualcomm/ipq40xx/uart.c index 265c25e..9c50611 100644 --- a/src/soc/qualcomm/ipq40xx/uart.c +++ b/src/soc/qualcomm/ipq40xx/uart.c @@ -87,7 +87,7 @@ /* Received data */ static unsigned int word = 0; -void uart_tx_byte(int idx, unsigned char data) +void uart_tx_byte(unsigned int idx, unsigned char data) { int num_of_chars = 1; void *base = uart_board_param.uart_dm_base; @@ -195,7 +195,7 @@ * * Initializes clocks, GPIO and UART controller. */ -void uart_init(int idx) +void uart_init(unsigned int idx) { /* Note int idx isn't used in this driver. */ void *dm_base; @@ -230,7 +230,7 @@ * @brief uart_tx_flush - transmits a string of data * @param idx: string to transmit */ -void uart_tx_flush(int idx) +void uart_tx_flush(unsigned int idx) { void *base = uart_board_param.uart_dm_base; @@ -244,7 +244,7 @@ * * Returns the character read from serial port. */ -uint8_t uart_rx_byte(int idx) +uint8_t uart_rx_byte(unsigned int idx) { uint8_t byte; diff --git a/src/soc/qualcomm/ipq806x/uart.c b/src/soc/qualcomm/ipq806x/uart.c index ea564b3..3a3a8bf 100644 --- a/src/soc/qualcomm/ipq806x/uart.c +++ b/src/soc/qualcomm/ipq806x/uart.c @@ -160,7 +160,7 @@ } #endif -void uart_tx_byte(int idx, unsigned char data) +void uart_tx_byte(unsigned int idx, unsigned char data) { int num_of_chars = 1; unsigned int tx_data = 0; @@ -269,7 +269,7 @@ * * Initializes clocks, GPIO and UART controller. */ -void uart_init(int idx) +void uart_init(unsigned int idx) { /* Note int idx isn't used in this driver. */ void *dm_base; @@ -316,7 +316,7 @@ * uart_tx_flush - transmits a string of data * @s: string to transmit */ -void uart_tx_flush(int idx) +void uart_tx_flush(unsigned int idx) { void *base = uart_board_param.uart_dm_base; @@ -351,7 +351,7 @@ * * Returns the character read from serial port. */ -uint8_t uart_rx_byte(int idx) +uint8_t uart_rx_byte(unsigned int idx) { uint8_t byte; diff --git a/src/soc/qualcomm/qcs405/uart.c b/src/soc/qualcomm/qcs405/uart.c index 1229053..ac72998 100644 --- a/src/soc/qualcomm/qcs405/uart.c +++ b/src/soc/qualcomm/qcs405/uart.c @@ -90,7 +90,7 @@ static unsigned int word = 0; -void uart_tx_byte(int idx, unsigned char data) +void uart_tx_byte(unsigned int idx, unsigned char data) { int num_of_chars = 1; void *base = uart_board_param.uart_dm_base; @@ -199,7 +199,7 @@ * * Initializes clocks, GPIO and UART controller. */ -void uart_init(int idx) +void uart_init(unsigned int idx) { /* Note int idx isn't used in this driver. */ void *dm_base; @@ -231,7 +231,7 @@ * @brief uart_tx_flush - transmits a string of data * @param idx: string to transmit */ -void uart_tx_flush(int idx) +void uart_tx_flush(unsigned int idx) { void *base = uart_board_param.uart_dm_base; @@ -246,7 +246,7 @@ * * Returns the character read from serial port. */ -uint8_t uart_rx_byte(int idx) +uint8_t uart_rx_byte(unsigned int idx) { uint8_t byte; diff --git a/src/soc/qualcomm/sc7180/qupv3_uart.c b/src/soc/qualcomm/sc7180/qupv3_uart.c index f9d99bb..bf274c2 100644 --- a/src/soc/qualcomm/sc7180/qupv3_uart.c +++ b/src/soc/qualcomm/sc7180/qupv3_uart.c @@ -34,7 +34,7 @@ #define UART_RX_PACK_VECTOR0 0xF #define UART_RX_PACK_VECTOR2 0x00 -void uart_tx_flush(int idx) +void uart_tx_flush(unsigned int idx) { struct qup_regs *regs = qup[idx].regs; @@ -43,7 +43,7 @@ ; } -void uart_init(int idx) +void uart_init(unsigned int idx) { struct qup_regs *regs = qup[idx].regs; unsigned int reg_value; @@ -113,7 +113,7 @@ write32(&regs->geni_s_cmd0, START_UART_RX); } -unsigned char uart_rx_byte(int idx) +unsigned char uart_rx_byte(unsigned int idx) { struct qup_regs *regs = qup[idx].regs; @@ -122,7 +122,7 @@ return 0; } -void uart_tx_byte(int idx, unsigned char data) +void uart_tx_byte(unsigned int idx, unsigned char data) { struct qup_regs *regs = qup[idx].regs; @@ -134,7 +134,7 @@ write32(&regs->geni_tx_fifon, data); } -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { return (uintptr_t)qup[idx].regs; } diff --git a/src/soc/qualcomm/sc7180/uart_bitbang.c b/src/soc/qualcomm/sc7180/uart_bitbang.c index b3a6cd5..7d88a20 100644 --- a/src/soc/qualcomm/sc7180/uart_bitbang.c +++ b/src/soc/qualcomm/sc7180/uart_bitbang.c @@ -16,22 +16,22 @@ gpio_set(UART_TX_PIN, line_state); } -void uart_init(int idx) +void uart_init(unsigned int idx) { gpio_output(UART_TX_PIN, 1); } -void uart_tx_byte(int idx, unsigned char data) +void uart_tx_byte(unsigned int idx, unsigned char data) { uart_bitbang_tx_byte(data, set_tx); } -void uart_tx_flush(int idx) +void uart_tx_flush(unsigned int idx) { /* unnecessary, PIO Tx means transaction is over when tx_byte returns */ } -unsigned char uart_rx_byte(int idx) +unsigned char uart_rx_byte(unsigned int idx) { return 0; /* not implemented */ } diff --git a/src/soc/qualcomm/sdm845/uart_bitbang.c b/src/soc/qualcomm/sdm845/uart_bitbang.c index b78db83..8d7138e 100644 --- a/src/soc/qualcomm/sdm845/uart_bitbang.c +++ b/src/soc/qualcomm/sdm845/uart_bitbang.c @@ -10,22 +10,22 @@ gpio_set(UART_TX_PIN, line_state); } -void uart_init(int idx) +void uart_init(unsigned int idx) { gpio_output(UART_TX_PIN, 1); } -void uart_tx_byte(int idx, unsigned char data) +void uart_tx_byte(unsigned int idx, unsigned char data) { uart_bitbang_tx_byte(data, set_tx); } -void uart_tx_flush(int idx) +void uart_tx_flush(unsigned int idx) { /* unnecessary, PIO Tx means transaction is over when tx_byte returns */ } -unsigned char uart_rx_byte(int idx) +unsigned char uart_rx_byte(unsigned int idx) { return 0; /* not implemented */ } diff --git a/src/soc/rockchip/common/uart.c b/src/soc/rockchip/common/uart.c index 2c6d6ce..b98f182 100644 --- a/src/soc/rockchip/common/uart.c +++ b/src/soc/rockchip/common/uart.c @@ -9,7 +9,7 @@ return OSC_HZ; } -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; } diff --git a/src/soc/samsung/exynos5250/uart.c b/src/soc/samsung/exynos5250/uart.c index 3263125..ef03c04 100644 --- a/src/soc/samsung/exynos5250/uart.c +++ b/src/soc/samsung/exynos5250/uart.c @@ -100,7 +100,7 @@ while (read32(&uart->ufstat) & 0x1ff0000); } -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { if (idx < 4) return 0x12c00000 + idx * 0x10000; @@ -108,25 +108,25 @@ return 0; } -void uart_init(int idx) +void uart_init(unsigned int idx) { struct s5p_uart *uart = uart_platform_baseptr(idx); exynos5_init_dev(uart); } -unsigned char uart_rx_byte(int idx) +unsigned char uart_rx_byte(unsigned int idx) { struct s5p_uart *uart = uart_platform_baseptr(idx); return exynos5_uart_rx_byte(uart); } -void uart_tx_byte(int idx, unsigned char data) +void uart_tx_byte(unsigned int idx, unsigned char data) { struct s5p_uart *uart = uart_platform_baseptr(idx); exynos5_uart_tx_byte(uart, data); } -void uart_tx_flush(int idx) +void uart_tx_flush(unsigned int idx) { struct s5p_uart *uart = uart_platform_baseptr(idx); exynos5_uart_tx_flush(uart); diff --git a/src/soc/samsung/exynos5420/uart.c b/src/soc/samsung/exynos5420/uart.c index c7a0649..16a4b11 100644 --- a/src/soc/samsung/exynos5420/uart.c +++ b/src/soc/samsung/exynos5420/uart.c @@ -92,7 +92,7 @@ write8(&uart->utxh, data); } -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { if (idx < 4) return 0x12c00000 + idx * 0x10000; @@ -100,25 +100,25 @@ return 0; } -void uart_init(int idx) +void uart_init(unsigned int idx) { struct s5p_uart *uart = uart_platform_baseptr(idx); exynos5_init_dev(uart); } -unsigned char uart_rx_byte(int idx) +unsigned char uart_rx_byte(unsigned int idx) { struct s5p_uart *uart = uart_platform_baseptr(idx); return exynos5_uart_rx_byte(uart); } -void uart_tx_byte(int idx, unsigned char data) +void uart_tx_byte(unsigned int idx, unsigned char data) { struct s5p_uart *uart = uart_platform_baseptr(idx); exynos5_uart_tx_byte(uart, data); } -void uart_tx_flush(int idx) +void uart_tx_flush(unsigned int idx) { /* Exynos5250 implements this too. */ } diff --git a/src/soc/sifive/fu540/uart.c b/src/soc/sifive/fu540/uart.c index c35e0f6..353f6cd 100644 --- a/src/soc/sifive/fu540/uart.c +++ b/src/soc/sifive/fu540/uart.c @@ -6,7 +6,7 @@ #include <soc/addressmap.h> #include <soc/clock.h> -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { if (idx < 2) return FU540_UART(idx); diff --git a/src/soc/ti/am335x/uart.c b/src/soc/ti/am335x/uart.c index 90095d4..e3648a9 100644 --- a/src/soc/ti/am335x/uart.c +++ b/src/soc/ti/am335x/uart.c @@ -135,7 +135,7 @@ return 48000000; } -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { const unsigned int bases[] = { 0x44e09000, 0x48022000, 0x48024000, @@ -146,7 +146,7 @@ return 0; } -void uart_init(int idx) +void uart_init(unsigned int idx) { struct am335x_uart *uart = uart_platform_baseptr(idx); uint16_t div = (uint16_t) uart_baudrate_divisor( @@ -154,19 +154,19 @@ am335x_uart_init(uart, div); } -unsigned char uart_rx_byte(int idx) +unsigned char uart_rx_byte(unsigned int idx) { struct am335x_uart *uart = uart_platform_baseptr(idx); return am335x_uart_rx_byte(uart); } -void uart_tx_byte(int idx, unsigned char data) +void uart_tx_byte(unsigned int idx, unsigned char data) { struct am335x_uart *uart = uart_platform_baseptr(idx); am335x_uart_tx_byte(uart, data); } -void uart_tx_flush(int idx) +void uart_tx_flush(unsigned int idx) { } diff --git a/src/southbridge/amd/pi/hudson/uart.c b/src/southbridge/amd/pi/hudson/uart.c index 2d28210..996215d 100644 --- a/src/southbridge/amd/pi/hudson/uart.c +++ b/src/southbridge/amd/pi/hudson/uart.c @@ -2,7 +2,7 @@ #include <console/uart.h> -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { return (uintptr_t)(0xFEDC6000 + 0x2000 * (idx & 1)); } -- To view, visit https://review.coreboot.org/c/coreboot/+/45294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64bd60bd2a3b82552cb3ac6524792b9ac6c09a94 Gerrit-Change-Number: 45294 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: soc/amd/picasso/uart: make index parameters unsigned
by Felix Held (Code Review) 12 Sep '20

12 Sep '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45292 ) Change subject: soc/amd/picasso/uart: make index parameters unsigned ...................................................................... soc/amd/picasso/uart: make index parameters unsigned The UART index is never negative, so make it unsigned and drop the check for the index to be non-negative. BRANCH=zork Change-Id: I38b5dad87f8af4fbe8ee1d919230efe48f68686c Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/include/soc/uart.h M src/soc/amd/picasso/uart.c 2 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/45292/1 diff --git a/src/soc/amd/picasso/include/soc/uart.h b/src/soc/amd/picasso/include/soc/uart.h index 3aac936..4e5619f 100644 --- a/src/soc/amd/picasso/include/soc/uart.h +++ b/src/soc/amd/picasso/include/soc/uart.h @@ -5,9 +5,9 @@ #include <types.h> -void set_uart_config(int idx); /* configure hardware of FCH UART selected by idx */ +void set_uart_config(unsigned int idx); /* configure hardware of FCH UART selected by idx */ void clear_uart_legacy_config(void); /* disable legacy I/O decode for FCH UART */ -uintptr_t get_uart_base(int idx); /* get MMIO base address of FCH UART */ +uintptr_t get_uart_base(unsigned int idx); /* get MMIO base address of FCH UART */ #endif /* __PICASSO_UART_H__ */ diff --git a/src/soc/amd/picasso/uart.c b/src/soc/amd/picasso/uart.c index d892333..0bf7eb8 100644 --- a/src/soc/amd/picasso/uart.c +++ b/src/soc/amd/picasso/uart.c @@ -32,9 +32,9 @@ } }, }; -uintptr_t get_uart_base(int idx) +uintptr_t get_uart_base(unsigned int idx) { - if (idx < 0 || idx >= ARRAY_SIZE(uart_info)) + if (idx >= ARRAY_SIZE(uart_info)) return 0; return uart_info[idx].base; @@ -45,12 +45,12 @@ write16((void *)FCH_UART_LEGACY_DECODE, 0); } -void set_uart_config(int idx) +void set_uart_config(unsigned int idx) { uint32_t uart_ctrl; uint16_t uart_leg; - if (idx < 0 || idx >= ARRAY_SIZE(uart_info)) + if (idx >= ARRAY_SIZE(uart_info)) return; program_gpios(uart_info[idx].mux, 2); -- To view, visit https://review.coreboot.org/c/coreboot/+/45292 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38b5dad87f8af4fbe8ee1d919230efe48f68686c Gerrit-Change-Number: 45292 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: mb/siemens/chili: Add Chili variant
by Nico Huber (Code Review) 12 Sep '20

12 Sep '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39995 ) Change subject: mb/siemens/chili: Add Chili variant ...................................................................... Patch Set 15: (4 comments) https://review.coreboot.org/c/coreboot/+/39995/15/src/mainboard/siemens/chi… File src/mainboard/siemens/chili/variants/chili/smbios.c: PS15: Please remove the whole file and use `SECUNET_DMI` instead. Kconfig select + devicetree entry. See boxer26 for reference. https://review.coreboot.org/c/coreboot/+/39995/1/src/mainboard/siemens/fiel… File src/mainboard/siemens/field_pg_m6/variants/chili/boxer26_eeprom.h: https://review.coreboot.org/c/coreboot/+/39995/1/src/mainboard/siemens/fiel… PS1, Line 6: BOXER26 > Is this Boxer26 though? Whole file will be dropped. https://review.coreboot.org/c/coreboot/+/39995/1/src/mainboard/siemens/fiel… File src/mainboard/siemens/field_pg_m6/variants/chili/smbios.c: https://review.coreboot.org/c/coreboot/+/39995/1/src/mainboard/siemens/fiel… PS1, Line 33: MAX_STRING_LENGTH); > nit: should fit in 96 chars Whole file will be dropped. https://review.coreboot.org/c/coreboot/+/39995/1/src/mainboard/siemens/fiel… PS1, Line 72: const int le) > fits? Whole file will be dropped. -- To view, visit https://review.coreboot.org/c/coreboot/+/39995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7a5dccbb0d5b7bceb154fb050cf991254475f7b Gerrit-Change-Number: 39995 Gerrit-PatchSet: 15 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 12 Sep 2020 11:09:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit September 2020