coreboot-gerrit September 2020

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Change in coreboot[master]: cpu/intel/model_1067x: enable PECI
by Michael Büchler (Code Review) 12 Sep '20

12 Sep '20

Michael Büchler has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45184 ) Change subject: cpu/intel/model_1067x: enable PECI ...................................................................... cpu/intel/model_1067x: enable PECI This is required for Super I/Os to be able to read the CPU temperature through PECI. On 45nm Core 2 CPUs (Wolfdale, Yorkfield) it is not enabled by default. This is probably related to erratum AW67 "Enabling PECI via the PECI_CTL MSR incorrectly writes CPUID_FEATURE_MASK1 MSR". The suggested workaround is "Do not initialize PECI before processor update is loaded". Since coreboot performs microcode updates before running this code it should not cause any trouble. It was tested on a Core 2 Duo E8400, stepping E0. PECI is already enabled by default on older (65nm) CPUs. Tested: Pentium Dual-Core E2160. See commit edac28ce65e48d6b2a0a2421d046a4fe4b2bf589 for the same change on cpu/intel/model_6fx. Signed-off-by: Michael Büchler <michael.buechler(a)posteo.net> Change-Id: I5a3ec033bd816665af4ecc82f7b167857cd7c1b6 --- M src/cpu/intel/model_1067x/model_1067x_init.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/45184/1 diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 6553f29..c59e1fc 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -166,6 +166,8 @@ wrmsr(MSR_EMTTM_CR_TABLE(5), msr); } +#define IA32_PECI_CTL 0x5a0 + static void configure_misc(const int eist, const int tm2, const int emttm) { msr_t msr; @@ -208,6 +210,11 @@ msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */ wrmsr(IA32_MISC_ENABLE, msr); } + + /* Enable PECI */ + msr = rdmsr(IA32_PECI_CTL); + msr.lo |= 1; + wrmsr(IA32_PECI_CTL, msr); } #define PIC_SENS_CFG 0x1aa -- To view, visit https://review.coreboot.org/c/coreboot/+/45184 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a3ec033bd816665af4ecc82f7b167857cd7c1b6 Gerrit-Change-Number: 45184 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Büchler <michael.buechler(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: mainboard: add Dell Latitude E7240
by Angel Pons (Code Review) 12 Sep '20

12 Sep '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40300 ) Change subject: mainboard: add Dell Latitude E7240 ...................................................................... Patch Set 3: (21 comments) https://review.coreboot.org/c/coreboot/+/40300/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/40300/3//COMMIT_MSG@11 PS3, Line 11: It boots from USB and mSATA > Microsoft Windows and GNU/Linux? Probably Linux for now. Windows in BIOS mode is very picky. Given that ACPI is still WIP, I'd say Windows is still untested. https://review.coreboot.org/c/coreboot/+/40300/3/Documentation/mainboard/de… File Documentation/mainboard/dell/latitude_e7240.md: https://review.coreboot.org/c/coreboot/+/40300/3/Documentation/mainboard/de… PS3, Line 31: when the IFD is unlocked That shouldn't be necessary to flash coreboot. Even flashrom says which command-line switch one should use to flash when a region is read-protected (--noverify-all). However, if the vendor firmware sets protected ranges, please mention so. https://review.coreboot.org/c/coreboot/+/40300/3/Documentation/mainboard/de… PS3, Line 37: not supported yet nit: `not yet supported` sounds better and seems to be more frequent (has over four times as many search results in Google) https://review.coreboot.org/c/coreboot/+/40300/3/Documentation/mainboard/de… PS3, Line 48: No internal display before booting to OS when connected with a dock Does this happen when using legacy VGA text mode with libgfxinit? https://review.coreboot.org/c/coreboot/+/40300/2/src/mainboard/dell/latitud… File src/mainboard/dell/latitude_e7240/Kconfig: https://review.coreboot.org/c/coreboot/+/40300/2/src/mainboard/dell/latitud… PS2, Line 6: select CPU_INTEL_HASWELL > CB:44976 removes this from in-tree mainboards Done https://review.coreboot.org/c/coreboot/+/40300/2/src/mainboard/dell/latitud… PS2, Line 20: default dell/latitude_e7240 > that is, guard the board directory with quotes, because newer Kconfig dislikes unquoted slashes: CB: […] Done https://review.coreboot.org/c/coreboot/+/40300/3/src/mainboard/dell/latitud… File src/mainboard/dell/latitude_e7240/board_info.txt: https://review.coreboot.org/c/coreboot/+/40300/3/src/mainboard/dell/latitud… PS3, Line 6: n flashrom works, though? https://review.coreboot.org/c/coreboot/+/40300/2/src/mainboard/dell/latitud… File src/mainboard/dell/latitude_e7240/bootblock.c: https://review.coreboot.org/c/coreboot/+/40300/2/src/mainboard/dell/latitud… PS2, Line 10: pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0x007c0901); > Uh, this will overwrite what `pch_enable_lpc` programmed (happens just before calling this function) […] Another option would be to use LPC_GEN4_DEC for this. It's not used in devicetree, so once you're done you can just clear it. https://review.coreboot.org/c/coreboot/+/40300/1/src/mainboard/dell/latitud… File src/mainboard/dell/latitude_e7240/devicetree.cb: https://review.coreboot.org/c/coreboot/+/40300/1/src/mainboard/dell/latitud… PS1, Line 101: Host bridge Host bridge > one Host bridge too much? Ack https://review.coreboot.org/c/coreboot/+/40300/1/src/mainboard/dell/latitud… PS1, Line 104: device pci 01.0 off # PCIe Bridge for discrete graphics : end > This does not exist on HSW-LP Done https://review.coreboot.org/c/coreboot/+/40300/2/src/mainboard/dell/latitud… File src/mainboard/dell/latitude_e7240/devicetree.cb: https://review.coreboot.org/c/coreboot/+/40300/2/src/mainboard/dell/latitud… PS2, Line 8: register "gpu_panel_port_select" = "0" > I'm going to kill this (it's reserved MBZ on haswell) Done https://review.coreboot.org/c/coreboot/+/40300/2/src/mainboard/dell/latitud… PS2, Line 47: (eSATA?) > Schematics say DOCK Done https://review.coreboot.org/c/coreboot/+/40300/2/src/mainboard/dell/latitud… PS2, Line 50: device pci 14.0 on end # xHCI Controller > nit: IMHO, having the `end` keywords aligned (one extra space for the "on" case) eases reading the d […] Done https://review.coreboot.org/c/coreboot/+/40300/2/src/mainboard/dell/latitud… PS2, Line 64: device pci 1c.6 off end # PCIe Port #7 : device pci 1c.7 off end # PCIe Port #8 > These devices don't exist on HSW-LP Done https://review.coreboot.org/c/coreboot/+/40300/3/src/mainboard/dell/latitud… File src/mainboard/dell/latitude_e7240/devicetree.cb: https://review.coreboot.org/c/coreboot/+/40300/3/src/mainboard/dell/latitud… PS3, Line 29: Host bridge Host bridge One host bridge too many? https://review.coreboot.org/c/coreboot/+/40300/3/src/mainboard/dell/latitud… File src/mainboard/dell/latitude_e7240/gma-mainboard.ads: https://review.coreboot.org/c/coreboot/+/40300/3/src/mainboard/dell/latitud… PS3, Line 14: eDP, You can try to place this first, so that the internal display is always the first to light up. Maybe it helps with the dock issue. https://review.coreboot.org/c/coreboot/+/40300/1/src/mainboard/dell/latitud… File src/mainboard/dell/latitude_e7240/gpio.c: https://review.coreboot.org/c/coreboot/+/40300/1/src/mainboard/dell/latitud… PS1, Line 8: LP_GPIO_OUT_LOW, /* 0: OUTPUT LOW */ > Maybe align with tabs? Ack https://review.coreboot.org/c/coreboot/+/40300/2/src/mainboard/dell/latitud… File src/mainboard/dell/latitude_e7240/gpio.c: https://review.coreboot.org/c/coreboot/+/40300/2/src/mainboard/dell/latitud… PS2, Line 6: LP_GPIO_OUT_LOW, /* 0: OUTPUT LOW */ > Instead of adding the GPIO number in comments, just use positional initializers for the array compon […] Done https://review.coreboot.org/c/coreboot/+/40300/2/src/mainboard/dell/latitud… PS2, Line 14: { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, .pirq = GPIO_PIRQ_APIC_ROUTE }, /* 8 */ > I'd define macros for these before the GPIO array, so as to make Jenkins happy and use one line per […] Using two lines is also reasonable, especially with the explicit array indices https://review.coreboot.org/c/coreboot/+/40300/2/src/mainboard/dell/latitud… PS2, Line 102: }; > Just add a final newline to make Jenkins happy. Done https://review.coreboot.org/c/coreboot/+/40300/2/src/superio/smsc/Makefile.… File src/superio/smsc/Makefile.inc: https://review.coreboot.org/c/coreboot/+/40300/2/src/superio/smsc/Makefile.… PS2, Line 16: subdirs-y += ece5048 > gosh, I'm not going to add this yet... Done -- To view, visit https://review.coreboot.org/c/coreboot/+/40300 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6933bdbcc8d0bbb85d62657624740266284ac71c Gerrit-Change-Number: 40300 Gerrit-PatchSet: 3 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 12 Sep 2020 09:35:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: build bot (Jenkins) <no-reply(a)coreboot.org> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: HAOUAS Elyes <ehaouas(a)noos.fr> Comment-In-Reply-To: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/system76/lemp9: correct interrupt pin used for ANX7411
by Michael Niewöhner (Code Review) 12 Sep '20

12 Sep '20

Hello Jeremy Soller, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45315 to look at the new patch set (#2). Change subject: mb/system76/lemp9: correct interrupt pin used for ANX7411 ...................................................................... mb/system76/lemp9: correct interrupt pin used for ANX7411 Instead of bein used as VBUS_SENSE interrupt, the pin INTP_OUT is used as interrupt for I2C/SMBus communication with the USB-C controller ANX7411. Configure the pad as GPI with APIC interrupt, that can be used by a driver for the ANX7411 later. Change-Id: Id01d3b44d5953646c9fb06642ee6625ee13d1ba0 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/system76/lemp9/gpio.h 1 file changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/45315/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45315 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id01d3b44d5953646c9fb06642ee6625ee13d1ba0 Gerrit-Change-Number: 45315 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: system76/lemp9: correct interrupt pin used for ANX7411
by Michael Niewöhner (Code Review) 12 Sep '20

12 Sep '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45315 ) Change subject: system76/lemp9: correct interrupt pin used for ANX7411 ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/45315 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id01d3b44d5953646c9fb06642ee6625ee13d1ba0 Gerrit-Change-Number: 45315 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Comment-Date: Sat, 12 Sep 2020 09:01:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard: add Dell Latitude E7240
by Paul Menzel (Code Review) 12 Sep '20

12 Sep '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40300 ) Change subject: mainboard: add Dell Latitude E7240 ...................................................................... Patch Set 3: (2 comments) https://review.coreboot.org/c/coreboot/+/40300/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/40300/3//COMMIT_MSG@11 PS3, Line 11: It boots from USB and mSATA Microsoft Windows and GNU/Linux? https://review.coreboot.org/c/coreboot/+/40300/3//COMMIT_MSG@11 PS3, Line 11: SeaBIOS What version? -- To view, visit https://review.coreboot.org/c/coreboot/+/40300 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6933bdbcc8d0bbb85d62657624740266284ac71c Gerrit-Change-Number: 40300 Gerrit-PatchSet: 3 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 12 Sep 2020 08:17:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard: add Dell Latitude E7240
by Iru Cai (vimacs) (Code Review) 12 Sep '20

12 Sep '20

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Iru Cai, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/40300 to look at the new patch set (#3). Change subject: mainboard: add Dell Latitude E7240 ...................................................................... mainboard: add Dell Latitude E7240 Based on autoport output. It boots from USB and mSATA with SeaBIOS. Change-Id: I6933bdbcc8d0bbb85d62657624740266284ac71c Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- A Documentation/mainboard/dell/latitude_e7240.md M Documentation/mainboard/index.md A src/mainboard/dell/latitude_e7240/Kconfig A src/mainboard/dell/latitude_e7240/Kconfig.name A src/mainboard/dell/latitude_e7240/Makefile.inc A src/mainboard/dell/latitude_e7240/acpi/ec.asl A src/mainboard/dell/latitude_e7240/acpi/platform.asl A src/mainboard/dell/latitude_e7240/acpi/superio.asl A src/mainboard/dell/latitude_e7240/acpi_tables.c A src/mainboard/dell/latitude_e7240/board_info.txt A src/mainboard/dell/latitude_e7240/bootblock.c A src/mainboard/dell/latitude_e7240/devicetree.cb A src/mainboard/dell/latitude_e7240/dsdt.asl A src/mainboard/dell/latitude_e7240/gma-mainboard.ads A src/mainboard/dell/latitude_e7240/gpio.c A src/mainboard/dell/latitude_e7240/hda_verb.c A src/mainboard/dell/latitude_e7240/mainboard.c A src/mainboard/dell/latitude_e7240/romstage.c 18 files changed, 506 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/40300/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/40300 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6933bdbcc8d0bbb85d62657624740266284ac71c Gerrit-Change-Number: 40300 Gerrit-PatchSet: 3 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/roda/rk886ex: Use PNP_IDX_EN instead of magic number
by HAOUAS Elyes (Code Review) 12 Sep '20

12 Sep '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44841 ) Change subject: mb/roda/rk886ex: Use PNP_IDX_EN instead of magic number ...................................................................... mb/roda/rk886ex: Use PNP_IDX_EN instead of magic number Change-Id: Ic8b5d94f8fb321d02400247ef86b4725a067ba76 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/roda/rk886ex/early_init.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/44841/1 diff --git a/src/mainboard/roda/rk886ex/early_init.c b/src/mainboard/roda/rk886ex/early_init.c index 21f115c..37682d6 100644 --- a/src/mainboard/roda/rk886ex/early_init.c +++ b/src/mainboard/roda/rk886ex/early_init.c @@ -4,6 +4,7 @@ #include <stdint.h> #include <arch/io.h> #include <cf9_reset.h> +#include <device/pnp_def.h> #include <device/pnp_ops.h> #include <device/pci_ops.h> #include <device/pci_def.h> @@ -50,7 +51,7 @@ pnp_write_config(dev, 0x27, (6 << 4) | 7); /* FDC + PP DMA */ pnp_write_config(dev, 0x28, (4 << 4) | 3); /* UART1,2 IRQ */ /* These are the SMI status registers in the SIO: */ - pnp_write_config(dev, 0x30, (0x600 >> 4)); /* Runtime Register Block Base */ + pnp_write_config(dev, PNP_IDX_EN, (0x600 >> 4)); /* Runtime Register Block Base */ pnp_write_config(dev, 0x31, 0x00); /* GPIO1 DIR */ pnp_write_config(dev, 0x32, 0x00); /* GPIO1 POL */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44841 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8b5d94f8fb321d02400247ef86b4725a067ba76 Gerrit-Change-Number: 44841 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/getac/p470: Use PNP_IDX_EN instead of magic number
by HAOUAS Elyes (Code Review) 12 Sep '20

12 Sep '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44837 ) Change subject: mb/getac/p470: Use PNP_IDX_EN instead of magic number ...................................................................... mb/getac/p470: Use PNP_IDX_EN instead of magic number Change-Id: Ie75e29ed307647f20a5b74deb6d998278fb99b7d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/getac/p470/early_init.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/44837/1 diff --git a/src/mainboard/getac/p470/early_init.c b/src/mainboard/getac/p470/early_init.c index 087e279..c003d48 100644 --- a/src/mainboard/getac/p470/early_init.c +++ b/src/mainboard/getac/p470/early_init.c @@ -3,6 +3,7 @@ #include <bootblock_common.h> #include <stdint.h> #include <arch/io.h> +#include <device/pnp_def.h> #include <device/pnp_ops.h> #include <device/pci_ops.h> #include <option.h> @@ -75,7 +76,7 @@ pnp_write_config(dev, 0x24, (0x3f8 >> 2)); // UART1 base pnp_write_config(dev, 0x28, (4 << 4) | 0); // UART1,2 IRQ pnp_write_config(dev, 0x2c, 0); // DMA0 FIR - pnp_write_config(dev, 0x30, (0x600 >> 4)); // Runtime Register Block Base + pnp_write_config(dev, PNP_IDX_EN, (0x600 >> 4)); // Runtime Register Block Base pnp_write_config(dev, 0x31, 0xce); // GPIO1 DIR pnp_write_config(dev, 0x32, 0x00); // GPIO1 POL -- To view, visit https://review.coreboot.org/c/coreboot/+/44837 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie75e29ed307647f20a5b74deb6d998278fb99b7d Gerrit-Change-Number: 44837 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/biostar/am1ml: Use 'PNP_IDX_*' instead of magic numbers
by HAOUAS Elyes (Code Review) 12 Sep '20

12 Sep '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44836 ) Change subject: mb/biostar/am1ml: Use 'PNP_IDX_*' instead of magic numbers ...................................................................... mb/biostar/am1ml: Use 'PNP_IDX_*' instead of magic numbers Change-Id: I5eaf33558e14f63045928215d88d2ad2554fdbf2 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/biostar/am1ml/bootblock.c 1 file changed, 13 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/44836/1 diff --git a/src/mainboard/biostar/am1ml/bootblock.c b/src/mainboard/biostar/am1ml/bootblock.c index 688f25d..405271b 100644 --- a/src/mainboard/biostar/am1ml/bootblock.c +++ b/src/mainboard/biostar/am1ml/bootblock.c @@ -2,6 +2,7 @@ #include <amdblocks/acpimmio.h> #include <bootblock_common.h> +#include <device/pnp_def.h> #include <device/pnp_ops.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8728f/it8728f.h> @@ -14,13 +15,13 @@ { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); - pnp_write_config(dev, 0xf1, 0x40); - pnp_write_config(dev, 0xf4, 0x80); - pnp_write_config(dev, 0xf5, 0x00); - pnp_write_config(dev, 0xf6, 0xf0); - pnp_write_config(dev, 0xf9, 0x48); - pnp_write_config(dev, 0xfa, 0x00); - pnp_write_config(dev, 0xfb, 0x00); + pnp_write_config(dev, PNP_IDX_MSC1, 0x40); + pnp_write_config(dev, PNP_IDX_MSC4, 0x80); + pnp_write_config(dev, PNP_IDX_MSC5, 0x00); + pnp_write_config(dev, PNP_IDX_MSC6, 0xf0); + pnp_write_config(dev, PNP_IDX_MSC9, 0x48); + pnp_write_config(dev, PNP_IDX_MSCA, 0x00); + pnp_write_config(dev, PNP_IDX_MSCB, 0x00); pnp_exit_conf_state(dev); } @@ -32,7 +33,7 @@ pnp_write_config(dev, 0x26, 0x07); pnp_write_config(dev, 0x28, 0x81); pnp_write_config(dev, 0x2c, 0x06); - pnp_write_config(dev, 0x72, 0x00); + pnp_write_config(dev, PNP_IDX_IRQ1, 0x00); pnp_write_config(dev, 0x73, 0x00); pnp_write_config(dev, 0xb3, 0x01); pnp_write_config(dev, 0xb8, 0x00); @@ -41,10 +42,10 @@ pnp_write_config(dev, 0xc8, 0x00); pnp_write_config(dev, 0xc9, 0x07); pnp_write_config(dev, 0xcb, 0x01); - pnp_write_config(dev, 0xf0, 0x10); - pnp_write_config(dev, 0xf4, 0x27); - pnp_write_config(dev, 0xf8, 0x20); - pnp_write_config(dev, 0xf9, 0x01); + pnp_write_config(dev, PNP_IDX_MSC0, 0x10); + pnp_write_config(dev, PNP_IDX_MSC4, 0x27); + pnp_write_config(dev, PNP_IDX_MSC8, 0x20); + pnp_write_config(dev, PNP_IDX_MSC9, 0x01); pnp_exit_conf_state(dev); } -- To view, visit https://review.coreboot.org/c/coreboot/+/44836 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5eaf33558e14f63045928215d88d2ad2554fdbf2 Gerrit-Change-Number: 44836 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/kontron/986lcd-m: Use ''PNP_IDX_*' instead of magic numbers
by HAOUAS Elyes (Code Review) 12 Sep '20

12 Sep '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44838 ) Change subject: mb/kontron/986lcd-m: Use ''PNP_IDX_*' instead of magic numbers ...................................................................... mb/kontron/986lcd-m: Use ''PNP_IDX_*' instead of magic numbers Change-Id: Ic7c1b4defa8c65ed739b1cf3861087cd53cd997c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/kontron/986lcd-m/early_init.c 1 file changed, 5 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/44838/1 diff --git a/src/mainboard/kontron/986lcd-m/early_init.c b/src/mainboard/kontron/986lcd-m/early_init.c index 37bb968..9022198 100644 --- a/src/mainboard/kontron/986lcd-m/early_init.c +++ b/src/mainboard/kontron/986lcd-m/early_init.c @@ -63,7 +63,7 @@ dev = PNP_DEV(0x2e, W83627THG_GAME_MIDI_GPIO1); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); - pnp_write_config(dev, 0xf5, 0xff); /* invert all GPIOs */ + pnp_write_config(dev, PNP_IDX_MSC5, 0xff); /* invert all GPIOs */ pnp_set_enable(dev, 1); dev = PNP_DEV(0x2e, W83627THG_GPIO2); @@ -73,9 +73,10 @@ dev = PNP_DEV(0x2e, W83627THG_GPIO3); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); - pnp_write_config(dev, 0xf0, 0xfb); /* GPIO bit 2 is output */ - pnp_write_config(dev, 0xf1, 0x00); /* GPIO bit 2 is 0 */ - pnp_write_config(dev, 0x30, 0x03); /* Enable GPIO3+4. pnp_set_enable is not sufficient */ + pnp_write_config(dev, PNP_IDX_MSC0, 0xfb); /* GPIO bit 2 is output */ + pnp_write_config(dev, PNP_IDX_MSC1, 0x00); /* GPIO bit 2 is 0 */ + /* Enable GPIO3+4. pnp_set_enable is not sufficient */ + pnp_write_config(dev, PNP_IDX_EN, 0x03); dev = PNP_DEV(0x2e, W83627THG_FDC); pnp_set_logical_device(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/44838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7c1b4defa8c65ed739b1cf3861087cd53cd997c Gerrit-Change-Number: 44838 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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