Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44814 )
Change subject: Documentation: Add ASan documentation
......................................................................
Patch Set 7: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/44814/7/Documentation/technotes/as…
File Documentation/technotes/asan.md:
https://review.coreboot.org/c/coreboot/+/44814/7/Documentation/technotes/as…
PS7, Line 283: 1/8th of the
: program memory
> It might be worth explaining somewhere why it has to be this way (in the code or in the docs)?
Because currently every program byte is monitored by a single bit in the shadow memory?
If you follow the above mentioned link to ASan (https://github.com/google/sanitizers/wiki/AddressSanitizer) and from there to
"AddressSanitizerAlgorithm -- if you are curious how it works."
you will find in the description:
"AddressSanitizer maps 8 bytes of the application memory into 1 byte of the shadow memory."
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Gerrit-Change-Id: I710ea495798597189941620c7e48fd5aa7476781
Gerrit-Change-Number: 44814
Gerrit-PatchSet: 7
Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
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Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45048 )
Change subject: sb/intel/lynxpoint/acpi: Do not determine PCH type at runtime
......................................................................
sb/intel/lynxpoint/acpi: Do not determine PCH type at runtime
Both PCH types are very different, and mixing the code for both together
isn't useful. Make `ISLP` return a constant, so that IASL can fold it.
Change-Id: I6222d6661115d444d4dad0217c2d376dc551465c
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/southbridge/intel/lynxpoint/acpi/pch.asl
1 file changed, 1 insertion(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/45048/1
diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl
index e1bd64f..154633d 100644
--- a/src/southbridge/intel/lynxpoint/acpi/pch.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl
@@ -7,11 +7,7 @@
// Return TRUE if chipset is LynxPoint-LP
Method (ISLP, 0, NotSerialized)
{
- If (LEqual (\_SB.PCI0.LPCB.DIDH, 0x9c)) {
- Return (1)
- } else {
- Return (0)
- }
+ Return (CONFIG(INTEL_LYNXPOINT_LP))
}
// IO-Trap at 0x800. This is the ACPI->SMI communication interface.
--
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Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44973 )
Change subject: src/vendorcode/intel/fsp/fsp2_0/cpx-sp: add prev boot error info HOB header file
......................................................................
src/vendorcode/intel/fsp/fsp2_0/cpx-sp: add prev boot error info HOB header file
PREV_BOOT_ERR_SRC_HOB is generated by CPX-SP FSP by interrogating
error status registered (such as MCA MSRs) to list fatal errors happened
during the previous boot session.
The header file supports 3 different error source types. CPX-SP FSP
supports only McBankType.
Change-Id: I9b88af17075b98e88c7e94e55fea37627ec03cd0
Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com>
---
A src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_prevbooterr.h
1 file changed, 83 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/44973/1
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_prevbooterr.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_prevbooterr.h
new file mode 100644
index 0000000..9241692
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_prevbooterr.h
@@ -0,0 +1,83 @@
+/**
+Copyright (c) 2019-2020, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+**/
+
+
+#ifndef _PREV_BOOT_ERR_SRC_GUID_H_
+#define _PREV_BOOT_ERR_SRC_GUID_H_
+
+#define FSP_PREV_BOOT_ERR_SRC_HOB_GUID { \
+ 0xc5, 0xb5, 0x38, 0x51, 0x69, 0x93, 0xec, 0x48, 0x5b, 0x97, \
+ 0x38, 0xa2, 0xf7, 0x09, 0x66, 0x75 \
+ }
+
+#define PREV_BOOT_ERR_SRC_HOB_SIZE 1000
+
+typedef struct {
+UINT16 Length; // Actual size of the error sources used in the HOB
+UINT8 HobData[PREV_BOOT_ERR_SRC_HOB_SIZE -2]; // List of Error source structures of format //MCBANK_ERR_INFO or CSR_ERR_INFO
+}PREV_BOOT_ERR_SRC_HOB;
+
+typedef struct{
+UINT8 Type; // McBankType = 1;
+UINT8 Segment;
+UINT8 Socket;
+UINT16 ApicId; // ApicId is Needed only if it a core McBank.
+UINT16 McBankNum;
+UINT64 McBankStatus;
+UINT64 McbankAddr;
+UINT64 McBankMisc;
+} MCBANK_ERR_INFO;
+
+typedef struct {
+UINT8 Type; // PciExType =2 ;
+UINT8 Segment;
+UINT8 Bus;
+UINT8 Device;
+UINT8 Function;
+UINT32 AerUncErrSts;
+UINT8 AerHdrLogData[16];
+} PCI_EX_ERR_INFO;
+
+typedef struct {
+UINT8 Type; // Other Csr error type =3 ;
+UINT8 Segment;
+UINT8 Bus;
+UINT8 Device;
+UINT8 Function;
+UINT16 offset;
+UINT32 Value;
+} CSR_ERR_INFO;
+
+typedef enum {
+ McBankType = 1,
+ PciExType,
+ CsrOtherType
+} ERROR_ACCESS_TYPE;
+
+#endif
--
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