coreboot-gerrit September 2020

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Change in coreboot[master]: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode
by 9elements QA (Code Review) 14 Sep '20

14 Sep '20

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43494 ) Change subject: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode ...................................................................... Patch Set 8: Automatic boot test returned (PASS/FAIL/TOTAL): 8/1/9 "QEMU x86 q35/ich9" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/19058 "QEMU x86 q35/ich9" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/19057 "QEMU x86 i440fx/piix4" (x86_64) using payload SeaBIOS : FAIL : https://lava.9esec.io/r/19056 "QEMU x86 i440fx/piix4" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/19055 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/19054 "HP Z220 SFF Workstation" (x86_32) using payload LinuxBoot_BusyBox_kexec : SUCCESS : https://lava.9esec.io/r/19062 "HP Z220 SFF Workstation" (x86_32) using payload LinuxBoot_BusyBox_kexec : SUCCESS : https://lava.9esec.io/r/19061 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/19060 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/19059 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/43494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54e047161853bfc70516c1d607aa479e68836d04 Gerrit-Change-Number: 43494 Gerrit-PatchSet: 8 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Comment-Date: Mon, 14 Sep 2020 08:57:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/tigerlake: Increase PRERAM_CBMEM_CONSOLE_SIZE to 8KB
by Anil Kumar K (Code Review) 14 Sep '20

14 Sep '20

Anil Kumar K has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45183 ) Change subject: soc/intel/tigerlake: Increase PRERAM_CBMEM_CONSOLE_SIZE to 8KB ...................................................................... soc/intel/tigerlake: Increase PRERAM_CBMEM_CONSOLE_SIZE to 8KB This patch increases PRERAM_CBMEM_CONSOLE_SIZE from 5KB to 8KB to fix cbmem buffer overflow issue. Bug=None Branch=None Test=Boot TGLRVP and check cbmem -c | grep 'CBFS: Locating' lists all stages Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> Change-Id: I2393cc83008211be8e6a2ca7a1e41a7e9d92caf0 --- M src/soc/intel/tigerlake/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/45183/1 diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index cdec3ef..46bbb74 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -214,5 +214,5 @@ config PRERAM_CBMEM_CONSOLE_SIZE hex - default 0x1400 + default 0x2000 endif -- To view, visit https://review.coreboot.org/c/coreboot/+/45183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2393cc83008211be8e6a2ca7a1e41a7e9d92caf0 Gerrit-Change-Number: 45183 Gerrit-PatchSet: 1 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: mb/google/volteer: Enable EC software sync
by David Wu (Code Review) 14 Sep '20

14 Sep '20

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45186 ) Change subject: mb/google/volteer: Enable EC software sync ...................................................................... mb/google/volteer: Enable EC software sync Enable EC software sync for terrador and todor BUG=None TEST=emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I8c463eadd19d99dc04923f7400560cf7ba4b8101 --- M src/mainboard/google/volteer/Kconfig.name 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/45186/1 diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index 1980dd5..db9d486 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -28,13 +28,11 @@ config BOARD_GOOGLE_TERRADOR bool "-> Terrador" select BOARD_GOOGLE_BASEBOARD_VOLTEER - select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC if CHROMEOS select SOC_INTEL_CSE_LITE_SKU config BOARD_GOOGLE_TODOR bool "-> Todor" select BOARD_GOOGLE_BASEBOARD_VOLTEER - select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC if CHROMEOS select SOC_INTEL_CSE_LITE_SKU config BOARD_GOOGLE_TRONDO -- To view, visit https://review.coreboot.org/c/coreboot/+/45186 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c463eadd19d99dc04923f7400560cf7ba4b8101 Gerrit-Change-Number: 45186 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

5 4

Change in coreboot[master]: Documentation: Add ASan documentation
by Werner Zeh (Code Review) 14 Sep '20

14 Sep '20

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44814 ) Change subject: Documentation: Add ASan documentation ...................................................................... Patch Set 7: Code-Review+2 (1 comment) https://review.coreboot.org/c/coreboot/+/44814/7/Documentation/technotes/as… File Documentation/technotes/asan.md: https://review.coreboot.org/c/coreboot/+/44814/7/Documentation/technotes/as… PS7, Line 283: 1/8th of the : program memory > It might be worth explaining somewhere why it has to be this way (in the code or in the docs)? Because currently every program byte is monitored by a single bit in the shadow memory? If you follow the above mentioned link to ASan (https://github.com/google/sanitizers/wiki/AddressSanitizer) and from there to "AddressSanitizerAlgorithm -- if you are curious how it works." you will find in the description: "AddressSanitizer maps 8 bytes of the application memory into 1 byte of the shadow memory." -- To view, visit https://review.coreboot.org/c/coreboot/+/44814 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I710ea495798597189941620c7e48fd5aa7476781 Gerrit-Change-Number: 44814 Gerrit-PatchSet: 7 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 14 Sep 2020 07:37:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: crossgcc: Fix libcpp to address -Wformat-security.
by Masanori Ogino (Code Review) 14 Sep '20

14 Sep '20

Masanori Ogino has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45311 ) Change subject: crossgcc: Fix libcpp to address -Wformat-security. ...................................................................... crossgcc: Fix libcpp to address -Wformat-security. On some systems where the system compiler enables `-Wformat-security -Werror=format-security` options are enabled by default, building libcpp fails because the code passes a variable directly as a format string. This change addresses this problem by patching the affected code. Tested with the default compiler of Nixpkgs unstable, GCC 9.3.0 with the options described above enabled by default. Signed-off-by: Masanori Ogino <mogino(a)acm.org> Change-Id: Ibf3c9e79ce10cd400c9f7ea40dd6de1ab81b50e2 --- A util/crossgcc/patches/gcc-8.3.0_libcpp.patch 1 file changed, 56 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/45311/1 diff --git a/util/crossgcc/patches/gcc-8.3.0_libcpp.patch b/util/crossgcc/patches/gcc-8.3.0_libcpp.patch new file mode 100644 index 0000000..b2701511 --- /dev/null +++ b/util/crossgcc/patches/gcc-8.3.0_libcpp.patch @@ -0,0 +1,56 @@ +GCC with `-Wformat-security -Werror=format-security` hardening options enabled +by default rejects some codes in libcpp. This patch fixes them. + +--- gcc-8.3.0/libcpp/expr.c.orig 2020-09-11 15:44:45.770000000 +0900 ++++ gcc-8.3.0/libcpp/expr.c 2020-09-11 15:46:22.370000000 +0900 +@@ -794,10 +794,10 @@ + + if (CPP_OPTION (pfile, c99)) + cpp_warning_with_line (pfile, CPP_W_LONG_LONG, virtual_location, +- 0, message); ++ 0, "%s", message); + else + cpp_pedwarning_with_line (pfile, CPP_W_LONG_LONG, +- virtual_location, 0, message); ++ virtual_location, 0, "%s", message); + } + + result |= CPP_N_INTEGER; +--- gcc-8.3.0/libcpp/macro.c.bak 2020-09-11 16:01:42.550000000 +0900 ++++ gcc-8.3.0/libcpp/macro.c 2020-09-11 16:03:47.850000000 +0900 +@@ -160,7 +160,7 @@ + if (m_state == 2 && token->type == CPP_PASTE) + { + cpp_error_at (m_pfile, CPP_DL_ERROR, token->src_loc, +- vaopt_paste_error); ++ "%s", vaopt_paste_error); + return ERROR; + } + /* Advance states before further considering this token, in +@@ -189,7 +189,7 @@ + if (was_paste) + { + cpp_error_at (m_pfile, CPP_DL_ERROR, token->src_loc, +- vaopt_paste_error); ++ "%s", vaopt_paste_error); + return ERROR; + } + +@@ -3361,7 +3361,7 @@ + function-like macros, but not at the end. */ + if (following_paste_op) + { +- cpp_error (pfile, CPP_DL_ERROR, paste_op_error_msg); ++ cpp_error (pfile, CPP_DL_ERROR, "%s", paste_op_error_msg); + return false; + } + break; +@@ -3374,7 +3374,7 @@ + function-like macros, but not at the beginning. */ + if (macro->count == 1) + { +- cpp_error (pfile, CPP_DL_ERROR, paste_op_error_msg); ++ cpp_error (pfile, CPP_DL_ERROR, "%s", paste_op_error_msg); + return false; + } + -- To view, visit https://review.coreboot.org/c/coreboot/+/45311 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf3c9e79ce10cd400c9f7ea40dd6de1ab81b50e2 Gerrit-Change-Number: 45311 Gerrit-PatchSet: 1 Gerrit-Owner: Masanori Ogino <masanori.ogino(a)gmail.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: src/include: Drop unneeded empty lines
by HAOUAS Elyes (Code Review) 14 Sep '20

14 Sep '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44611 ) Change subject: src/include: Drop unneeded empty lines ...................................................................... src/include: Drop unneeded empty lines Change-Id: Ie325541547ea10946f41a8f979d144a06a7e80eb Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/include/console/flash.h M src/include/console/spi.h M src/include/cpu/intel/em64t100_save_state.h M src/include/cpu/intel/em64t101_save_state.h M src/include/cpu/intel/smm_reloc.h M src/include/cpu/intel/speedstep.h M src/include/cpu/x86/msr.h M src/include/cpu/x86/mtrr.h M src/include/cpu/x86/post_code.h M src/include/device/dram/ddr3.h M src/include/device/dram/ddr4.h M src/include/device/hypertransport_def.h M src/include/device/path.h M src/include/device/pci_def.h M src/include/device/pci_ids.h M src/include/device/pci_mmio_cfg.h M src/include/device/pnp.h M src/include/device/resource.h M src/include/device_tree.h M src/include/elog.h M src/include/input-event-codes.h M src/include/memrange.h M src/include/nhlt.h M src/include/pc80/mc146818rtc.h M src/include/reg_script.h M src/include/smp/atomic.h M src/include/spd.h 27 files changed, 0 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/44611/1 diff --git a/src/include/console/flash.h b/src/include/console/flash.h index 8104e5c..9a0dc63 100644 --- a/src/include/console/flash.h +++ b/src/include/console/flash.h @@ -27,5 +27,4 @@ static inline void __flashconsole_tx_flush(void) {} #endif /* __CONSOLE_FLASH_ENABLE__ */ - #endif /* CONSOLE_FLASH_H */ diff --git a/src/include/console/spi.h b/src/include/console/spi.h index cb32d7e..8a58b85 100644 --- a/src/include/console/spi.h +++ b/src/include/console/spi.h @@ -52,6 +52,4 @@ char data[MAX_MSG_LENGTH]; } __packed; - - #endif /* CONSOLE_SPI_H */ diff --git a/src/include/cpu/intel/em64t100_save_state.h b/src/include/cpu/intel/em64t100_save_state.h index 8596ce5..b656a28 100644 --- a/src/include/cpu/intel/em64t100_save_state.h +++ b/src/include/cpu/intel/em64t100_save_state.h @@ -66,7 +66,6 @@ u64 rsi; u64 rdi; - u64 io_mem_addr; u32 io_misc_info; diff --git a/src/include/cpu/intel/em64t101_save_state.h b/src/include/cpu/intel/em64t101_save_state.h index 2e4e0d5..6884b28 100644 --- a/src/include/cpu/intel/em64t101_save_state.h +++ b/src/include/cpu/intel/em64t101_save_state.h @@ -6,7 +6,6 @@ #include <types.h> #include <cpu/x86/smm.h> - /* Intel Revision 30101 SMM State-Save Area * The following processor architectures use this: * - Westmere @@ -83,7 +82,6 @@ u64 rsi; u64 rdi; - u64 io_mem_addr; u32 io_misc_info; diff --git a/src/include/cpu/intel/smm_reloc.h b/src/include/cpu/intel/smm_reloc.h index 07fe038..126aa2a 100644 --- a/src/include/cpu/intel/smm_reloc.h +++ b/src/include/cpu/intel/smm_reloc.h @@ -51,7 +51,6 @@ bool cpu_has_alternative_smrr(void); - #define MSR_PRMRR_PHYS_BASE 0x1f4 #define MSR_PRMRR_PHYS_MASK 0x1f5 #define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h index d66b8e2..e085e34 100644 --- a/src/include/cpu/intel/speedstep.h +++ b/src/include/cpu/intel/speedstep.h @@ -18,7 +18,6 @@ */ #define PMB1_BASE 0x800 - /* Speedstep related MSRs */ #define MSR_THERM2_CTL 0x19D #define MSR_EBC_FREQUENCY_ID 0x2c diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index c761bc0..81312f2 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -296,7 +296,6 @@ return MCA_ERRTYPE_UNKNOWN; } - /* Helper for setting single MSR bits */ static inline void msr_set_bit(unsigned int reg, unsigned int bit) { @@ -315,6 +314,5 @@ wrmsr(reg, msr); } - #endif /* __ASSEMBLER__ */ #endif /* CPU_X86_MSR_H */ diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 42964b0..08cfde7 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -27,7 +27,6 @@ #define MTRR_DEF_TYPE_EN (1 << 11) #define MTRR_DEF_TYPE_FIX_EN (1 << 10) - #define IA32_SMRR_PHYS_BASE 0x1f2 #define IA32_SMRR_PHYS_MASK 0x1f3 diff --git a/src/include/cpu/x86/post_code.h b/src/include/cpu/x86/post_code.h index fce39b7..077f964 100644 --- a/src/include/cpu/x86/post_code.h +++ b/src/include/cpu/x86/post_code.h @@ -3,7 +3,6 @@ #include <console/post_codes.h> - #if CONFIG(POST_IO) #define post_code(value) \ movb $value, %al; \ diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h index 74e0ff55..0814990 100644 --- a/src/include/device/dram/ddr3.h +++ b/src/include/device/dram/ddr3.h @@ -19,7 +19,6 @@ #include <device/dram/common.h> #include <types.h> - /** * Convenience definitions for SPD offsets * diff --git a/src/include/device/dram/ddr4.h b/src/include/device/dram/ddr4.h index f258fa9..d22d4bc 100644 --- a/src/include/device/dram/ddr4.h +++ b/src/include/device/dram/ddr4.h @@ -21,7 +21,6 @@ #define SPD_DDR4_PART_OFF 329 #define SPD_DDR4_PART_LEN 20 - /* * Module type (byte 3, bits 3:0) of SPD * This definition is specific to DDR4. DDR2/3 SPDs have a different structure. diff --git a/src/include/device/hypertransport_def.h b/src/include/device/hypertransport_def.h index a0b1a36..3cbd90b 100644 --- a/src/include/device/hypertransport_def.h +++ b/src/include/device/hypertransport_def.h @@ -18,7 +18,6 @@ #define HT_FREQ_2600Mhz 14 #define HT_FREQ_VENDOR 15 /* AMD defines this to be 100Mhz */ - static inline bool offset_unit_id(bool is_sb_ht_chain) { bool need_offset = (CONFIG_HT_CHAIN_UNITID_BASE != 1) diff --git a/src/include/device/path.h b/src/include/device/path.h index 4db83b7..5690bad 100644 --- a/src/include/device/path.h +++ b/src/include/device/path.h @@ -137,7 +137,6 @@ }; }; - #define DEVICE_PATH_MAX 40 #define BUS_PATH_MAX (DEVICE_PATH_MAX+10) diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index 25372bf..e0d891e 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -305,7 +305,6 @@ #define PCI_MSIX_PBA_OFFSET ~0x7 /* Offset into specified BAR */ #define PCI_CAP_MSIX_SIZEOF 12 /* size of MSIX registers */ - /* CompactPCI Hotswap Register */ #define PCI_CHSWP_CSR 2 /* Control and Status Register */ @@ -521,7 +520,6 @@ #define PCI_PWR_CAP 12 /* Capability */ #define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */ - /* * The PCI interface treats multi-function devices as independent * devices. The slot/function address of each device is encoded diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index b1d3d3f..dce076c 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -517,7 +517,6 @@ #define PCI_DEVICE_ID_NS_SCx200_XBUS 0x0505 #define PCI_DEVICE_ID_NS_87410 0xd001 - #define PCI_VENDOR_ID_TSENG 0x100c #define PCI_DEVICE_ID_TSENG_W32P_2 0x3202 #define PCI_DEVICE_ID_TSENG_W32P_b 0x3205 @@ -1664,7 +1663,6 @@ #define PCI_DEVICE_ID_ATT_L56XMF 0x0440 #define PCI_DEVICE_ID_ATT_VENUS_MODEM 0x480 - #define PCI_VENDOR_ID_SPECIALIX 0x11cb #define PCI_DEVICE_ID_SPECIALIX_IO8 0x2000 #define PCI_DEVICE_ID_SPECIALIX_XIO 0x4000 diff --git a/src/include/device/pci_mmio_cfg.h b/src/include/device/pci_mmio_cfg.h index d3666c2..234ebb4 100644 --- a/src/include/device/pci_mmio_cfg.h +++ b/src/include/device/pci_mmio_cfg.h @@ -7,7 +7,6 @@ #include <device/mmio.h> #include <device/pci_type.h> - /* By not assigning this to CONFIG_MMCONF_BASE_ADDRESS here we * prevent some sub-optimal constant folding. */ extern u8 *const pci_mmconf; diff --git a/src/include/device/pnp.h b/src/include/device/pnp.h index 800bcc0..7340bbf 100644 --- a/src/include/device/pnp.h +++ b/src/include/device/pnp.h @@ -67,7 +67,6 @@ void pnp_enable_devices(struct device *dev, struct device_operations *ops, unsigned int functions, struct pnp_info *info); - struct pnp_mode_ops { void (*enter_conf_mode)(struct device *dev); void (*exit_conf_mode)(struct device *dev); diff --git a/src/include/device/resource.h b/src/include/device/resource.h index 42c7e6a..3a7ccf0 100644 --- a/src/include/device/resource.h +++ b/src/include/device/resource.h @@ -109,7 +109,6 @@ const struct device *largest_resource(struct bus *bus, struct resource **result_res, unsigned long type_mask, unsigned long type); - /* Compute and allocate resources. This is the main resource allocator entry point. */ void allocate_resources(const struct device *root); diff --git a/src/include/device_tree.h b/src/include/device_tree.h index b70f5aa..ae30c59 100644 --- a/src/include/device_tree.h +++ b/src/include/device_tree.h @@ -43,8 +43,6 @@ uint32_t size; }; - - /* * Unflattened device tree structures. */ @@ -88,8 +86,6 @@ struct device_tree_node *root; }; - - /* * Flattened device tree functions. These generally return the number of bytes * which were consumed reading the requested value. @@ -109,8 +105,6 @@ invalidates the unflattened one. */ struct device_tree *fdt_unflatten(const void *blob); - - /* * Unflattened device tree functions. */ diff --git a/src/include/elog.h b/src/include/elog.h index c41887a..8c50e00 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -202,7 +202,6 @@ #define ELOG_TYPE_MI_HRPC 0xb4 #define ELOG_TYPE_MI_HR 0xb5 - struct elog_event_extended_event { u8 event_type; u32 event_complement; diff --git a/src/include/input-event-codes.h b/src/include/input-event-codes.h index 006c262..abb1e08 100644 --- a/src/include/input-event-codes.h +++ b/src/include/input-event-codes.h @@ -870,7 +870,6 @@ #define ABS_MT_TOOL_X 0x3c /* Center X tool position */ #define ABS_MT_TOOL_Y 0x3d /* Center Y tool position */ - #define ABS_MAX 0x3f #define ABS_CNT (ABS_MAX+1) diff --git a/src/include/memrange.h b/src/include/memrange.h index 72cfa72..80db598 100644 --- a/src/include/memrange.h +++ b/src/include/memrange.h @@ -82,7 +82,6 @@ #define memranges_each_entry(r, ranges) \ for (r = (ranges)->entries; r != NULL; r = r->next) - /* Initialize memranges structure providing an optional array of range_entry * to use as the free list. Additionally, it accepts an align parameter that * represents the required alignment(log 2) of addresses. */ diff --git a/src/include/nhlt.h b/src/include/nhlt.h index 30cb274..3355801 100644 --- a/src/include/nhlt.h +++ b/src/include/nhlt.h @@ -219,7 +219,6 @@ SPEAKER_TOP_BACK_RIGHT = 1 << 17, }; - /* Supporting structures. Only SoC/chipset and the library code directly should * be manipulating these structures. */ struct sub_format { diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index a2c65cb..2f94cc0 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -17,7 +17,6 @@ #define RTC_REG_C 12 #define RTC_REG_D 13 - /********************************************************************** * register details **********************************************************************/ diff --git a/src/include/reg_script.h b/src/include/reg_script.h index 59da0cb..aa6bf80 100644 --- a/src/include/reg_script.h +++ b/src/include/reg_script.h @@ -355,7 +355,6 @@ #define REG_RES_XOR32(bar_, reg_, value_) \ REG_RES_RXW32(bar_, reg_, 0xffffffff, value_) - #if CONFIG(SOC_INTEL_BAYTRAIL) /* * IO Sideband Function diff --git a/src/include/smp/atomic.h b/src/include/smp/atomic.h index ed70cb7..5e78ae4 100644 --- a/src/include/smp/atomic.h +++ b/src/include/smp/atomic.h @@ -31,7 +31,6 @@ */ #define atomic_set(v, i) (((v)->counter) = (i)) - /** * atomic_inc - increment atomic variable * @param v: pointer of type atomic_t @@ -41,7 +40,6 @@ */ #define atomic_inc(v) (((v)->counter)++) - /** * atomic_dec - decrement atomic variable * @param v: pointer of type atomic_t @@ -51,7 +49,6 @@ */ #define atomic_dec(v) (((v)->counter)--) - #endif /* CONFIG_SMP */ #endif /* SMP_ATOMIC_H */ diff --git a/src/include/spd.h b/src/include/spd.h index f46bde6..9afb706 100644 --- a/src/include/spd.h +++ b/src/include/spd.h @@ -136,7 +136,6 @@ /* SDRAM Device Minimum Auto Refresh to Active/Auto Refresh (tRFC) */ #define SPD_tRFC 42 - /* SPD_MEMORY_TYPE values. */ enum spd_memory_type { SPD_MEMORY_TYPE_UNDEFINED = 0x00, -- To view, visit https://review.coreboot.org/c/coreboot/+/44611 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie325541547ea10946f41a8f979d144a06a7e80eb Gerrit-Change-Number: 44611 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/delbin: Configure DP_HPD as PAD_NC and disable DdiPortHpd
by Ravishankar Sarawadi (Code Review) 14 Sep '20

14 Sep '20

Ravishankar Sarawadi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45031 ) Change subject: mb/google/delbin: Configure DP_HPD as PAD_NC and disable DdiPortHpd ...................................................................... mb/google/delbin: Configure DP_HPD as PAD_NC and disable DdiPortHpd GPP_A19(DP_HPD1) and GPP_A20(DP_HPD2) were configured native function (NF1) without internal pull-down which wrongly presents HPD interrupts. DP_HPD had been removed for EVT design as those events are through eSPI. This change configures GPP_A19 and GPP_A20 to be no connection and disables DdiPort1Hpd and DdiPort2Hpd. BUG=b:162566436 TEST=Booted to kernel and verified no kernel HPD pins assertion message on Delbin board. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Change-Id: Ifdef8ee438276678258b75d2fb70c6dfc7ee0a33 --- M src/mainboard/google/volteer/variants/delbin/gpio.c M src/mainboard/google/volteer/variants/delbin/overridetree.cb 2 files changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/45031/1 diff --git a/src/mainboard/google/volteer/variants/delbin/gpio.c b/src/mainboard/google/volteer/variants/delbin/gpio.c index 1d4bfe6..5748bb3 100644 --- a/src/mainboard/google/volteer/variants/delbin/gpio.c +++ b/src/mainboard/google/volteer/variants/delbin/gpio.c @@ -19,9 +19,9 @@ /* A18 : DDSP_HPDB ==> HDMI_HPD */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */ - PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), + PAD_NC(GPP_A19, NONE), /* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */ - PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + PAD_NC(GPP_A20, NONE), /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ PAD_CFG_GPO(GPP_A22, 1, DEEP), /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ diff --git a/src/mainboard/google/volteer/variants/delbin/overridetree.cb b/src/mainboard/google/volteer/variants/delbin/overridetree.cb index fc549c7..05c8a34 100644 --- a/src/mainboard/google/volteer/variants/delbin/overridetree.cb +++ b/src/mainboard/google/volteer/variants/delbin/overridetree.cb @@ -1,4 +1,7 @@ chip soc/intel/tigerlake + register "DdiPort1Hpd" = "0" + register "DdiPort2Hpd" = "0" + device domain 0 on device pci 15.0 on chip drivers/i2c/generic -- To view, visit https://review.coreboot.org/c/coreboot/+/45031 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdef8ee438276678258b75d2fb70c6dfc7ee0a33 Gerrit-Change-Number: 45031 Gerrit-PatchSet: 1 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/boten: Add audio configuration
by Patrick Georgi (Code Review) 14 Sep '20

14 Sep '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44920 ) Change subject: mb/google/dedede/var/boten: Add audio configuration ...................................................................... mb/google/dedede/var/boten: Add audio configuration Add configuration for ALC5682 headphone jack and ALC1015 speaker amplifier. Also turn on the HDA PCI device. BUG=b:161667665 TEST=Build the boten board and verified the audio functionality. Change-Id: I835db854543e6282c102c86a7073b432fd89d0a5 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44920 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Justin TerAvest <teravest(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/dedede/variants/boten/overridetree.cb 1 file changed, 28 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Justin TerAvest: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/dedede/variants/boten/overridetree.cb b/src/mainboard/google/dedede/variants/boten/overridetree.cb index 1e75864..61dff93 100644 --- a/src/mainboard/google/dedede/variants/boten/overridetree.cb +++ b/src/mainboard/google/dedede/variants/boten/overridetree.cb @@ -35,5 +35,32 @@ .speed = I2C_SPEED_FAST, }, }" - device domain 0 on end + device domain 0 on + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1015"" + register "desc" = ""Realtek SPK AMP L"" + register "uid" = "0" + device i2c 28 on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1015"" + register "desc" = ""Realtek SPK AMP R"" + register "uid" = "1" + device i2c 29 on end + end + end + device pci 1f.3 on end # Intel HDA + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/44920 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I835db854543e6282c102c86a7073b432fd89d0a5 Gerrit-Change-Number: 44920 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Ben Zhang <benzh(a)google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: sb/intel/lynxpoint/acpi: Do not determine PCH type at runtime
by Angel Pons (Code Review) 14 Sep '20

14 Sep '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45048 ) Change subject: sb/intel/lynxpoint/acpi: Do not determine PCH type at runtime ...................................................................... sb/intel/lynxpoint/acpi: Do not determine PCH type at runtime Both PCH types are very different, and mixing the code for both together isn't useful. Make `ISLP` return a constant, so that IASL can fold it. Change-Id: I6222d6661115d444d4dad0217c2d376dc551465c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/acpi/pch.asl 1 file changed, 1 insertion(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/45048/1 diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index e1bd64f..154633d 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -7,11 +7,7 @@ // Return TRUE if chipset is LynxPoint-LP Method (ISLP, 0, NotSerialized) { - If (LEqual (\_SB.PCI0.LPCB.DIDH, 0x9c)) { - Return (1) - } else { - Return (0) - } + Return (CONFIG(INTEL_LYNXPOINT_LP)) } // IO-Trap at 0x800. This is the ACPI->SMI communication interface. -- To view, visit https://review.coreboot.org/c/coreboot/+/45048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6222d6661115d444d4dad0217c2d376dc551465c Gerrit-Change-Number: 45048 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/lynxpoint: Do not determine PCH type at runtime
by Angel Pons (Code Review) 14 Sep '20

14 Sep '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45047 ) Change subject: sb/intel/lynxpoint: Do not determine PCH type at runtime ...................................................................... sb/intel/lynxpoint: Do not determine PCH type at runtime Both PCH types are very different, and mixing the code for both together isn't useful. First of all, inline `pch_is_lp` to return a constant. Subsequent commits will further split the southbridge code. Change-Id: Iba904acf64096478d1b76ffd05a076f0203502f8 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/early_pch.c M src/southbridge/intel/lynxpoint/pch.c M src/southbridge/intel/lynxpoint/pch.h 3 files changed, 5 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/45047/1 diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 85f9f33..956d1d2 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -35,11 +35,6 @@ return PCH_TYPE_DESKTOP; } -int pch_is_lp(void) -{ - return get_pch_platform_type() == PCH_TYPE_ULT; -} - static void pch_enable_bars(void) { pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index c08f0da..adc011b 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -57,11 +57,6 @@ return PCH_TYPE_DESKTOP; } -int pch_is_lp(void) -{ - return get_pch_platform_type() == PCH_TYPE_ULT; -} - u16 get_pmbase(void) { static u16 pmbase; diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 2c86ff0..1ecad62 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -69,6 +69,11 @@ #ifndef __ACPI__ +static inline int pch_is_lp(void) +{ + return CONFIG(INTEL_LYNXPOINT_LP); +} + /* PCH platform types, safe for MRC consumption */ enum pch_platform_type { PCH_TYPE_MOBILE = 0, @@ -84,7 +89,6 @@ enum pch_platform_type get_pch_platform_type(void); int pch_silicon_revision(void); int pch_silicon_id(void); -int pch_is_lp(void); u16 get_pmbase(void); u16 get_gpiobase(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/45047 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba904acf64096478d1b76ffd05a076f0203502f8 Gerrit-Change-Number: 45047 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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