Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45048 )
Change subject: sb/intel/lynxpoint/acpi: Do not determine PCH type at runtime ......................................................................
sb/intel/lynxpoint/acpi: Do not determine PCH type at runtime
Both PCH types are very different, and mixing the code for both together isn't useful. Make `ISLP` return a constant, so that IASL can fold it.
Change-Id: I6222d6661115d444d4dad0217c2d376dc551465c Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/lynxpoint/acpi/pch.asl 1 file changed, 1 insertion(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/45048/1
diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index e1bd64f..154633d 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -7,11 +7,7 @@ // Return TRUE if chipset is LynxPoint-LP Method (ISLP, 0, NotSerialized) { - If (LEqual (_SB.PCI0.LPCB.DIDH, 0x9c)) { - Return (1) - } else { - Return (0) - } + Return (CONFIG(INTEL_LYNXPOINT_LP)) }
// IO-Trap at 0x800. This is the ACPI->SMI communication interface.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45048 )
Change subject: sb/intel/lynxpoint/acpi: Do not determine PCH type at runtime ......................................................................
Patch Set 3: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45048 )
Change subject: sb/intel/lynxpoint/acpi: Do not determine PCH type at runtime ......................................................................
sb/intel/lynxpoint/acpi: Do not determine PCH type at runtime
Both PCH types are very different, and mixing the code for both together isn't useful. Make `ISLP` return a constant, so that IASL can fold it.
Change-Id: I6222d6661115d444d4dad0217c2d376dc551465c Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/45048 Reviewed-by: Arthur Heymans arthur@aheymans.xyz Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/southbridge/intel/lynxpoint/acpi/pch.asl 1 file changed, 1 insertion(+), 5 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index e1bd64f..154633d 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -7,11 +7,7 @@ // Return TRUE if chipset is LynxPoint-LP Method (ISLP, 0, NotSerialized) { - If (LEqual (_SB.PCI0.LPCB.DIDH, 0x9c)) { - Return (1) - } else { - Return (0) - } + Return (CONFIG(INTEL_LYNXPOINT_LP)) }
// IO-Trap at 0x800. This is the ACPI->SMI communication interface.