Change in coreboot[master]: mb/intel/tglrvp/variants/tglrvp_up4 - Disable TBT_PCIe3 for TGL-Y RVP
Jason V Le has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45216 )
Change subject: mb/intel/tglrvp/variants/tglrvp_up4 - Disable TBT_PCIe3 for TGL-Y RVP ......................................................................
mb/intel/tglrvp/variants/tglrvp_up4 - Disable TBT_PCIe3 for TGL-Y RVP
- Disable TBT_PCIe3 since it is not applicable for TGL-Y RVP
Test: Boot the system and verify existing TBT ports still working
Signed-off-by: Jason Le jason.v.le@intel.com Change-Id: I4ba873832931c17eed5908127dbb2e44b41f46bf --- M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/45216/1
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index c2c6902..6a0f3dd 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -160,7 +160,7 @@ device pci 07.0 on end # TBT_PCIe0 0x9A23 device pci 07.1 on end # TBT_PCIe1 0x9A25 device pci 07.2 on end # TBT_PCIe2 0x9A27 - device pci 07.3 on end # TBT_PCIe3 0x9A29 + device pci 07.3 off end # TBT_PCIe3 0x9A29 device pci 08.0 off end # GNA 0x9A11 device pci 09.0 off end # NPK 0x9A33 device pci 0a.0 off end # Crash-log SRAM 0x9A0D
Utkarsh H Patel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45216 )
Change subject: mb/intel/tglrvp/variants/tglrvp_up4 - Disable TBT_PCIe3 for TGL-Y RVP ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/45216/1/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/45216/1/src/mainboard/intel/tglrvp/... PS1, Line 168: any reason xdci is enabled?
https://review.coreboot.org/c/coreboot/+/45216/1/src/mainboard/intel/tglrvp/... PS1, Line 170: why do we disable DMA1 on UP4?
Jason V Le has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45216 )
Change subject: mb/intel/tglrvp/variants/tglrvp_up4 - Disable TBT_PCIe3 for TGL-Y RVP ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/45216/1/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/45216/1/src/mainboard/intel/tglrvp/... PS1, Line 168:
any reason xdci is enabled?
Not sure. For debugging purpose?
https://review.coreboot.org/c/coreboot/+/45216/1/src/mainboard/intel/tglrvp/... PS1, Line 170:
why do we disable DMA1 on UP4?
It was temporarily turned off earlier to get around with coreboot reboot issue. I can enable it now. Will update in the second patchset
Jason V Le has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/45216 )
Change subject: mb/intel/tglrvp/variants/tglrvp_up4 - Disable TBT_PCIe3 for TGL-Y RVP ......................................................................
Abandoned
-
Jason V Le (Code Review) -
Utkarsh H Patel (Code Review)