coreboot-gerrit September 2020

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Change in coreboot[master]: lint: check for misuse of Kconfig SUBSYSTEM_*_ID
by Martin Roth (Code Review) 18 Sep '20

18 Sep '20

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45513 ) Change subject: lint: check for misuse of Kconfig SUBSYSTEM_*_ID ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/c/coreboot/+/45513/1/util/lint/check_lint_tests File util/lint/check_lint_tests: https://review.coreboot.org/c/coreboot/+/45513/1/util/lint/check_lint_tests… PS1, Line 31: lint use lint-stable instead so that it runs on the builder? https://review.coreboot.org/c/coreboot/+/45513/1/util/lint/check_lint_tests… PS1, Line 31: 009 Since this is a new test, the number should be the next number in the lint list - currently 24. -- To view, visit https://review.coreboot.org/c/coreboot/+/45513 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21c021c718154f1396f795a555af47a76d6efe03 Gerrit-Change-Number: 45513 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 18 Sep 2020 14:59:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/rockchip: Port make_idb.py to python3
by Yilin Yang (Code Review) 18 Sep '20

18 Sep '20

Yilin Yang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45447 ) Change subject: util/rockchip: Port make_idb.py to python3 ...................................................................... util/rockchip: Port make_idb.py to python3 BUG=chromium:1023662 Signed-off-by: Yilin Yang <kerker(a)google.com> Change-Id: I04253084ec9b65310c52598b629390051cd2172b --- M util/rockchip/make_idb.py 1 file changed, 26 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/45447/1 diff --git a/util/rockchip/make_idb.py b/util/rockchip/make_idb.py index 12cd130..c633d4d 100755 --- a/util/rockchip/make_idb.py +++ b/util/rockchip/make_idb.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python2 +#!/usr/bin/env python3 # SPDX-License-Identifier: BSD-2-Clause import struct @@ -7,7 +7,7 @@ class IDBTool: def __init__(self): - print "Initialize IDBTool" + print("Initialize IDBTool") def p_rc4(self, buf, length): key = (124,78,3,4,85,5,9,7,45,44,123,56,23,13,23,17) @@ -27,6 +27,13 @@ k = (S[i] + S[j]) % 256 buf[x] = struct.pack('B', ord(buf[x]) ^ S[k]) + def bytesToList(self, byte_string): + ret = [] + for ch in byte_string: + ret.append(bytes((ch,))) + + return ret + def makeIDB(self, chip, from_file, to_file, rc4_flag = False, align_flag = False): try: fin = open(from_file, 'rb') @@ -50,23 +57,23 @@ sectors = pages * PAGE_ALIGN; buf = [B'\0'] * sectors * SECTOR_SIZE - buf[:4] = chip - buf[4 : 4+data_len] = data + buf[:4] = self.bytesToList(chip) + buf[4 : 4+data_len] = self.bytesToList(data) idblock = [B'\0'] * 4 * SECTOR_SIZE blank = [B'\0'] * 4 * SECTOR_SIZE - idblock[:4] = ['\x55', '\xAA', '\xF0', '\x0F'] + idblock[:4] = [b'\x55', b'\xAA', b'\xF0', b'\x0F'] if (not rc4_flag): - idblock[8:12] = struct.pack("<I", 1) + idblock[8:12] = self.bytesToList(struct.pack("<I", 1)) else: for i in range(sectors): list_tmp = buf[SECTOR_SIZE*i : SECTOR_SIZE*(i+1)] self.p_rc4(list_tmp, SECTOR_SIZE) buf[SECTOR_SIZE*i : SECTOR_SIZE*(i+1)] = list_tmp - idblock[12:16] = struct.pack("<HH", 4, 4); - idblock[506:510] = struct.pack("<HH", sectors, sectors); + idblock[12:16] = self.bytesToList(struct.pack("<HH", 4, 4)) + idblock[506:510] = self.bytesToList(struct.pack("<HH", sectors, sectors)) self.p_rc4(idblock, SECTOR_SIZE) try: @@ -76,25 +83,25 @@ try: if (align_flag): - fout.write(''.join(idblock)) - fout.write(''.join(blank)) + fout.write(b''.join(idblock)) + fout.write(b''.join(blank)) - for s in xrange(0, sectors * SECTOR_SIZE, PAGE_ALIGN * SECTOR_SIZE): - fout.write(''.join(buf[s : s + PAGE_ALIGN * SECTOR_SIZE])) - fout.write(''.join(blank)) + for s in range(0, sectors * SECTOR_SIZE, PAGE_ALIGN * SECTOR_SIZE): + fout.write(b''.join(buf[s : s + PAGE_ALIGN * SECTOR_SIZE])) + fout.write(b''.join(blank)) else: - fout.write(''.join(idblock)) - fout.write(''.join(buf)) + fout.write(b''.join(idblock)) + fout.write(b''.join(buf)) fout.flush() except: sys.exit("Failed to write data to : " + to_file) finally: fout.close() - print "DONE" + print("DONE") def usage(): - print "Usage: make_idb.py [--chip=RKXX] [--enable-rc4] [--enable-align] [--to=out] --from=in" - print " --chip: default is RK32" + print("Usage: make_idb.py [--chip=RKXX] [--enable-rc4] [--enable-align] [--to=out] --from=in") + print(" --chip: default is RK32") if __name__ == '__main__': rc4_flag = align_flag = False @@ -123,4 +130,4 @@ sys.exit() idbtool = IDBTool() - idbtool.makeIDB(chip, from_file, to_file, rc4_flag, align_flag) + idbtool.makeIDB(chip.encode('utf-8'), from_file, to_file, rc4_flag, align_flag) -- To view, visit https://review.coreboot.org/c/coreboot/+/45447 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04253084ec9b65310c52598b629390051cd2172b Gerrit-Change-Number: 45447 Gerrit-PatchSet: 1 Gerrit-Owner: Yilin Yang <kerker(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: superio/nuvoton: Build hwm.c for all stages
by Angel Pons (Code Review) 18 Sep '20

18 Sep '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42130 ) Change subject: superio/nuvoton: Build hwm.c for all stages ...................................................................... superio/nuvoton: Build hwm.c for all stages There's no reason to restrict `nuvoton_hwm_select_bank` to ramstage. Change-Id: I103a4ea4cef24844d382854c9358bbb37d229e04 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/superio/nuvoton/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/42130/1 diff --git a/src/superio/nuvoton/Makefile.inc b/src/superio/nuvoton/Makefile.inc index 054c7ba..0d5d0f5 100644 --- a/src/superio/nuvoton/Makefile.inc +++ b/src/superio/nuvoton/Makefile.inc @@ -5,7 +5,7 @@ romstage-$(CONFIG_SUPERIO_NUVOTON_COMMON_PRE_RAM) += common/early_serial.c ## include generic Nuvoton HWM driver -ramstage-$(CONFIG_SUPERIO_NUVOTON_COMMON_HWM) += common/hwm.c +all-$(CONFIG_SUPERIO_NUVOTON_COMMON_HWM) += common/hwm.c subdirs-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += wpcm450 subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5104D) += nct5104d -- To view, visit https://review.coreboot.org/c/coreboot/+/42130 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I103a4ea4cef24844d382854c9358bbb37d229e04 Gerrit-Change-Number: 42130 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/include: Add PnP/HWM update functions
by Angel Pons (Code Review) 18 Sep '20

18 Sep '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42134 ) Change subject: src/include: Add PnP/HWM update functions ...................................................................... src/include: Add PnP/HWM update functions RMW (read/modify/write) ops on PnP devices has never been so simple. Change-Id: Ica01211af2a9a00aed98880844a836f6b7957b14 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/include/device/pnp.h M src/include/device/pnp_ops.h M src/include/superio/hwm5_conf.h 3 files changed, 51 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/42134/1 diff --git a/src/include/device/pnp.h b/src/include/device/pnp.h index 800bcc0..158d40e 100644 --- a/src/include/device/pnp.h +++ b/src/include/device/pnp.h @@ -133,4 +133,29 @@ outb(value, port + 1); } +/* + * void pnp_update_index(u16 port, u8 reg, u8 mask, u8 or) + * Description: + * This routine updates indexed I/O registers. The reg byte is written + * to the index register at I/O address = port. The value is then read + * from the data register at I/O address = port + 1. This value is ANDed + * with the mask value and then ORed with the or value. Finally, the + * new value is written to the data register at I/O address = port + 1. + * + * Parameters: + * @param[in] u16 port = The address of the port index register. + * @param[in] u8 reg = The offset within the indexed space. + * @param[in] u8 mask = The mask value to apply to the data register value. + * @param[in] u8 or = The or value to apply to the data register value. + */ +static inline void pnp_update_index(u16 port, u8 reg, u8 mask, u8 or) +{ + outb(reg, port); + + uint8_t value = inb(port + 1); + value &= mask; + value |= or; + outb(value, port + 1); +} + #endif /* DEVICE_PNP_H */ diff --git a/src/include/device/pnp_ops.h b/src/include/device/pnp_ops.h index 0cfdd61..783c3ad 100644 --- a/src/include/device/pnp_ops.h +++ b/src/include/device/pnp_ops.h @@ -22,6 +22,12 @@ return pnp_read_index(dev >> 8, reg); } +static __always_inline void pnp_update_config( + pnp_devfn_t dev, uint8_t reg, uint8_t mask, uint8_t or) +{ + pnp_update_index(dev >> 8, reg, mask, or); +} + static __always_inline void pnp_set_logical_device(pnp_devfn_t dev) { diff --git a/src/include/superio/hwm5_conf.h b/src/include/superio/hwm5_conf.h index 661f3ee..5e9a142 100644 --- a/src/include/superio/hwm5_conf.h +++ b/src/include/superio/hwm5_conf.h @@ -44,4 +44,24 @@ pnp_write_index(base + 5, reg, value); } +/* + * void pnp_update_hwm5_index(u16 base, u8 reg, u8 mask, u8 or) + * Description: + * This routine updates indexed I/O registers. The reg byte is written + * to the index register at I/O address = port + 5. The value is then read + * from the data register at I/O address = port + 6. This value is ANDed + * with the mask value and then ORed with the or value. Finally, the + * new value is written to the data register at I/O address = port + 6. + * + * Parameters: + * @param[in] u16 port = The address of the port index register. + * @param[in] u8 reg = The offset within the indexed space. + * @param[in] u8 mask = The mask value to apply to the data register value. + * @param[in] u8 or = The or value to apply to the data register value. + */ +static inline void pnp_update_hwm5_index(u16 base, u8 reg, u8 mask, u8 or) +{ + pnp_update_index(base + 5, reg, mask, or); +} + #endif /* DEVICE_PNP_HWM5_CONF_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42134 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica01211af2a9a00aed98880844a836f6b7957b14 Gerrit-Change-Number: 42134 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/mtkheader: Port gen-bl-img.py to python3
by Yilin Yang (Code Review) 18 Sep '20

18 Sep '20

Yilin Yang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45440 ) Change subject: util/mtkheader: Port gen-bl-img.py to python3 ...................................................................... util/mtkheader: Port gen-bl-img.py to python3 Test steps : 1. Use python2 script 2. Run `emerge-board coreboot` twice, so we get bootblock.bin.1 and bootblock.bin.2 3. Run `xxd` on these two bootblock so we get bootblock.bin.1.hex and bootblock.bin.2.hex 4. `diff bootblock.bin.1.hex bootblock.bin.2.hex` and record the difference. (at least, the time info changes) 5. Migrate to python3 6. Similar steps, we get bootblock.bin.py3.hex 7. `diff bootblock.bin.1.hex bootblock.bin.py3.hex`, the difference is similar. BUG=chromium:1023662 Signed-off-by: Yilin Yang <kerker(a)google.com> Change-Id: I788e7c9b09257142728a0f76df8c2ccc72bf6b3b --- M util/mtkheader/gen-bl-img.py 1 file changed, 17 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/45440/1 diff --git a/util/mtkheader/gen-bl-img.py b/util/mtkheader/gen-bl-img.py index 282dfbf..1627a79 100755 --- a/util/mtkheader/gen-bl-img.py +++ b/util/mtkheader/gen-bl-img.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python2 +#!/usr/bin/env python3 # # SPDX-License-Identifier: GPL-2.0-only @@ -14,10 +14,10 @@ with open(path, 'wb') as f: f.write(data) -def padding(data, size, pattern='\0'): +def padding(data, size, pattern=b'\0'): return data + pattern * (size - len(data)) -def align(data, size, pattern='\0'): +def align(data, size, pattern=b'\0'): return padding(data, (len(data) + (size - 1)) & ~(size - 1), pattern) def gen_gfh_info(chip, data): @@ -47,19 +47,19 @@ return gfh def gen_emmc_header(data): - header = (padding(struct.pack('<12sII', 'EMMC_BOOT', 1, 512), 512, '\xff') + - padding(struct.pack('<8sIIIIIIII', 'BRLYT', 1, 2048, 2048 + len(data), - 0x42424242, 0x00010005, 2048, 2048 + len(data), 1) + '\0' * 140, 512, - '\xff') + - '\0' * 1024) + header = (padding(struct.pack('<12sII', b'EMMC_BOOT', 1, 512), 512, b'\xff') + + padding(struct.pack('<8sIIIIIIII', b'BRLYT', 1, 2048, 2048 + len(data), + 0x42424242, 0x00010005, 2048, 2048 + len(data), 1) + b'\0' * 140, 512, + b'\xff') + + b'\0' * 1024) return header def gen_sf_header(data): - header = (padding(struct.pack('<12sII', 'SF_BOOT', 1, 512), 512, '\xff') + - padding(struct.pack('<8sIIIIIIII', 'BRLYT', 1, 2048, 2048 + len(data), - 0x42424242, 0x00010007, 2048, 2048 + len(data), 1) + '\0' * 140, 512, - '\xff') + - '\0' * 1024) + header = (padding(struct.pack('<12sII', b'SF_BOOT', 1, 512), 512, b'\xff') + + padding(struct.pack('<8sIIIIIIII', b'BRLYT', 1, 2048, 2048 + len(data), + 0x42424242, 0x00010007, 2048, 2048 + len(data), 1) + b'\0' * 140, 512, + b'\xff') + + b'\0' * 1024) return header gen_dev_header = { @@ -71,15 +71,15 @@ gfh_info = gen_gfh_info(chip_ver, data) gfh_hash = hashlib.sha256(gfh_info + data).digest() - data = align(gfh_info + data + gfh_hash, 512, '\xff') + data = align(gfh_info + data + gfh_hash, 512, b'\xff') header = gen_dev_header[flash_type](data) return header + data def main(argv): if len(argv) != 5: - print 'Usage: %s <chip> <flash_type> <input_file> <output_file>' % argv[0] - print '\t flash_type: emmc|sf' - print '\t chip : mt8173|mt8183' + print('Usage: %s <chip> <flash_type> <input_file> <output_file>' % argv[0]) + print('\t flash_type: emmc|sf') + print('\t chip : mt8173|mt8183') exit(1) write(argv[4], gen_preloader(argv[1], argv[2], read(argv[3]))) -- To view, visit https://review.coreboot.org/c/coreboot/+/45440 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I788e7c9b09257142728a0f76df8c2ccc72bf6b3b Gerrit-Change-Number: 45440 Gerrit-PatchSet: 1 Gerrit-Owner: Yilin Yang <kerker(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel: cnl,icl,elh,jsl,tgl: enable C6DRAM
by Nico Huber (Code Review) 18 Sep '20

18 Sep '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45417 ) Change subject: soc/intel: cnl,icl,elh,jsl,tgl: enable C6DRAM ...................................................................... Patch Set 6: > > > What about adding a Kconfig (default n) instead? > > > > How about removing the option entirely? We already have > > enough unused options ;) > > Huh? Remove an option just because some ucode breaks it? This is a power-saving option we definitely should *not* remove entirely. It was unused, hence we would effectively not remove any functionality. And yes, it's a power-saving option. That means without some business backup, it will likely never be really tested. People start testing and say "it boots". But this option has no effect on booting at all. If you wanted to test this on a single unit with a single ucode revision, I'd suggest that you use this unit for a few years without making any more changes just to see if it is stable ;) If it trips once per year and somebody would sell 1,000 units, that would mean roughly 3 units trip per day. So really, we don't have the means to test this properly. If you can find some documentation about when it is safe to use, it would be a completely different story, IMHO. But until then, why present an option that would need a warning in the help text? -- To view, visit https://review.coreboot.org/c/coreboot/+/45417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I556dba59bc06c9101bdfdfd6aee00610aac516e3 Gerrit-Change-Number: 45417 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Andrew McRae <amcrae(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jonas Löffelholz <jonas.loeffelholz(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 18 Sep 2020 08:47:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/system76/lemp9: drop disabled options from devicetree
by Michael Niewöhner (Code Review) 18 Sep '20

18 Sep '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45491 ) Change subject: mb/system76/lemp9: drop disabled options from devicetree ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/45491/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45491/1//COMMIT_MSG@7 PS1, Line 7: registers > options Done -- To view, visit https://review.coreboot.org/c/coreboot/+/45491 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a1a91778e83dc49c6dcf2d518cd3591f7ec4cfa Gerrit-Change-Number: 45491 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 18 Sep 2020 08:21:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/system76/lemp9: enable SATA ALPM capability
by Michael Niewöhner (Code Review) 18 Sep '20

18 Sep '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45492 ) Change subject: mb/system76/lemp9: enable SATA ALPM capability ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/45492/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45492/1//COMMIT_MSG@11 PS1, Line 11: Tested successfully. > How? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/45492 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88de28cfb266af3fcd6e498a08a24b46c992cb9d Gerrit-Change-Number: 45492 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 18 Sep 2020 08:20:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: comment

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Change in coreboot[master]: util/exynos: Port *_cksum.py to python3
by Yilin Yang (Code Review) 18 Sep '20

18 Sep '20

Yilin Yang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45460 ) Change subject: util/exynos: Port *_cksum.py to python3 ...................................................................... util/exynos: Port *_cksum.py to python3 BUG=chromium:1023662 TEST=1. Create a tiny file `in.txt` as input 2. Run `fixed_cksum.py in.txt out.txt 20` with py2 and py3 version, the output is the same 3. Run `variable_cksum.py in.txt out.txt` with py2 and py3 version, the output is the same Signed-off-by: Yilin Yang <kerker(a)google.com> Change-Id: I9428269dfb826a3a95fffef9ea3f7c1a7107ef84 --- M util/exynos/fixed_cksum.py M util/exynos/variable_cksum.py 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/45460/1 diff --git a/util/exynos/fixed_cksum.py b/util/exynos/fixed_cksum.py index c6a9ddae..0ae7e4f 100755 --- a/util/exynos/fixed_cksum.py +++ b/util/exynos/fixed_cksum.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python2 +#!/usr/bin/env python3 # # SPDX-License-Identifier: BSD-3-Clause @@ -28,7 +28,7 @@ checksum_size = struct.calcsize(checksum_format) data_size = size - checksum_size assert len(data) <= data_size - checksum = struct.pack(checksum_format, sum(map(ord, data))) + checksum = struct.pack(checksum_format, sum(data)) out_file.write(data + bytearray(data_size - len(data)) + checksum) diff --git a/util/exynos/variable_cksum.py b/util/exynos/variable_cksum.py index 62a76cc..4321f8e 100755 --- a/util/exynos/variable_cksum.py +++ b/util/exynos/variable_cksum.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python2 +#!/usr/bin/env python3 # # SPDX-License-Identifier: BSD-3-Clause @@ -27,7 +27,7 @@ data = in_file.read() header = struct.pack(header_format, struct.calcsize(header_format) + len(data), - sum(map(ord, data)), + sum(data), 0, 0) out_file.write(header + data) -- To view, visit https://review.coreboot.org/c/coreboot/+/45460 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9428269dfb826a3a95fffef9ea3f7c1a7107ef84 Gerrit-Change-Number: 45460 Gerrit-PatchSet: 1 Gerrit-Owner: Yilin Yang <kerker(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/system76/lemp9: drop disabled options from devicetree
by Michael Niewöhner (Code Review) 18 Sep '20

18 Sep '20

Hello Felix Singer, build bot (Jenkins), Jeremy Soller, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45491 to look at the new patch set (#3). Change subject: mb/system76/lemp9: drop disabled options from devicetree ...................................................................... mb/system76/lemp9: drop disabled options from devicetree Drop all options with zero-value, since they already default to 0. Change-Id: I2a1a91778e83dc49c6dcf2d518cd3591f7ec4cfa Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/system76/lemp9/devicetree.cb 1 file changed, 0 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/45491/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/45491 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a1a91778e83dc49c6dcf2d518cd3591f7ec4cfa Gerrit-Change-Number: 45491 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit September 2020