Yilin Yang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45447 )
Change subject: util/rockchip: Port make_idb.py to python3 ......................................................................
util/rockchip: Port make_idb.py to python3
BUG=chromium:1023662
Signed-off-by: Yilin Yang kerker@google.com Change-Id: I04253084ec9b65310c52598b629390051cd2172b --- M util/rockchip/make_idb.py 1 file changed, 26 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/45447/1
diff --git a/util/rockchip/make_idb.py b/util/rockchip/make_idb.py index 12cd130..c633d4d 100755 --- a/util/rockchip/make_idb.py +++ b/util/rockchip/make_idb.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python2 +#!/usr/bin/env python3 # SPDX-License-Identifier: BSD-2-Clause
import struct @@ -7,7 +7,7 @@
class IDBTool: def __init__(self): - print "Initialize IDBTool" + print("Initialize IDBTool")
def p_rc4(self, buf, length): key = (124,78,3,4,85,5,9,7,45,44,123,56,23,13,23,17) @@ -27,6 +27,13 @@ k = (S[i] + S[j]) % 256 buf[x] = struct.pack('B', ord(buf[x]) ^ S[k])
+ def bytesToList(self, byte_string): + ret = [] + for ch in byte_string: + ret.append(bytes((ch,))) + + return ret + def makeIDB(self, chip, from_file, to_file, rc4_flag = False, align_flag = False): try: fin = open(from_file, 'rb') @@ -50,23 +57,23 @@ sectors = pages * PAGE_ALIGN;
buf = [B'\0'] * sectors * SECTOR_SIZE - buf[:4] = chip - buf[4 : 4+data_len] = data + buf[:4] = self.bytesToList(chip) + buf[4 : 4+data_len] = self.bytesToList(data)
idblock = [B'\0'] * 4 * SECTOR_SIZE blank = [B'\0'] * 4 * SECTOR_SIZE - idblock[:4] = ['\x55', '\xAA', '\xF0', '\x0F'] + idblock[:4] = [b'\x55', b'\xAA', b'\xF0', b'\x0F']
if (not rc4_flag): - idblock[8:12] = struct.pack("<I", 1) + idblock[8:12] = self.bytesToList(struct.pack("<I", 1)) else: for i in range(sectors): list_tmp = buf[SECTOR_SIZE*i : SECTOR_SIZE*(i+1)] self.p_rc4(list_tmp, SECTOR_SIZE) buf[SECTOR_SIZE*i : SECTOR_SIZE*(i+1)] = list_tmp
- idblock[12:16] = struct.pack("<HH", 4, 4); - idblock[506:510] = struct.pack("<HH", sectors, sectors); + idblock[12:16] = self.bytesToList(struct.pack("<HH", 4, 4)) + idblock[506:510] = self.bytesToList(struct.pack("<HH", sectors, sectors)) self.p_rc4(idblock, SECTOR_SIZE)
try: @@ -76,25 +83,25 @@
try: if (align_flag): - fout.write(''.join(idblock)) - fout.write(''.join(blank)) + fout.write(b''.join(idblock)) + fout.write(b''.join(blank))
- for s in xrange(0, sectors * SECTOR_SIZE, PAGE_ALIGN * SECTOR_SIZE): - fout.write(''.join(buf[s : s + PAGE_ALIGN * SECTOR_SIZE])) - fout.write(''.join(blank)) + for s in range(0, sectors * SECTOR_SIZE, PAGE_ALIGN * SECTOR_SIZE): + fout.write(b''.join(buf[s : s + PAGE_ALIGN * SECTOR_SIZE])) + fout.write(b''.join(blank)) else: - fout.write(''.join(idblock)) - fout.write(''.join(buf)) + fout.write(b''.join(idblock)) + fout.write(b''.join(buf)) fout.flush() except: sys.exit("Failed to write data to : " + to_file) finally: fout.close() - print "DONE" + print("DONE")
def usage(): - print "Usage: make_idb.py [--chip=RKXX] [--enable-rc4] [--enable-align] [--to=out] --from=in" - print " --chip: default is RK32" + print("Usage: make_idb.py [--chip=RKXX] [--enable-rc4] [--enable-align] [--to=out] --from=in") + print(" --chip: default is RK32")
if __name__ == '__main__': rc4_flag = align_flag = False @@ -123,4 +130,4 @@ sys.exit()
idbtool = IDBTool() - idbtool.makeIDB(chip, from_file, to_file, rc4_flag, align_flag) + idbtool.makeIDB(chip.encode('utf-8'), from_file, to_file, rc4_flag, align_flag)
Hello build bot (Jenkins), Julius Werner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45447
to look at the new patch set (#2).
Change subject: util/rockchip: Port make_idb.py to python3 ......................................................................
util/rockchip: Port make_idb.py to python3
BUG=chromium:1023662
Signed-off-by: Yilin Yang kerker@google.com Change-Id: I04253084ec9b65310c52598b629390051cd2172b --- M util/rockchip/make_idb.py 1 file changed, 29 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/45447/2
Hello build bot (Jenkins), Julius Werner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45447
to look at the new patch set (#3).
Change subject: util/rockchip: Port make_idb.py to python3 ......................................................................
util/rockchip: Port make_idb.py to python3
BUG=chromium:1023662 TEST=buildbot pass
Signed-off-by: Yilin Yang kerker@google.com Change-Id: I04253084ec9b65310c52598b629390051cd2172b --- M util/rockchip/make_idb.py 1 file changed, 29 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/45447/3
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45447 )
Change subject: util/rockchip: Port make_idb.py to python3 ......................................................................
Patch Set 3: Code-Review+1
not sure if 'buildbot pass' is sufficient.
From RK Makefile, the make_idb is something just like mtk's gen-bl-image.
Can you build the config 'gru' (rk3399), and compare if the bootblock.bin looks the same?
Hello Hung-Te Lin, build bot (Jenkins), Julius Werner, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45447
to look at the new patch set (#4).
Change subject: util/rockchip: Port make_idb.py to python3 ......................................................................
util/rockchip: Port make_idb.py to python3
BUG=chromium:1023662 TEST=buildbot pass TEST=1. Use python2 script 2. Run `emerge-kevin coreboot` twice, so we get bootblock.bin.1 and bootblock.bin.2 3. Run `xxd` on these two bootblock so we get bootblock.bin.1.hex and bootblock.bin.2.hex 4. `diff bootblock.bin.1.hex bootblock.bin.2.hex` and record the difference. (at least, the time info changes) 5. Migrate to python3 6. Similar steps, we get bootblock.bin.py3.hex 7. `diff bootblock.bin.1.hex bootblock.bin.py3.hex`, the difference is similar. (time info, git hash changes)
Signed-off-by: Yilin Yang kerker@google.com Change-Id: I04253084ec9b65310c52598b629390051cd2172b --- M util/rockchip/make_idb.py 1 file changed, 29 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/45447/4
Yilin Yang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45447 )
Change subject: util/rockchip: Port make_idb.py to python3 ......................................................................
Patch Set 4:
Patch Set 3: Code-Review+1
not sure if 'buildbot pass' is sufficient.
From RK Makefile, the make_idb is something just like mtk's gen-bl-image.
Can you build the config 'gru' (rk3399), and compare if the bootblock.bin looks the same?
Sure, I tried the similar steps with kevin board, and it works!
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45447 )
Change subject: util/rockchip: Port make_idb.py to python3 ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45447/4/util/rockchip/make_idb.py File util/rockchip/make_idb.py:
https://review.coreboot.org/c/coreboot/+/45447/4/util/rockchip/make_idb.py@1 PS4, Line 1: #!/usr/bin/env python3 Can it be ported in a way, that it’s compatible with Python 2 and 3, so only `python` is used.
Yilin Yang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45447 )
Change subject: util/rockchip: Port make_idb.py to python3 ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45447/4/util/rockchip/make_idb.py File util/rockchip/make_idb.py:
https://review.coreboot.org/c/coreboot/+/45447/4/util/rockchip/make_idb.py@1 PS4, Line 1: #!/usr/bin/env python3
Can it be ported in a way, that it’s compatible with Python 2 and 3, so only `python` is used.
Sometimes it's possible, if there is no complicated string issue. But python2 is totally out of support now, is there any reason that we want to support both version ?
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45447 )
Change subject: util/rockchip: Port make_idb.py to python3 ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45447/4/util/rockchip/make_idb.py File util/rockchip/make_idb.py:
https://review.coreboot.org/c/coreboot/+/45447/4/util/rockchip/make_idb.py@1 PS4, Line 1: #!/usr/bin/env python3
Sometimes it's possible, if there is no complicated string issue. […]
I agree with kerker. Python 2 is EOL now and we should migrate that to python3, so having that in shebang is more clear.
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45447 )
Change subject: util/rockchip: Port make_idb.py to python3 ......................................................................
Patch Set 4:
Please also update util/README.md and description.md
Hello Hung-Te Lin, build bot (Jenkins), Julius Werner, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45447
to look at the new patch set (#5).
Change subject: util/rockchip: Port make_idb.py to python3 ......................................................................
util/rockchip: Port make_idb.py to python3
BUG=chromium:1023662 TEST=buildbot pass TEST=1. Use python2 script 2. Run `emerge-kevin coreboot` twice, so we get bootblock.bin.1 and bootblock.bin.2 3. Run `xxd` on these two bootblock so we get bootblock.bin.1.hex and bootblock.bin.2.hex 4. `diff bootblock.bin.1.hex bootblock.bin.2.hex` and record the difference. (at least, the time info changes) 5. Migrate to python3 6. Similar steps, we get bootblock.bin.py3.hex 7. `diff bootblock.bin.1.hex bootblock.bin.py3.hex`, the difference is similar. (time info, git hash changes)
Signed-off-by: Yilin Yang kerker@google.com Change-Id: I04253084ec9b65310c52598b629390051cd2172b --- M util/README.md M util/rockchip/description.md M util/rockchip/make_idb.py 3 files changed, 31 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/45447/5
Yilin Yang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45447 )
Change subject: util/rockchip: Port make_idb.py to python3 ......................................................................
Patch Set 5:
Patch Set 4:
Please also update util/README.md and description.md
Done~
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45447 )
Change subject: util/rockchip: Port make_idb.py to python3 ......................................................................
Patch Set 5: Code-Review+2
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45447 )
Change subject: util/rockchip: Port make_idb.py to python3 ......................................................................
Patch Set 5:
(3 comments)
https://review.coreboot.org/c/coreboot/+/45447/5/util/rockchip/make_idb.py File util/rockchip/make_idb.py:
https://review.coreboot.org/c/coreboot/+/45447/5/util/rockchip/make_idb.py@5... PS5, Line 59: B b for consistency. Or use "B" consistently throughout this file.
https://review.coreboot.org/c/coreboot/+/45447/5/util/rockchip/make_idb.py@6... PS5, Line 60: buf[:4] = self.bytesToList(chip) If we're modifying it like this, I think we should use bytearray, which simplfies things:
buf = bytearray(sectors * SECTOR_SIZE) buf[:4] = chip buf[4 : 4+data_len] = data
Writing to file also becomes simpler:
fout.write(buf)
https://review.coreboot.org/c/coreboot/+/45447/5/util/rockchip/make_idb.py@1... PS5, Line 133: chip.encode('utf-8') It's better to encode 'chip' inside makeIDB() in my opinion.
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45447 )
Change subject: util/rockchip: Port make_idb.py to python3 ......................................................................
Patch Set 5: -Code-Review
Hello Hung-Te Lin, build bot (Jenkins), Julius Werner, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45447
to look at the new patch set (#6).
Change subject: util/rockchip: Port make_idb.py to python3 ......................................................................
util/rockchip: Port make_idb.py to python3
BUG=chromium:1023662 TEST=buildbot pass TEST=1. Use python2 script 2. Run `emerge-kevin coreboot` twice, so we get bootblock.bin.1 and bootblock.bin.2 3. Run `xxd` on these two bootblock so we get bootblock.bin.1.hex and bootblock.bin.2.hex 4. `diff bootblock.bin.1.hex bootblock.bin.2.hex` and record the difference. (at least, the time info changes) 5. Migrate to python3 6. Similar steps, we get bootblock.bin.py3.hex 7. `diff bootblock.bin.1.hex bootblock.bin.py3.hex`, the difference is similar. (time info, git hash changes)
Signed-off-by: Yilin Yang kerker@google.com Change-Id: I04253084ec9b65310c52598b629390051cd2172b --- M util/README.md M util/rockchip/description.md M util/rockchip/make_idb.py 3 files changed, 25 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/45447/6
Yilin Yang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45447 )
Change subject: util/rockchip: Port make_idb.py to python3 ......................................................................
Patch Set 6:
(3 comments)
https://review.coreboot.org/c/coreboot/+/45447/5/util/rockchip/make_idb.py File util/rockchip/make_idb.py:
https://review.coreboot.org/c/coreboot/+/45447/5/util/rockchip/make_idb.py@5... PS5, Line 59: B
b for consistency. Or use "B" consistently throughout this file.
Done
https://review.coreboot.org/c/coreboot/+/45447/5/util/rockchip/make_idb.py@6... PS5, Line 60: buf[:4] = self.bytesToList(chip)
If we're modifying it like this, I think we should use bytearray, which simplfies things: […]
Done. Thanks, it's better!
https://review.coreboot.org/c/coreboot/+/45447/5/util/rockchip/make_idb.py@1... PS5, Line 133: chip.encode('utf-8')
It's better to encode 'chip' inside makeIDB() in my opinion.
Done
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45447 )
Change subject: util/rockchip: Port make_idb.py to python3 ......................................................................
Patch Set 6: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/45447/6/util/rockchip/make_idb.py File util/rockchip/make_idb.py:
https://review.coreboot.org/c/coreboot/+/45447/6/util/rockchip/make_idb.py@5... PS6, Line 53: utf-8 Safer to use 'ascii' here?
Yilin Yang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45447 )
Change subject: util/rockchip: Port make_idb.py to python3 ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45447/6/util/rockchip/make_idb.py File util/rockchip/make_idb.py:
https://review.coreboot.org/c/coreboot/+/45447/6/util/rockchip/make_idb.py@5... PS6, Line 53: utf-8
Safer to use 'ascii' here?
I think utf-8 is more general.
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45447 )
Change subject: util/rockchip: Port make_idb.py to python3 ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45447/6/util/rockchip/make_idb.py File util/rockchip/make_idb.py:
https://review.coreboot.org/c/coreboot/+/45447/6/util/rockchip/make_idb.py@5... PS6, Line 53: utf-8
I think utf-8 is more general.
Do we need to make sure that len(chip.encode(...)) == 4? Otherwise, len(buf) will potentially be different from 'sectors * SECTOR_SIZE'.
Yilin Yang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45447 )
Change subject: util/rockchip: Port make_idb.py to python3 ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45447/6/util/rockchip/make_idb.py File util/rockchip/make_idb.py:
https://review.coreboot.org/c/coreboot/+/45447/6/util/rockchip/make_idb.py@5... PS6, Line 53: utf-8
Do we need to make sure that len(chip.encode(... […]
I thought that before, but I think as long as the input (e.g. chip) was correct before, then it should be correct now. So I don't add any check for the migration.
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45447 )
Change subject: util/rockchip: Port make_idb.py to python3 ......................................................................
Patch Set 6: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/45447/6/util/rockchip/make_idb.py File util/rockchip/make_idb.py:
https://review.coreboot.org/c/coreboot/+/45447/6/util/rockchip/make_idb.py@5... PS6, Line 53: utf-8
I thought that before, but I think as long as the input (e.g. […]
That's a reasonable argument. Let's keep it as is.
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45447 )
Change subject: util/rockchip: Port make_idb.py to python3 ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45447/6/util/rockchip/make_idb.py File util/rockchip/make_idb.py:
https://review.coreboot.org/c/coreboot/+/45447/6/util/rockchip/make_idb.py@5... PS6, Line 53: utf-8
I thought that before, but I think as long as the input (e.g. […]
Although in current implementation them seem to always input something you can type (e.g., ASCII), I'd recommend selecting either 'ascii' (and fail if >0x80) or 'latin-1' (which supports raw mapping from 0x00~0xff).
Encoding to utf-8 implies if the user specified something > 0x80, then we won't fail and will be generating unexpected contents (longer than 4).
And an assert may be a better idea especially python3 is handling bytes and string very different.
Hello Hung-Te Lin, build bot (Jenkins), Julius Werner, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45447
to look at the new patch set (#7).
Change subject: util/rockchip: Port make_idb.py to python3 ......................................................................
util/rockchip: Port make_idb.py to python3
BUG=chromium:1023662 TEST=buildbot pass TEST=1. Use python2 script 2. Run `emerge-kevin coreboot` twice, so we get bootblock.bin.1 and bootblock.bin.2 3. Run `xxd` on these two bootblock so we get bootblock.bin.1.hex and bootblock.bin.2.hex 4. `diff bootblock.bin.1.hex bootblock.bin.2.hex` and record the difference. (at least, the time info changes) 5. Migrate to python3 6. Similar steps, we get bootblock.bin.py3.hex 7. `diff bootblock.bin.1.hex bootblock.bin.py3.hex`, the difference is similar. (time info, git hash changes)
Signed-off-by: Yilin Yang kerker@google.com Change-Id: I04253084ec9b65310c52598b629390051cd2172b --- M util/README.md M util/rockchip/description.md M util/rockchip/make_idb.py 3 files changed, 26 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/45447/7
Yilin Yang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45447 )
Change subject: util/rockchip: Port make_idb.py to python3 ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45447/6/util/rockchip/make_idb.py File util/rockchip/make_idb.py:
https://review.coreboot.org/c/coreboot/+/45447/6/util/rockchip/make_idb.py@5... PS6, Line 53: utf-8
Although in current implementation them seem to always input something you can type (e.g. […]
Done~ I make it throw exception when the length is not 4.
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45447 )
Change subject: util/rockchip: Port make_idb.py to python3 ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45447/7/util/rockchip/make_idb.py File util/rockchip/make_idb.py:
https://review.coreboot.org/c/coreboot/+/45447/7/util/rockchip/make_idb.py@5... PS7, Line 53: assert len(chip.encode('ascii')) == 4 Either
assert len(chip) == 4
since encoding in ascii should preserve length, or,
chip_bytes = chip.encode('ascii') assert len(chip_bytes) == 4 buf[:4] = chip_bytes
to avoid encoding twice.
Hello Hung-Te Lin, build bot (Jenkins), Julius Werner, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45447
to look at the new patch set (#8).
Change subject: util/rockchip: Port make_idb.py to python3 ......................................................................
util/rockchip: Port make_idb.py to python3
BUG=chromium:1023662 TEST=buildbot pass TEST=1. Use python2 script 2. Run `emerge-kevin coreboot` twice, so we get bootblock.bin.1 and bootblock.bin.2 3. Run `xxd` on these two bootblock so we get bootblock.bin.1.hex and bootblock.bin.2.hex 4. `diff bootblock.bin.1.hex bootblock.bin.2.hex` and record the difference. (at least, the time info changes) 5. Migrate to python3 6. Similar steps, we get bootblock.bin.py3.hex 7. `diff bootblock.bin.1.hex bootblock.bin.py3.hex`, the difference is similar. (time info, git hash changes)
Signed-off-by: Yilin Yang kerker@google.com Change-Id: I04253084ec9b65310c52598b629390051cd2172b --- M util/README.md M util/rockchip/description.md M util/rockchip/make_idb.py 3 files changed, 26 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/45447/8
Yilin Yang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45447 )
Change subject: util/rockchip: Port make_idb.py to python3 ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45447/7/util/rockchip/make_idb.py File util/rockchip/make_idb.py:
https://review.coreboot.org/c/coreboot/+/45447/7/util/rockchip/make_idb.py@5... PS7, Line 53: assert len(chip.encode('ascii')) == 4
Either […]
Done
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45447 )
Change subject: util/rockchip: Port make_idb.py to python3 ......................................................................
Patch Set 8: Code-Review+2
Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45447 )
Change subject: util/rockchip: Port make_idb.py to python3 ......................................................................
util/rockchip: Port make_idb.py to python3
BUG=chromium:1023662 TEST=buildbot pass TEST=1. Use python2 script 2. Run `emerge-kevin coreboot` twice, so we get bootblock.bin.1 and bootblock.bin.2 3. Run `xxd` on these two bootblock so we get bootblock.bin.1.hex and bootblock.bin.2.hex 4. `diff bootblock.bin.1.hex bootblock.bin.2.hex` and record the difference. (at least, the time info changes) 5. Migrate to python3 6. Similar steps, we get bootblock.bin.py3.hex 7. `diff bootblock.bin.1.hex bootblock.bin.py3.hex`, the difference is similar. (time info, git hash changes)
Signed-off-by: Yilin Yang kerker@google.com Change-Id: I04253084ec9b65310c52598b629390051cd2172b Reviewed-on: https://review.coreboot.org/c/coreboot/+/45447 Reviewed-by: Yu-Ping Wu yupingso@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M util/README.md M util/rockchip/description.md M util/rockchip/make_idb.py 3 files changed, 26 insertions(+), 25 deletions(-)
Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved
diff --git a/util/README.md b/util/README.md index 4b2fe38..778c83e 100644 --- a/util/README.md +++ b/util/README.md @@ -83,7 +83,7 @@ can be passed to SPIKE, the RISC-V reference emulator.`Bash` * _sifive-gpt.py_ - Wraps the bootblock in a GPT partition for SiFive's bootrom. `Python3` -* __rockchip__ - Generate Rockchip idblock bootloader. `Python2` +* __rockchip__ - Generate Rockchip idblock bootloader. `Python3` * __sconfig__ - coreboot device tree compiler `Lex` `Yacc` * __scripts__ * _config_ - Manipulate options in a .config file from the diff --git a/util/rockchip/description.md b/util/rockchip/description.md index 3eed7a6..e482d1e 100644 --- a/util/rockchip/description.md +++ b/util/rockchip/description.md @@ -1 +1 @@ -Generate Rockchip idblock bootloader. `Python2` +Generate Rockchip idblock bootloader. `Python3` diff --git a/util/rockchip/make_idb.py b/util/rockchip/make_idb.py index 12cd130..ff82e73 100755 --- a/util/rockchip/make_idb.py +++ b/util/rockchip/make_idb.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python2 +#!/usr/bin/env python3 # SPDX-License-Identifier: BSD-2-Clause
import struct @@ -7,7 +7,7 @@
class IDBTool: def __init__(self): - print "Initialize IDBTool" + print("Initialize IDBTool")
def p_rc4(self, buf, length): key = (124,78,3,4,85,5,9,7,45,44,123,56,23,13,23,17) @@ -25,7 +25,7 @@ j = (j + S[i]) % 256 temp = S[i]; S[i] = S[j]; S[j] = temp k = (S[i] + S[j]) % 256 - buf[x] = struct.pack('B', ord(buf[x]) ^ S[k]) + buf[x] = struct.pack('B', buf[x] ^ S[k])[0]
def makeIDB(self, chip, from_file, to_file, rc4_flag = False, align_flag = False): try: @@ -45,17 +45,18 @@ data_len = len(data) SECTOR_SIZE = 512 PAGE_ALIGN = 4 - sectors = (data_len + 4 - 1) / SECTOR_SIZE + 1 - pages = (sectors - 1) / PAGE_ALIGN + 1 - sectors = pages * PAGE_ALIGN; + sectors = (data_len + 4 - 1) // SECTOR_SIZE + 1 + pages = (sectors - 1) // PAGE_ALIGN + 1 + sectors = pages * PAGE_ALIGN
- buf = [B'\0'] * sectors * SECTOR_SIZE - buf[:4] = chip + buf = bytearray(sectors * SECTOR_SIZE) + assert len(chip) == 4 + buf[:4] = chip.encode('ascii') buf[4 : 4+data_len] = data
- idblock = [B'\0'] * 4 * SECTOR_SIZE - blank = [B'\0'] * 4 * SECTOR_SIZE - idblock[:4] = ['\x55', '\xAA', '\xF0', '\x0F'] + idblock = bytearray(4 * SECTOR_SIZE) + blank = bytearray(4 * SECTOR_SIZE) + idblock[:4] = b'\x55\xAA\xF0\x0F'
if (not rc4_flag): idblock[8:12] = struct.pack("<I", 1) @@ -65,8 +66,8 @@ self.p_rc4(list_tmp, SECTOR_SIZE) buf[SECTOR_SIZE*i : SECTOR_SIZE*(i+1)] = list_tmp
- idblock[12:16] = struct.pack("<HH", 4, 4); - idblock[506:510] = struct.pack("<HH", sectors, sectors); + idblock[12:16] = struct.pack("<HH", 4, 4) + idblock[506:510] = struct.pack("<HH", sectors, sectors) self.p_rc4(idblock, SECTOR_SIZE)
try: @@ -76,25 +77,25 @@
try: if (align_flag): - fout.write(''.join(idblock)) - fout.write(''.join(blank)) + fout.write(idblock) + fout.write(blank)
- for s in xrange(0, sectors * SECTOR_SIZE, PAGE_ALIGN * SECTOR_SIZE): - fout.write(''.join(buf[s : s + PAGE_ALIGN * SECTOR_SIZE])) - fout.write(''.join(blank)) + for s in range(0, sectors * SECTOR_SIZE, PAGE_ALIGN * SECTOR_SIZE): + fout.write(buf[s : s + PAGE_ALIGN * SECTOR_SIZE]) + fout.write(blank) else: - fout.write(''.join(idblock)) - fout.write(''.join(buf)) + fout.write(idblock) + fout.write(buf) fout.flush() except: sys.exit("Failed to write data to : " + to_file) finally: fout.close() - print "DONE" + print("DONE")
def usage(): - print "Usage: make_idb.py [--chip=RKXX] [--enable-rc4] [--enable-align] [--to=out] --from=in" - print " --chip: default is RK32" + print("Usage: make_idb.py [--chip=RKXX] [--enable-rc4] [--enable-align] [--to=out] --from=in") + print(" --chip: default is RK32")
if __name__ == '__main__': rc4_flag = align_flag = False
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45447 )
Change subject: util/rockchip: Port make_idb.py to python3 ......................................................................
Patch Set 9:
Automatic boot test returned (PASS/FAIL/TOTAL): 8/1/9 "QEMU x86 q35/ich9" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/19954 "QEMU x86 q35/ich9" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/19953 "QEMU x86 i440fx/piix4" (x86_64) using payload SeaBIOS : FAIL : https://lava.9esec.io/r/19952 "QEMU x86 i440fx/piix4" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/19951 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/19950 "HP Z220 SFF Workstation" (x86_32) using payload LinuxBoot_BusyBox_kexec : SUCCESS : https://lava.9esec.io/r/19958 "HP Z220 SFF Workstation" (x86_32) using payload LinuxBoot_BusyBox_kexec : SUCCESS : https://lava.9esec.io/r/19957 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/19956 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/19955
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Hung-Te Lin (Code Review)
-
Paul Menzel (Code Review)
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Yilin Yang (Code Review)
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Yu-Ping Wu (Code Review)