Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45542 )
Change subject: mb/Kconfig: add option for selecting the default state of s0ix
......................................................................
Patch Set 1:
This change is ready for review.
--
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Gerrit-Branch: master
Gerrit-Change-Id: I3a29cc1187ceb4f2ce9a6cc3deed8764e0f26691
Gerrit-Change-Number: 45542
Gerrit-PatchSet: 1
Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de>
Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com>
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Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-Comment-Date: Sat, 19 Sep 2020 09:19:23 +0000
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Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45469 )
Change subject: mb/{google,intel,siemens}/devicetree.cb: Enable CSE device
......................................................................
mb/{google,intel,siemens}/devicetree.cb: Enable CSE device
Enable CSE PCI device Bus 0: Device 0x0f: Function 0x00 to let
Intel common cse block code can use this device.
Calling me_read_config32(offset) function from ramstage:
Without this CL:
HECI: Global Reset(Type:1) Command
BUG: me_read_config32 requests hidden 00:0f.0
PCI: dev is NULL!
With this CL:
HECI: Global Reset(Type:1) Command
HECI: Global Reset success!
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
Change-Id: I97d221ae52b4b03ecd859d708847ad77fe4bf465
---
M src/mainboard/google/reef/variants/baseboard/devicetree.cb
M src/mainboard/google/reef/variants/coral/devicetree.cb
M src/mainboard/google/reef/variants/pyro/devicetree.cb
M src/mainboard/google/reef/variants/sand/devicetree.cb
M src/mainboard/google/reef/variants/snappy/devicetree.cb
M src/mainboard/intel/apollolake_rvp/devicetree.cb
M src/mainboard/intel/leafhill/devicetree.cb
M src/mainboard/intel/minnow3/devicetree.cb
M src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
M src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
M src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb
M src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb
M src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb
M src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
14 files changed, 14 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/45469/1
diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb
index 4c35bd2..4c93096 100644
--- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb
@@ -139,6 +139,7 @@
device generic 0 on end
end
end
+ device pci 0f.0 on end # - CSE
device pci 11.0 off end # - ISH
device pci 12.0 off end # - SATA
device pci 13.0 off end # - Root Port 2 - PCIe-A 0
diff --git a/src/mainboard/google/reef/variants/coral/devicetree.cb b/src/mainboard/google/reef/variants/coral/devicetree.cb
index f987e1d..249e2c8 100644
--- a/src/mainboard/google/reef/variants/coral/devicetree.cb
+++ b/src/mainboard/google/reef/variants/coral/devicetree.cb
@@ -139,6 +139,7 @@
device generic 0 on end
end
end
+ device pci 0f.0 on end # - CSE
device pci 11.0 off end # - ISH
device pci 12.0 off end # - SATA
device pci 13.0 off end # - Root Port 2 - PCIe-A 0
diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb
index 1282edb..9ed1c4c 100644
--- a/src/mainboard/google/reef/variants/pyro/devicetree.cb
+++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb
@@ -148,6 +148,7 @@
device generic 0 on end
end
end
+ device pci 0f.0 on end # - CSE
device pci 11.0 off end # - ISH
device pci 12.0 off end # - SATA
device pci 13.0 off end # - Root Port 2 - PCIe-A 0
diff --git a/src/mainboard/google/reef/variants/sand/devicetree.cb b/src/mainboard/google/reef/variants/sand/devicetree.cb
index ad76a91..0b1134c 100644
--- a/src/mainboard/google/reef/variants/sand/devicetree.cb
+++ b/src/mainboard/google/reef/variants/sand/devicetree.cb
@@ -135,6 +135,7 @@
device generic 0 on end
end
end
+ device pci 0f.0 on end # - CSE
device pci 11.0 off end # - ISH
device pci 12.0 off end # - SATA
device pci 13.0 off end # - Root Port 2 - PCIe-A 0
diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb
index a82400f..fdd84dd 100644
--- a/src/mainboard/google/reef/variants/snappy/devicetree.cb
+++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb
@@ -144,6 +144,7 @@
device generic 0 on end
end
end
+ device pci 0f.0 on end # - CSE
device pci 11.0 off end # - ISH
device pci 12.0 off end # - SATA
device pci 13.0 off end # - Root Port 2 - PCIe-A 0
diff --git a/src/mainboard/intel/apollolake_rvp/devicetree.cb b/src/mainboard/intel/apollolake_rvp/devicetree.cb
index f7e82a0..dd12a5b 100644
--- a/src/mainboard/intel/apollolake_rvp/devicetree.cb
+++ b/src/mainboard/intel/apollolake_rvp/devicetree.cb
@@ -22,6 +22,7 @@
device pci 0d.2 on end # - SPI
device pci 0d.3 on end # - Shared SRAM
device pci 0e.0 on end # - Audio
+ device pci 0f.0 on end # - CSE
device pci 11.0 on end # - ISH
device pci 12.0 on end # - SATA
device pci 13.0 on end # - PCIe-A 0
diff --git a/src/mainboard/intel/leafhill/devicetree.cb b/src/mainboard/intel/leafhill/devicetree.cb
index 6c872b1..e2f2f8e 100644
--- a/src/mainboard/intel/leafhill/devicetree.cb
+++ b/src/mainboard/intel/leafhill/devicetree.cb
@@ -22,6 +22,7 @@
device pci 0d.2 on end # - SPI
device pci 0d.3 on end # - Shared SRAM
device pci 0e.0 on end # - Audio
+ device pci 0f.0 on end # - CSE
device pci 11.0 on end # - ISH
device pci 12.0 on end # - SATA
device pci 13.0 on end # - PCIe-A 0
diff --git a/src/mainboard/intel/minnow3/devicetree.cb b/src/mainboard/intel/minnow3/devicetree.cb
index 6c872b1..e2f2f8e 100644
--- a/src/mainboard/intel/minnow3/devicetree.cb
+++ b/src/mainboard/intel/minnow3/devicetree.cb
@@ -22,6 +22,7 @@
device pci 0d.2 on end # - SPI
device pci 0d.3 on end # - Shared SRAM
device pci 0e.0 on end # - Audio
+ device pci 0f.0 on end # - CSE
device pci 11.0 on end # - ISH
device pci 12.0 on end # - SATA
device pci 13.0 on end # - PCIe-A 0
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
index 0e72fcf..c927dcc 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
@@ -69,6 +69,7 @@
device pci 0d.2 on end # - SPI
device pci 0d.3 off end # - Shared SRAM
device pci 0e.0 on end # - Audio
+ device pci 0f.0 on end # - CSE
device pci 11.0 on end # - ISH
device pci 12.0 on end # - SATA
device pci 13.0 on end # - RP 2 - PCIe A 0 - MACPHY
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
index bee531f..8887929 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
@@ -61,6 +61,7 @@
device pci 0d.2 on end # - SPI
device pci 0d.3 off end # - Shared SRAM
device pci 0e.0 on end # - Audio
+ device pci 0f.0 on end # - CSE
device pci 11.0 on end # - ISH
device pci 12.0 on end # - SATA
device pci 13.0 on end # - RP 2 - PCIe A 0
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb
index e1e79b4..9747292 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb
@@ -57,6 +57,7 @@
device pci 0d.2 on end # - SPI
device pci 0d.3 off end # - Shared SRAM
device pci 0e.0 on end # - Audio
+ device pci 0f.0 on end # - CSE
device pci 11.0 on end # - ISH
device pci 12.0 on end # - SATA
device pci 13.0 on end # - RP 2 - PCIe A 0
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb
index be50408..89fa45e9 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb
@@ -58,6 +58,7 @@
device pci 0d.2 on end # - SPI
device pci 0d.3 off end # - Shared SRAM
device pci 0e.0 on end # - Audio
+ device pci 0f.0 on end # - CSE
device pci 11.0 on end # - ISH
device pci 12.0 on end # - SATA
device pci 13.0 on end # - RP 2 - PCIe A 0
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb
index 33664fe..05ec8b4 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb
@@ -60,6 +60,7 @@
device pci 0d.2 on end # - SPI
device pci 0d.3 off end # - Shared SRAM
device pci 0e.0 on end # - Audio
+ device pci 0f.0 on end # - CSE
device pci 11.0 on end # - ISH
device pci 12.0 on end # - SATA
device pci 13.0 on end # - RP 2 - PCIe A 0
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
index a865f9f..4b0367f 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
@@ -28,6 +28,7 @@
device pci 0d.2 on end # - SPI
device pci 0d.3 off end # - Shared SRAM
device pci 0e.0 on end # - Audio
+ device pci 0f.0 on end # - CSE
device pci 11.0 on end # - ISH
device pci 12.0 on end # - SATA
device pci 13.0 on end # - RP 2 - PCIe A 0
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I97d221ae52b4b03ecd859d708847ad77fe4bf465
Gerrit-Change-Number: 45469
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-MessageType: newchange
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45341 )
Change subject: soc/intel/common/block/cse: Add helper function cse_send_global_reset
......................................................................
soc/intel/common/block/cse: Add helper function cse_send_global_reset
Sends GLOBAL_RESET_REQ cmd to CSE.
1. Check if CSE is enable from devicetree.cb
2. Ensure CSE in Normal Mode prior sending global reset command
3. If not in normal mode then send error status
4. If in normal mode then only call cse_request_global_reset() to
send global reset command
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
Change-Id: I3668b473bec8d51f847908d11e2e25c485ec7a97
---
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/include/intelblocks/cse.h
2 files changed, 28 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/45341/1
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index 4b598e2..90afdcf 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -663,6 +663,25 @@
return status;
}
+int cse_send_global_reset(void)
+{
+ int status = -1;
+ union me_hfsts1 hfs1;
+
+ if (!is_cse_enabled())
+ goto ret;
+
+ /* Check ME operating mode */
+ hfs1.data = me_read_config32(PCI_ME_HFSTS1);
+ if (hfs1.fields.operation_mode)
+ goto ret;
+
+ /* ME should be in Normal Mode for this command */
+ status = cse_request_global_reset(GLOBAL_RESET);
+ret:
+ return status;
+}
+
static bool cse_is_hmrfpo_enable_allowed(void)
{
/*
diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h
index a67010c..9804b0d 100644
--- a/src/soc/intel/common/block/include/intelblocks/cse.h
+++ b/src/soc/intel/common/block/include/intelblocks/cse.h
@@ -126,7 +126,15 @@
* Returns 0 on failure and 1 on success.
*/
int cse_request_global_reset(enum rst_req_type rst_type);
-
+/*
+ * Sends GLOBAL_RESET_REQ cmd to CSE.
+ * 1. Check if CSE is enable from devicetree.cb
+ * 2. Ensure CSE in Normal Mode prior sending global reset command
+ * 3. If not in normal mode then send error status
+ * 4. If in normal mode then only call cse_request_global_reset() to send global reset command
+ * Returns 0 on failure and 1 on success.
+ */
+int cse_send_global_reset(void);
/*
* Sends HMRFPO_ENABLE command.
* HMRFPO - Host ME Region Flash Protection Override.
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I3668b473bec8d51f847908d11e2e25c485ec7a97
Gerrit-Change-Number: 45341
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newchange
Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44036 )
Change subject: sconfig: Add function for parse+override of tree
......................................................................
sconfig: Add function for parse+override of tree
Extract the steps to parse and override a devicetree into a function
so it can be used multiple times without copying the same logic.
Change-Id: I4e496a223757beb22e3bd678eb6115968bd32529
Signed-off-by: Duncan Laurie <dlaurie(a)google.com>
---
M util/sconfig/main.c
1 file changed, 14 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/44036/1
diff --git a/util/sconfig/main.c b/util/sconfig/main.c
index 66f9cbf..251aa3f 100644
--- a/util/sconfig/main.c
+++ b/util/sconfig/main.c
@@ -1666,6 +1666,18 @@
}
}
+static void parse_override_devicetree(const char *file, struct device *dev)
+{
+ parse_devicetree(file, dev->bus);
+
+ if (!dev_has_children(dev)) {
+ fprintf(stderr, "ERROR: Override tree needs at least one device!\n");
+ exit(1);
+ }
+
+ override_devicetree(&base_root_bus, dev->bus);
+}
+
int main(int argc, char **argv)
{
static const struct option long_options[] = {
@@ -1708,16 +1720,8 @@
parse_devicetree(base_devtree, &base_root_bus);
- if (override_devtree) {
- parse_devicetree(override_devtree, &override_root_bus);
-
- if (!dev_has_children(&override_root_dev)) {
- fprintf(stderr, "ERROR: Override tree needs at least one device!\n");
- exit(1);
- }
-
- override_devicetree(&base_root_bus, &override_root_bus);
- }
+ if (override_devtree)
+ parse_override_devicetree(override_devtree, &override_root_dev);
FILE *autogen = fopen(outputc, "w");
if (!autogen) {
--
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Gerrit-Change-Id: I4e496a223757beb22e3bd678eb6115968bd32529
Gerrit-Change-Number: 44036
Gerrit-PatchSet: 1
Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-MessageType: newchange