coreboot-gerrit September 2020

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Change in coreboot[master]: sconfig: Add function for parse+override of tree
by Duncan Laurie (Code Review) 18 Sep '20

18 Sep '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44036 ) Change subject: sconfig: Add function for parse+override of tree ...................................................................... sconfig: Add function for parse+override of tree Extract the steps to parse and override a devicetree into a function so it can be used multiple times without copying the same logic. Change-Id: I4e496a223757beb22e3bd678eb6115968bd32529 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M util/sconfig/main.c 1 file changed, 14 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/44036/1 diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 66f9cbf..251aa3f 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -1666,6 +1666,18 @@ } } +static void parse_override_devicetree(const char *file, struct device *dev) +{ + parse_devicetree(file, dev->bus); + + if (!dev_has_children(dev)) { + fprintf(stderr, "ERROR: Override tree needs at least one device!\n"); + exit(1); + } + + override_devicetree(&base_root_bus, dev->bus); +} + int main(int argc, char **argv) { static const struct option long_options[] = { @@ -1708,16 +1720,8 @@ parse_devicetree(base_devtree, &base_root_bus); - if (override_devtree) { - parse_devicetree(override_devtree, &override_root_bus); - - if (!dev_has_children(&override_root_dev)) { - fprintf(stderr, "ERROR: Override tree needs at least one device!\n"); - exit(1); - } - - override_devicetree(&base_root_bus, &override_root_bus); - } + if (override_devtree) + parse_override_devicetree(override_devtree, &override_root_dev); FILE *autogen = fopen(outputc, "w"); if (!autogen) { -- To view, visit https://review.coreboot.org/c/coreboot/+/44036 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e496a223757beb22e3bd678eb6115968bd32529 Gerrit-Change-Number: 44036 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/tglrvp: Enable HECI interface
by Angel Pons (Code Review) 18 Sep '20

18 Sep '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42307 ) Change subject: mb/intel/tglrvp: Enable HECI interface ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/42307 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23117fa96503942e6a72765dd3fd1cc762e3f705 Gerrit-Change-Number: 42307 Gerrit-PatchSet: 10 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 18 Sep 2020 23:06:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/tglrvp: Enable HECI interface
by Jamie Ryu (Code Review) 18 Sep '20

18 Sep '20

Jamie Ryu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42307 ) Change subject: mb/intel/tglrvp: Enable HECI interface ...................................................................... Patch Set 8: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/42307/4//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/42307/4//COMMIT_MSG@11 PS4, Line 11: > Could you please add this information in the commit message? Done. Thanks for comments! I just added this to the commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/42307 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23117fa96503942e6a72765dd3fd1cc762e3f705 Gerrit-Change-Number: 42307 Gerrit-PatchSet: 8 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 18 Sep 2020 22:31:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Jamie Ryu <jamie.m.ryu(a)intel.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/tglrvp: Enable HECI interface
by Jamie Ryu (Code Review) 18 Sep '20

18 Sep '20

Hello build bot (Jenkins), Patrick Georgi, Furquan Shaikh, Wonkyu Kim, Rizwan Qureshi, Angel Pons, Tim Wawrzynczak, Shreesh Chhabbi, Patrick Rudolph, Tim Wawrzynczak, Nick Vaccaro, Raj Astekar, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/42307 to look at the new patch set (#8). Change subject: mb/intel/tglrvp: Enable HECI interface ...................................................................... mb/intel/tglrvp: Enable HECI interface This is to enable Intel ME communication interface HECI1 by devicetree for PAVP with CSE Lite. PAVP feature is enabled with CSE Lite SKU for Chrome and HECI1 interface is required between kernel and CSE Lite. BUG=None TEST=Build and boot tglrvp. Run lspci and check pcie device 00:16.0 Communication controller: Intel Corporation Device a0e0 Change-Id: I23117fa96503942e6a72765dd3fd1cc762e3f705 Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/42307/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/42307 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23117fa96503942e6a72765dd3fd1cc762e3f705 Gerrit-Change-Number: 42307 Gerrit-PatchSet: 8 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/tglrvp: Enable HECI interface
by Angel Pons (Code Review) 18 Sep '20

18 Sep '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42307 ) Change subject: mb/intel/tglrvp: Enable HECI interface ...................................................................... Patch Set 7: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/42307/4//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/42307/4//COMMIT_MSG@11 PS4, Line 11: > PAVP feature is enabled with CSE Lite SKU for Chrome and it requires HECI1 interface to open the int […] Could you please add this information in the commit message? -- To view, visit https://review.coreboot.org/c/coreboot/+/42307 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23117fa96503942e6a72765dd3fd1cc762e3f705 Gerrit-Change-Number: 42307 Gerrit-PatchSet: 7 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 18 Sep 2020 22:24:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Jamie Ryu <jamie.m.ryu(a)intel.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/acpi: add code for CPPC entries generation
by Michael Niewöhner (Code Review) 18 Sep '20

18 Sep '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45535 ) Change subject: soc/intel/common/block/acpi: add code for CPPC entries generation ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/45535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fcc2d0d7c6b6f35f8dd011f55dab8469be99d47 Gerrit-Change-Number: 45535 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Fri, 18 Sep 2020 22:15:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{cnl,icl,jsl,tgl}/acpi: generate CPPC entries
by Michael Niewöhner (Code Review) 18 Sep '20

18 Sep '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45536 ) Change subject: soc/intel/{cnl,icl,jsl,tgl}/acpi: generate CPPC entries ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/45536 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40d47d18a35002bc9ec55473e94277d89fc5797e Gerrit-Change-Number: 45536 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Fri, 18 Sep 2020 22:15:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/tglrvp: Enable HECI interface
by Shreesh Chhabbi (Code Review) 18 Sep '20

18 Sep '20

Shreesh Chhabbi has uploaded a new patch set (#7) to the change originally created by Jamie Ryu. ( https://review.coreboot.org/c/coreboot/+/42307 ) Change subject: mb/intel/tglrvp: Enable HECI interface ...................................................................... mb/intel/tglrvp: Enable HECI interface This is to enable Intel ME communication interface HECI1 by devicetree for PAVP with CSE Lite. BUG=None TEST=Build and boot tglrvp. Run lspci and check pcie device 00:16.0 Communication controller: Intel Corporation Device a0e0 Change-Id: I23117fa96503942e6a72765dd3fd1cc762e3f705 Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/42307/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/42307 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23117fa96503942e6a72765dd3fd1cc762e3f705 Gerrit-Change-Number: 42307 Gerrit-PatchSet: 7 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: trogdor: Move EN_PP3300_DX_EDP for Coachz
by Julius Werner (Code Review) 18 Sep '20

18 Sep '20

Hello Douglas Anderson, Philip Chen, Bob Moragues, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45306 to review the following change. Change subject: trogdor: Move EN_PP3300_DX_EDP for Coachz ...................................................................... trogdor: Move EN_PP3300_DX_EDP for Coachz This patch updates the display power enable GPIO which moved from 30 to 52 for Coachz. Veterans of this project know that there's no point trying to ask *why* this change was necessary -- the pins move in mysterious ways and all we can do is watch and wonder. Pin 30 is now used for a new camera reset GPIO... surely, there must have been some excellent reason why that pin couldn't just have become pin 52 instead. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I00ad6a6249df66006b4f2b953a0a2449bd478f6d --- M src/mainboard/google/trogdor/board.h 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/45306/1 diff --git a/src/mainboard/google/trogdor/board.h b/src/mainboard/google/trogdor/board.h index 39661b5..4d38378 100644 --- a/src/mainboard/google/trogdor/board.h +++ b/src/mainboard/google/trogdor/board.h @@ -16,7 +16,8 @@ /* Display specific GPIOS */ #define GPIO_BACKLIGHT_ENABLE GPIO(12) #define GPIO_EDP_BRIDGE_ENABLE (CONFIG(TROGDOR_REV0) ? GPIO(14) : GPIO(104)) -#define GPIO_EN_PP3300_DX_EDP (CONFIG(TROGDOR_REV0) ? GPIO(106) : GPIO(30)) +#define GPIO_EN_PP3300_DX_EDP (CONFIG(TROGDOR_REV0) ? GPIO(106) : \ + (CONFIG(BOARD_GOOGLE_COACHZ) ? GPIO(52) : GPIO(30))) void setup_chromeos_gpios(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/45306 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00ad6a6249df66006b4f2b953a0a2449bd478f6d Gerrit-Change-Number: 45306 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Bob Moragues <moragues(a)chromium.org> Gerrit-Reviewer: Douglas Anderson <dianders(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sconfig: Switch to getopt
by Duncan Laurie (Code Review) 18 Sep '20

18 Sep '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44035 ) Change subject: sconfig: Switch to getopt ...................................................................... sconfig: Switch to getopt Instead of positional arguments switch sconfig to use getopt and pass the arguments as options in the build system. This will make it easier to add additional options. Change-Id: I431633781e80362e086c000b7108191b5b01aa9d Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M Makefile.inc M util/sconfig/main.c 2 files changed, 50 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/44035/1 diff --git a/Makefile.inc b/Makefile.inc index a51b73d..dc1c6e0 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -592,19 +592,23 @@ # Creation of these is architecture and mainboard independent DEVICETREE_FILE := $(src)/mainboard/$(MAINBOARDDIR)/$(CONFIG_DEVICETREE) +SCONFIG_OPTIONS := --mainboard_devtree=$(DEVICETREE_FILE) + ifneq ($(CONFIG_OVERRIDE_DEVICETREE),) - OVERRIDE_DEVICETREE_FILE := $(src)/mainboard/$(MAINBOARDDIR)/$(CONFIG_OVERRIDE_DEVICETREE) - +SCONFIG_OPTIONS += --override_devtree=$(OVERRIDE_DEVICETREE_FILE) endif DEVICETREE_STATIC_C := $(obj)/mainboard/$(MAINBOARDDIR)/static.c +SCONFIG_OPTIONS += --output_c=$(DEVICETREE_STATIC_C) + DEVICETREE_STATIC_H := $(obj)/static.h +SCONFIG_OPTIONS += --output_h=$(DEVICETREE_STATIC_H) $(DEVICETREE_STATIC_C): $(DEVICETREE_FILE) $(OVERRIDE_DEVICETREE_FILE) $(objutil)/sconfig/sconfig @printf " SCONFIG $(subst $(src)/,,$(<))\n" mkdir -p $(dir $(DEVICETREE_STATIC_C)) - $(objutil)/sconfig/sconfig $(DEVICETREE_FILE) $(DEVICETREE_STATIC_C) $(DEVICETREE_STATIC_H) $(OVERRIDE_DEVICETREE_FILE) + $(objutil)/sconfig/sconfig $(SCONFIG_OPTIONS) ramstage-y+=$(DEVICETREE_STATIC_C) romstage-y+=$(DEVICETREE_STATIC_C) diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 170acad..66f9cbf 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -2,6 +2,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <ctype.h> +#include <getopt.h> /* stat.h needs to be included before commonlib/helpers.h to avoid errors.*/ #include <sys/stat.h> #include <commonlib/helpers.h> @@ -1309,21 +1310,14 @@ static void usage(void) { - printf("usage: sconfig devicetree_file output_file header_file [override_devicetree_file]\n"); + printf("usage: sconfig <options>\n"); + printf(" -c | --output_c : Output static.c file (required)\n"); + printf(" -r | --output_h : Header static.h file (required)\n"); + printf(" -m | --mainboard_devtree : Mainboard devicetree file (required)\n"); + printf(" -o | --override_devtree : Override devicetree file (optional)\n"); exit(1); } -enum { - DEVICEFILE_ARG = 1, - OUTPUTFILE_ARG, - HEADERFILE_ARG, - OVERRIDE_DEVICEFILE_ARG, -}; - -#define MANDATORY_ARG_COUNT 4 -#define OPTIONAL_ARG_COUNT 1 -#define TOTAL_ARG_COUNT (MANDATORY_ARG_COUNT + OPTIONAL_ARG_COUNT) - static void parse_devicetree(const char *file, struct bus *parent) { FILE *filec = fopen(file, "r"); @@ -1674,18 +1668,47 @@ int main(int argc, char **argv) { - if ((argc < MANDATORY_ARG_COUNT) || (argc > TOTAL_ARG_COUNT)) - usage(); + static const struct option long_options[] = { + { "mainboard_devtree", 1, NULL, 'm' }, + { "override_devtree", 1, NULL, 'o' }, + { "output_c", 1, NULL, 'c' }, + { "output_h", 1, NULL, 'r' }, + { "help", 1, NULL, 'h' }, + { } + }; + const char *override_devtree = NULL; + const char *base_devtree = NULL; + const char *outputc = NULL; + const char *outputh = NULL; + int opt, option_index; - const char *base_devtree = argv[DEVICEFILE_ARG]; - const char *outputc = argv[OUTPUTFILE_ARG]; - const char *outputh = argv[HEADERFILE_ARG]; - const char *override_devtree; + while ((opt = getopt_long(argc, argv, "m:o:c:r:h", long_options, + &option_index)) != EOF) { + switch (opt) { + case 'm': + base_devtree = strdup(optarg); + break; + case 'o': + override_devtree = strdup(optarg); + break; + case 'c': + outputc = strdup(optarg); + break; + case 'r': + outputh = strdup(optarg); + break; + case 'h': + default: + usage(); + } + } + + if (!base_devtree || !outputc || !outputh) + usage(); parse_devicetree(base_devtree, &base_root_bus); - if (argc == TOTAL_ARG_COUNT) { - override_devtree = argv[OVERRIDE_DEVICEFILE_ARG]; + if (override_devtree) { parse_devicetree(override_devtree, &override_root_bus); if (!dev_has_children(&override_root_dev)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/44035 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I431633781e80362e086c000b7108191b5b01aa9d Gerrit-Change-Number: 44035 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit September 2020