coreboot-gerrit May 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/volteer: add generic SPDs
by Nick Vaccaro (Code Review) 08 May '20

08 May '20

Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40463 ) Change subject: mb/google/volteer: add generic SPDs ...................................................................... Patch Set 20: (1 comment) https://review.coreboot.org/c/coreboot/+/40463/16/src/mainboard/google/volt… File src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_2R_32Gb_QDP_4266.spd.hex: PS16: > > Yes, Micron/Hynix (SPD_LPDDR4X_200b_2R_32Gb_QDP_4267) and Samsung (SPD_LPDDR4X_200b_2R_32Gb_QDP_42 […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/40463 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4cd148e28efe458f2b312a7f1c5b6d71e8ef433 Gerrit-Change-Number: 40463 Gerrit-PatchSet: 20 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Dossym Nurmukhanov <dossym(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 08 May 2020 17:15:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: commonlib/region: Add region_overlap
by Patrick Rudolph (Code Review) 08 May '20

08 May '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41083 ) Change subject: commonlib/region: Add region_overlap ...................................................................... commonlib/region: Add region_overlap Add inline function to check if two regions overlap. Change-Id: I6f3dfaa9f0805893bd691ba64f112944d89a8e71 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/commonlib/include/commonlib/region.h 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/41083/1 diff --git a/src/commonlib/include/commonlib/region.h b/src/commonlib/include/commonlib/region.h index 86b9ee3..cf5d2a6 100644 --- a/src/commonlib/include/commonlib/region.h +++ b/src/commonlib/include/commonlib/region.h @@ -117,6 +117,12 @@ return region_offset(r) + region_sz(r); } +static inline bool region_overlap(const struct region *r1, const struct region *r2) +{ + return (region_end(r1) > region_offset(r2)) && + (region_offset(r1) < region_end(r2)); +} + static inline const struct region *region_device_region( const struct region_device *rdev) { -- To view, visit https://review.coreboot.org/c/coreboot/+/41083 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f3dfaa9f0805893bd691ba64f112944d89a8e71 Gerrit-Change-Number: 41083 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

5 5

Change in coreboot[master]: sb/intel/i82371eb: Replace GPLv2 long form headers with SPDX header
by HAOUAS Elyes (Code Review) 08 May '20

08 May '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41129 ) Change subject: sb/intel/i82371eb: Replace GPLv2 long form headers with SPDX header ...................................................................... sb/intel/i82371eb: Replace GPLv2 long form headers with SPDX header Change-Id: If54234ec2d80d5a6502400eb1c6f02dd9bba73c5 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/i82371eb/fadt.c 1 file changed, 2 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/41129/1 diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index 3240221..77801e4 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -1,17 +1,8 @@ /* This file is part of the coreboot project. */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /* * Based on src/southbridge/via/vt8237r/vt8237_fadt.c - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <string.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/41129 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If54234ec2d80d5a6502400eb1c6f02dd9bba73c5 Gerrit-Change-Number: 41129 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

5 4

Change in coreboot[master]: sb/intel/i82371eb: Fix iasl warning
by Keith Hui (Code Review) 08 May '20

08 May '20

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41094 ) Change subject: sb/intel/i82371eb: Fix iasl warning ...................................................................... sb/intel/i82371eb: Fix iasl warning The backslash on the very last line is not needed and causes an iasl warning. Change-Id: I27e78bc34b9386dd014db5880a104693b4f0db5a Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/southbridge/intel/i82371eb/acpi/intx.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/41094/1 diff --git a/src/southbridge/intel/i82371eb/acpi/intx.asl b/src/southbridge/intel/i82371eb/acpi/intx.asl index c1dc508..fe2c180 100644 --- a/src/southbridge/intel/i82371eb/acpi/intx.asl +++ b/src/southbridge/intel/i82371eb/acpi/intx.asl @@ -45,4 +45,4 @@ } \ Store(Local0, pinx) \ } \ -} \ +} -- To view, visit https://review.coreboot.org/c/coreboot/+/41094 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27e78bc34b9386dd014db5880a104693b4f0db5a Gerrit-Change-Number: 41094 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: security: tcg-2.0: Improve error response handling, fix Cr50 boot mode
by Julius Werner (Code Review) 08 May '20

08 May '20

Hello Vadim Bendebury, Andrey Pronin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/41100 to review the following change. Change subject: security: tcg-2.0: Improve error response handling, fix Cr50 boot mode ...................................................................... security: tcg-2.0: Improve error response handling, fix Cr50 boot mode This patch imrpoves the response buffer handling for some TPM 2.0 commands in error cases. Previously we would just allow any command to return no payload -- with this patch, only commands with errors are accepted without payload as a default, for other commands the command-specific unmarshalling code decides the expected response length. Also explicitly confirm that the amount of data received matches the response header. For vendor commands, we additionally allow errors to have an empty payload after the subcommand code. This fixes a problem with the Cr50 GET_BOOT_MODE command where an error response would only return the subcommand code but no data after that. Also add support for a second, slightly different NO_SUCH_COMMAND error code that was added in Cr50 recently. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: Ib85032d85482d5484180be6fd105f2467f393cd2 --- M src/security/tpm/tss/tcg-2.0/tss_marshaling.c M src/security/tpm/tss/vendor/cr50/cr50.c M src/security/tpm/tss/vendor/cr50/cr50.h 3 files changed, 29 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/41100/1 diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c index a229dd1..ce0ee5e 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c @@ -546,29 +546,33 @@ return 0; } -static int unmarshal_vendor_command(struct ibuf *ib, - struct vendor_command_response *vcr) +static int unmarshal_vendor_command(struct ibuf *ib, struct tpm2_response *resp) { - if (ibuf_read_be16(ib, &vcr->vc_subcommand)) + if (ibuf_read_be16(ib, &resp->vcr.vc_subcommand)) return -1; - switch (vcr->vc_subcommand) { + /* On errors, some subcommands do not return a payload. */ + if (resp->hdr.tpm_code != TPM2_RC_SUCCESS && + ibuf_nr_read(ib) == resp->hdr.tpm_size) + return 0; + + switch (resp->vcr.vc_subcommand) { case TPM2_CR50_SUB_CMD_IMMEDIATE_RESET: break; case TPM2_CR50_SUB_CMD_NVMEM_ENABLE_COMMITS: break; case TPM2_CR50_SUB_CMD_TURN_UPDATE_ON: - return ibuf_read_be8(ib, &vcr->num_restored_headers); + return ibuf_read_be8(ib, &resp->vcr.num_restored_headers); case TPM2_CR50_SUB_CMD_GET_REC_BTN: - return ibuf_read_be8(ib, &vcr->recovery_button_state); + return ibuf_read_be8(ib, &resp->vcr.recovery_button_state); case TPM2_CR50_SUB_CMD_TPM_MODE: - return ibuf_read_be8(ib, &vcr->tpm_mode); + return ibuf_read_be8(ib, &resp->vcr.tpm_mode); case TPM2_CR50_SUB_CMD_GET_BOOT_MODE: - return ibuf_read_be8(ib, &vcr->boot_mode); + return ibuf_read_be8(ib, &resp->vcr.boot_mode); default: printk(BIOS_ERR, "%s:%d - unsupported vendor command %#04x!\n", - __func__, __LINE__, vcr->vc_subcommand); + __func__, __LINE__, resp->vcr.vc_subcommand); return -1; } @@ -587,14 +591,18 @@ if (rc != 0) return NULL; - if (ibuf_remaining(ib) == 0) { - if (tpm2_static_resp.hdr.tpm_size != ibuf_nr_read(ib)) - printk(BIOS_ERR, - "%s: size mismatch in response to command %#x\n", - __func__, command); - return &tpm2_static_resp; + if (ibuf_remaining(ib) != tpm2_static_resp.hdr.tpm_size - 10) { + printk(BIOS_ERR, + "%s: size mismatch in response to command %#x\n", + __func__, command); + return NULL; } + /* On errors, some commands do not return a payload. */ + if (tpm2_static_resp.hdr.tpm_code != TPM2_RC_SUCCESS && + ibuf_remaining(ib) == 0) + return &tpm2_static_resp; + switch (command) { case TPM2_Startup: case TPM2_Shutdown: @@ -620,7 +628,7 @@ break; case TPM2_CR50_VENDOR_COMMAND: - rc |= unmarshal_vendor_command(ib, &tpm2_static_resp.vcr); + rc |= unmarshal_vendor_command(ib, &tpm2_static_resp); break; default: diff --git a/src/security/tpm/tss/vendor/cr50/cr50.c b/src/security/tpm/tss/vendor/cr50/cr50.c index ae2f7c2..d7bf48d 100644 --- a/src/security/tpm/tss/vendor/cr50/cr50.c +++ b/src/security/tpm/tss/vendor/cr50/cr50.c @@ -89,7 +89,8 @@ return TPM_E_MUST_REBOOT; } - if (response->hdr.tpm_code == VENDOR_RC_NO_SUCH_COMMAND) { + if (response->hdr.tpm_code == VENDOR_RC_NO_SUCH_COMMAND || + response->hdr.tpm_code == VENDOR_RC_NO_SUCH_SUBCOMMAND) { /* * Explicitly inform caller when command is not supported */ @@ -119,7 +120,8 @@ if (!response) return TPM_E_IOERROR; - if (response->hdr.tpm_code == VENDOR_RC_NO_SUCH_COMMAND) + if (response->hdr.tpm_code == VENDOR_RC_NO_SUCH_COMMAND || + response->hdr.tpm_code == VENDOR_RC_NO_SUCH_SUBCOMMAND) /* Explicitly inform caller when command is not supported */ return TPM_E_NO_SUCH_COMMAND; diff --git a/src/security/tpm/tss/vendor/cr50/cr50.h b/src/security/tpm/tss/vendor/cr50/cr50.h index 0f91732..e3146a4 100644 --- a/src/security/tpm/tss/vendor/cr50/cr50.h +++ b/src/security/tpm/tss/vendor/cr50/cr50.h @@ -21,6 +21,7 @@ #define VENDOR_RC_ERR 0x00000500 enum cr50_vendor_rc { VENDOR_RC_INTERNAL_ERROR = (VENDOR_RC_ERR | 6), + VENDOR_RC_NO_SUCH_SUBCOMMAND = (VENDOR_RC_ERR | 8), VENDOR_RC_NO_SUCH_COMMAND = (VENDOR_RC_ERR | 127), }; -- To view, visit https://review.coreboot.org/c/coreboot/+/41100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib85032d85482d5484180be6fd105f2467f393cd2 Gerrit-Change-Number: 41100 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Andrey Pronin <apronin(a)chromium.org> Gerrit-Reviewer: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-MessageType: newchange

4 25

Change in coreboot[master]: memrange: Break early from memranges_find_entry if limit is crossed
by Furquan Shaikh (Code Review) 08 May '20

08 May '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41104 ) Change subject: memrange: Break early from memranges_find_entry if limit is crossed ...................................................................... memrange: Break early from memranges_find_entry if limit is crossed This change updates memranges_find_entry() to break and return early if the end address of the hole within the current range entry crosses the requested limit. This is because all range entries and maintained in increasing order and so none of the following range entries can satisfy the given request. Change-Id: I14e03946ddbbb5d254b23e9a9917da42960313a6 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/lib/memrange.c 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/41104/1 diff --git a/src/lib/memrange.c b/src/lib/memrange.c index 32f053d..bc827d3 100644 --- a/src/lib/memrange.c +++ b/src/lib/memrange.c @@ -400,8 +400,13 @@ if (end > r->end) continue; + /* + * If end for the hole in the current range entry goes beyond the requested + * limit, then none of the following ranges can satisfy this request because all + * range entries are maintained in increasing order. + */ if (end > limit) - continue; + break; return r; } -- To view, visit https://review.coreboot.org/c/coreboot/+/41104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14e03946ddbbb5d254b23e9a9917da42960313a6 Gerrit-Change-Number: 41104 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: memrange: Update comment to indicate limit is inclusive for memranges...
by Furquan Shaikh (Code Review) 08 May '20

08 May '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41103 ) Change subject: memrange: Update comment to indicate limit is inclusive for memranges_next_entry ...................................................................... memrange: Update comment to indicate limit is inclusive for memranges_next_entry This change updates the comment for memranges_next_entry() to indicate that the limit provided by the caller is inclusive. Change-Id: Id40263efcb9417ed31c130996e56c30dbbc82e02 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/include/memrange.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/41103/1 diff --git a/src/include/memrange.h b/src/include/memrange.h index 2579f20..faeef2e 100644 --- a/src/include/memrange.h +++ b/src/include/memrange.h @@ -162,7 +162,7 @@ const struct range_entry *r); /* Steals memory from the available list in given ranges as per the constraints: - * limit = Upper bound for the memory range to steal. + * limit = Upper bound for the memory range to steal (Inclusive). * size = Requested size for the stolen memory. * align = Required alignment(log 2) for the starting address of the stolen memory. * tag = Use a range that matches the given tag. -- To view, visit https://review.coreboot.org/c/coreboot/+/41103 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id40263efcb9417ed31c130996e56c30dbbc82e02 Gerrit-Change-Number: 41103 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: sb/intel/bd82x6x: Put temp BAR in a define
by Angel Pons (Code Review) 08 May '20

08 May '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41111 ) Change subject: sb/intel/bd82x6x: Put temp BAR in a define ...................................................................... sb/intel/bd82x6x: Put temp BAR in a define We use a temporary BAR value to program the thermal settings. To make this more obvious, factor it out. Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change. Change-Id: Icda6e4100d954fe28d2624270b5d7ab7ed155e32 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/early_thermal.c 1 file changed, 14 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/41111/1 diff --git a/src/southbridge/intel/bd82x6x/early_thermal.c b/src/southbridge/intel/bd82x6x/early_thermal.c index e73f3a5..6519a24 100644 --- a/src/southbridge/intel/bd82x6x/early_thermal.c +++ b/src/southbridge/intel/bd82x6x/early_thermal.c @@ -22,6 +22,9 @@ return read16((u16 *)addr); } +/* Temporary thermal BAR value */ +#define TBARB_TEMP 0x40000000 + /* Early thermal init, must be done prior to giving ME its memory which is done at the end of raminit. */ void early_thermal_init(void) @@ -32,31 +35,31 @@ dev = PCI_DEV(0x0, 0x1f, 0x6); /* Program address for temporary BAR. */ - pci_write_config32(dev, 0x40, 0x40000000); + pci_write_config32(dev, 0x40, TBARB_TEMP); pci_write_config32(dev, 0x44, 0x0); /* Activate temporary BAR. */ pci_write_config32(dev, 0x40, pci_read_config32(dev, 0x40) | 5); + write16p(TBARB_TEMP + 0x04, 0x3a2b); - write16p(0x40000004, 0x3a2b); - write8p(0x4000000c, 0xff); - write8p(0x4000000d, 0x00); - write8p(0x4000000e, 0x40); - write8p(0x40000082, 0x00); - write8p(0x40000001, 0xba); + write8p(TBARB_TEMP + 0x0c, 0xff); + write8p(TBARB_TEMP + 0x0d, 0x00); + write8p(TBARB_TEMP + 0x0e, 0x40); + write8p(TBARB_TEMP + 0x82, 0x00); + write8p(TBARB_TEMP + 0x01, 0xba); /* Perform init. */ /* Configure TJmax. */ msr = rdmsr(MSR_TEMPERATURE_TARGET); - write16p(0x40000012, ((msr.lo >> 16) & 0xff) << 6); + write16p(TBARB_TEMP + 0x12, ((msr.lo >> 16) & 0xff) << 6); /* Northbridge temperature slope and offset */ - write16p(0x40000016, 0x808c); + write16p(TBARB_TEMP + 0x16, 0x808c); - write16p(0x40000014, 0xde87); + write16p(TBARB_TEMP + 0x14, 0xde87); /* Enable thermal data reporting, processor, PCH and northbridge */ - write16p(0x4000001a, (read16p(0x4000001a) & ~0xf) | 0x10f0); + write16p(TBARB_TEMP + 0x1a, (read16p(TBARB_TEMP + 0x1a) & ~0xf) | 0x10f0); /* Disable temporary BAR */ pci_write_config32(dev, 0x40, pci_read_config32(dev, 0x40) & ~1); -- To view, visit https://review.coreboot.org/c/coreboot/+/41111 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icda6e4100d954fe28d2624270b5d7ab7ed155e32 Gerrit-Change-Number: 41111 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: sb/intel/bd82x6x: Do cosmetic fixes
by Angel Pons (Code Review) 08 May '20

08 May '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41110 ) Change subject: sb/intel/bd82x6x: Do cosmetic fixes ...................................................................... sb/intel/bd82x6x: Do cosmetic fixes Make the code follow the coding style, and reflow things that fit in 96 characters. Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change. Change-Id: I6e0acdc9c21d4b416597dc776bd9abab12bff4a0 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/bd82x6x/early_rcba.c M src/southbridge/intel/bd82x6x/early_thermal.c 3 files changed, 22 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/41110/1 diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 530f11a..bd507c4 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -19,15 +19,13 @@ #define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0) -static void -wait_iobp(void) +static void wait_iobp(void) { while (RCBA8(IOBPS) & 1) ; // implement timeout? } -static u32 -read_iobp(u32 address) +static u32 read_iobp(u32 address) { u32 ret; @@ -40,8 +38,7 @@ return ret; } -static void -write_iobp(u32 address, u32 val) +static void write_iobp(u32 address, u32 val) { /* this function was probably pch_iobp_update with the andvalue * being 0. So either the IOBP read can be removed or this function @@ -137,11 +134,9 @@ ; } -void -early_pch_init_native (void) +void early_pch_init_native(void) { - pci_write_config8 (SOUTHBRIDGE, 0xa6, - pci_read_config8 (SOUTHBRIDGE, 0xa6) | 2); + pci_write_config8(SOUTHBRIDGE, 0xa6, pci_read_config8(SOUTHBRIDGE, 0xa6) | 2); RCBA32(CIR1) = 0x00109000; RCBA32(REC); // !!! = 0x00000000 @@ -278,9 +273,8 @@ * - 0x3f8-0x3ff COMA */ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); - pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN - | MC_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN - | COMB_LPC_EN | COMA_LPC_EN); + pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN + | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN | COMA_LPC_EN); const struct device *dev = pcidev_on_root(0x1f, 0); const struct southbridge_intel_bd82x6x_config *config = NULL; diff --git a/src/southbridge/intel/bd82x6x/early_rcba.c b/src/southbridge/intel/bd82x6x/early_rcba.c index 915a935..61877bb 100644 --- a/src/southbridge/intel/bd82x6x/early_rcba.c +++ b/src/southbridge/intel/bd82x6x/early_rcba.c @@ -5,8 +5,7 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include "pch.h" -void -southbridge_configure_default_intmap(void) +void southbridge_configure_default_intmap(void) { /* * For the PCH internal PCI functions, provide a reasonable @@ -83,8 +82,7 @@ (void) RCBA16(OIC); } -void -southbridge_rcba_config(void) +void southbridge_rcba_config(void) { RCBA32(FD) = PCH_DISABLE_ALWAYS; } diff --git a/src/southbridge/intel/bd82x6x/early_thermal.c b/src/southbridge/intel/bd82x6x/early_thermal.c index ac7a3a4..e73f3a5 100644 --- a/src/southbridge/intel/bd82x6x/early_thermal.c +++ b/src/southbridge/intel/bd82x6x/early_thermal.c @@ -36,34 +36,31 @@ pci_write_config32(dev, 0x44, 0x0); /* Activate temporary BAR. */ - pci_write_config32(dev, 0x40, - pci_read_config32(dev, 0x40) | 5); + pci_write_config32(dev, 0x40, pci_read_config32(dev, 0x40) | 5); - write16p (0x40000004, 0x3a2b); - write8p (0x4000000c, 0xff); - write8p (0x4000000d, 0x00); - write8p (0x4000000e, 0x40); - write8p (0x40000082, 0x00); - write8p (0x40000001, 0xba); + write16p(0x40000004, 0x3a2b); + write8p(0x4000000c, 0xff); + write8p(0x4000000d, 0x00); + write8p(0x4000000e, 0x40); + write8p(0x40000082, 0x00); + write8p(0x40000001, 0xba); /* Perform init. */ /* Configure TJmax. */ msr = rdmsr(MSR_TEMPERATURE_TARGET); write16p(0x40000012, ((msr.lo >> 16) & 0xff) << 6); - /* Northbridge temperature slope and offset. */ + /* Northbridge temperature slope and offset */ write16p(0x40000016, 0x808c); - write16p (0x40000014, 0xde87); + write16p(0x40000014, 0xde87); - /* Enable thermal data reporting, processor, PCH and northbridge. */ + /* Enable thermal data reporting, processor, PCH and northbridge */ write16p(0x4000001a, (read16p(0x4000001a) & ~0xf) | 0x10f0); - /* Disable temporary BAR. */ - pci_write_config32(dev, 0x40, - pci_read_config32(dev, 0x40) & ~1); + /* Disable temporary BAR */ + pci_write_config32(dev, 0x40, pci_read_config32(dev, 0x40) & ~1); pci_write_config32(dev, 0x40, 0); - write32 (DEFAULT_RCBA + 0x38b0, - (read32 (DEFAULT_RCBA + 0x38b0) & 0xffff8003) | 0x403c); + write32(DEFAULT_RCBA + 0x38b0, (read32(DEFAULT_RCBA + 0x38b0) & 0xffff8003) | 0x403c); } -- To view, visit https://review.coreboot.org/c/coreboot/+/41110 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e0acdc9c21d4b416597dc776bd9abab12bff4a0 Gerrit-Change-Number: 41110 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/haswell/northbridge.c: Fix typo
by Angel Pons (Code Review) 08 May '20

08 May '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41109 ) Change subject: nb/intel/haswell/northbridge.c: Fix typo ...................................................................... nb/intel/haswell/northbridge.c: Fix typo `TESGMB` => `TSEGMB` Change-Id: Id48bed068f9d2be7201e7fa120b00608f6fe2f98 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/northbridge.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/41109/1 diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 552f032..099e7f0 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -255,7 +255,7 @@ [TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"), [BDSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"), [BGSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"), - [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"), + [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TSEGMB"), }; static void mc_read_map_entries(struct device *dev, uint64_t *values) -- To view, visit https://review.coreboot.org/c/coreboot/+/41109 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id48bed068f9d2be7201e7fa120b00608f6fe2f98 Gerrit-Change-Number: 41109 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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