Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41111 )
Change subject: sb/intel/bd82x6x: Put temp BAR in a define ......................................................................
sb/intel/bd82x6x: Put temp BAR in a define
We use a temporary BAR value to program the thermal settings. To make this more obvious, factor it out.
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change.
Change-Id: Icda6e4100d954fe28d2624270b5d7ab7ed155e32 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/bd82x6x/early_thermal.c 1 file changed, 14 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/41111/1
diff --git a/src/southbridge/intel/bd82x6x/early_thermal.c b/src/southbridge/intel/bd82x6x/early_thermal.c index e73f3a5..6519a24 100644 --- a/src/southbridge/intel/bd82x6x/early_thermal.c +++ b/src/southbridge/intel/bd82x6x/early_thermal.c @@ -22,6 +22,9 @@ return read16((u16 *)addr); }
+/* Temporary thermal BAR value */ +#define TBARB_TEMP 0x40000000 + /* Early thermal init, must be done prior to giving ME its memory which is done at the end of raminit. */ void early_thermal_init(void) @@ -32,31 +35,31 @@ dev = PCI_DEV(0x0, 0x1f, 0x6);
/* Program address for temporary BAR. */ - pci_write_config32(dev, 0x40, 0x40000000); + pci_write_config32(dev, 0x40, TBARB_TEMP); pci_write_config32(dev, 0x44, 0x0);
/* Activate temporary BAR. */ pci_write_config32(dev, 0x40, pci_read_config32(dev, 0x40) | 5);
+ write16p(TBARB_TEMP + 0x04, 0x3a2b);
- write16p(0x40000004, 0x3a2b); - write8p(0x4000000c, 0xff); - write8p(0x4000000d, 0x00); - write8p(0x4000000e, 0x40); - write8p(0x40000082, 0x00); - write8p(0x40000001, 0xba); + write8p(TBARB_TEMP + 0x0c, 0xff); + write8p(TBARB_TEMP + 0x0d, 0x00); + write8p(TBARB_TEMP + 0x0e, 0x40); + write8p(TBARB_TEMP + 0x82, 0x00); + write8p(TBARB_TEMP + 0x01, 0xba);
/* Perform init. */ /* Configure TJmax. */ msr = rdmsr(MSR_TEMPERATURE_TARGET); - write16p(0x40000012, ((msr.lo >> 16) & 0xff) << 6); + write16p(TBARB_TEMP + 0x12, ((msr.lo >> 16) & 0xff) << 6); /* Northbridge temperature slope and offset */ - write16p(0x40000016, 0x808c); + write16p(TBARB_TEMP + 0x16, 0x808c);
- write16p(0x40000014, 0xde87); + write16p(TBARB_TEMP + 0x14, 0xde87);
/* Enable thermal data reporting, processor, PCH and northbridge */ - write16p(0x4000001a, (read16p(0x4000001a) & ~0xf) | 0x10f0); + write16p(TBARB_TEMP + 0x1a, (read16p(TBARB_TEMP + 0x1a) & ~0xf) | 0x10f0);
/* Disable temporary BAR */ pci_write_config32(dev, 0x40, pci_read_config32(dev, 0x40) & ~1);
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41111 )
Change subject: sb/intel/bd82x6x: Put temp BAR in a define ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41111/1/src/southbridge/intel/bd82x... File src/southbridge/intel/bd82x6x/early_thermal.c:
https://review.coreboot.org/c/coreboot/+/41111/1/src/southbridge/intel/bd82x... PS1, Line 25: value "address"?
Hello build bot (Jenkins), Arthur Heymans, Patrick Rudolph, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41111
to look at the new patch set (#2).
Change subject: sb/intel/bd82x6x: Put temp BAR in a define ......................................................................
sb/intel/bd82x6x: Put temp BAR in a define
We use a temporary BAR value to program the thermal settings. To make this more obvious, factor it out.
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change.
Change-Id: Icda6e4100d954fe28d2624270b5d7ab7ed155e32 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/bd82x6x/early_thermal.c 1 file changed, 14 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/41111/2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41111 )
Change subject: sb/intel/bd82x6x: Put temp BAR in a define ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41111/1/src/southbridge/intel/bd82x... File src/southbridge/intel/bd82x6x/early_thermal.c:
https://review.coreboot.org/c/coreboot/+/41111/1/src/southbridge/intel/bd82x... PS1, Line 25: value
"address"?
I wanted to avoid "Base Address Range address". I reworded the thing a bit
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41111 )
Change subject: sb/intel/bd82x6x: Put temp BAR in a define ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41111 )
Change subject: sb/intel/bd82x6x: Put temp BAR in a define ......................................................................
sb/intel/bd82x6x: Put temp BAR in a define
We use a temporary BAR value to program the thermal settings. To make this more obvious, factor it out.
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change.
Change-Id: Icda6e4100d954fe28d2624270b5d7ab7ed155e32 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/41111 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Georgi pgeorgi@google.com --- M src/southbridge/intel/bd82x6x/early_thermal.c 1 file changed, 14 insertions(+), 11 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved
diff --git a/src/southbridge/intel/bd82x6x/early_thermal.c b/src/southbridge/intel/bd82x6x/early_thermal.c index e73f3a5..60c08d1 100644 --- a/src/southbridge/intel/bd82x6x/early_thermal.c +++ b/src/southbridge/intel/bd82x6x/early_thermal.c @@ -22,6 +22,9 @@ return read16((u16 *)addr); }
+/* Temporary address for the thermal BAR */ +#define TBARB_TEMP 0x40000000 + /* Early thermal init, must be done prior to giving ME its memory which is done at the end of raminit. */ void early_thermal_init(void) @@ -32,31 +35,31 @@ dev = PCI_DEV(0x0, 0x1f, 0x6);
/* Program address for temporary BAR. */ - pci_write_config32(dev, 0x40, 0x40000000); + pci_write_config32(dev, 0x40, TBARB_TEMP); pci_write_config32(dev, 0x44, 0x0);
/* Activate temporary BAR. */ pci_write_config32(dev, 0x40, pci_read_config32(dev, 0x40) | 5);
+ write16p(TBARB_TEMP + 0x04, 0x3a2b);
- write16p(0x40000004, 0x3a2b); - write8p(0x4000000c, 0xff); - write8p(0x4000000d, 0x00); - write8p(0x4000000e, 0x40); - write8p(0x40000082, 0x00); - write8p(0x40000001, 0xba); + write8p(TBARB_TEMP + 0x0c, 0xff); + write8p(TBARB_TEMP + 0x0d, 0x00); + write8p(TBARB_TEMP + 0x0e, 0x40); + write8p(TBARB_TEMP + 0x82, 0x00); + write8p(TBARB_TEMP + 0x01, 0xba);
/* Perform init. */ /* Configure TJmax. */ msr = rdmsr(MSR_TEMPERATURE_TARGET); - write16p(0x40000012, ((msr.lo >> 16) & 0xff) << 6); + write16p(TBARB_TEMP + 0x12, ((msr.lo >> 16) & 0xff) << 6); /* Northbridge temperature slope and offset */ - write16p(0x40000016, 0x808c); + write16p(TBARB_TEMP + 0x16, 0x808c);
- write16p(0x40000014, 0xde87); + write16p(TBARB_TEMP + 0x14, 0xde87);
/* Enable thermal data reporting, processor, PCH and northbridge */ - write16p(0x4000001a, (read16p(0x4000001a) & ~0xf) | 0x10f0); + write16p(TBARB_TEMP + 0x1a, (read16p(TBARB_TEMP + 0x1a) & ~0xf) | 0x10f0);
/* Disable temporary BAR */ pci_write_config32(dev, 0x40, pci_read_config32(dev, 0x40) & ~1);
-
Angel Pons (Code Review) -
Patrick Georgi (Code Review)