coreboot-gerrit May 2020

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Change in coreboot[master]: treewide: more SPDX header work
by Patrick Georgi (Code Review) 09 May '20

09 May '20

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41174 ) Change subject: treewide: more SPDX header work ...................................................................... treewide: more SPDX header work Change-Id: Ib78c322730ec6dfa9dcaafa16e5741cd3d351b8d Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M Documentation/mainboard_io_trap_handler_sample.c M Makefile.inc M gnat.adc M toolchain.inc 4 files changed, 7 insertions(+), 54 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/41174/1 diff --git a/Documentation/mainboard_io_trap_handler_sample.c b/Documentation/mainboard_io_trap_handler_sample.c index f440f8d..f785568 100644 --- a/Documentation/mainboard_io_trap_handler_sample.c +++ b/Documentation/mainboard_io_trap_handler_sample.c @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* This file is part of the coreboot project. */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/io.h> #include <console/console.h> diff --git a/Makefile.inc b/Makefile.inc index e315732..ef247da 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -1,17 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2011 secunet Security Networks AG -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-only ifneq ($(NOCOMPILE),1) GIT:=$(shell git -C "$(top)" rev-parse --git-dir 1>/dev/null 2>&1 \ diff --git a/gnat.adc b/gnat.adc index 88cf438..c4a9f72 100644 --- a/gnat.adc +++ b/gnat.adc @@ -1,15 +1,5 @@ --- -- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; version 2 of the License. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- +-- SPDX-License-Identifier: GPL-2.0-only pragma Restrictions (No_Access_Subprograms); pragma Restrictions (No_Allocators); diff --git a/toolchain.inc b/toolchain.inc index 865227b..2a4a91d 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -1,17 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2014 Google Inc -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-only # ccache integration ifeq ($(CONFIG_CCACHE),y) -- To view, visit https://review.coreboot.org/c/coreboot/+/41174 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib78c322730ec6dfa9dcaafa16e5741cd3d351b8d Gerrit-Change-Number: 41174 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skylake: Configure L1 substates for PCH root ports
by Benjamin Doron (Code Review) 09 May '20

09 May '20

Hello build bot (Jenkins), Nico Huber, Matt DeVillier, Paul Menzel, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39538 to look at the new patch set (#20). Change subject: soc/intel/skylake: Configure L1 substates for PCH root ports ...................................................................... soc/intel/skylake: Configure L1 substates for PCH root ports Exposes PcieRpL1Substates to devicetree to allow boards to override this configuration. Change-Id: I36150858485715016158595c832c142b0582ddb8 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h 2 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/39538/20 -- To view, visit https://review.coreboot.org/c/coreboot/+/39538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36150858485715016158595c832c142b0582ddb8 Gerrit-Change-Number: 39538 Gerrit-PatchSet: 20 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/skylake: Configure L1 substates for PCH root ports
by Benjamin Doron (Code Review) 09 May '20

09 May '20

Hello build bot (Jenkins), Nico Huber, Matt DeVillier, Paul Menzel, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39538 to look at the new patch set (#19). Change subject: soc/intel/skylake: Configure L1 substates for PCH root ports ...................................................................... soc/intel/skylake: Configure L1 substates for PCH root ports Exposes PcieRpL1Substates to devicetree to allow boards to override this configuration. Change-Id: I36150858485715016158595c832c142b0582ddb8 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h 2 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/39538/19 -- To view, visit https://review.coreboot.org/c/coreboot/+/39538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36150858485715016158595c832c142b0582ddb8 Gerrit-Change-Number: 39538 Gerrit-PatchSet: 19 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports
by Benjamin Doron (Code Review) 09 May '20

09 May '20

Hello build bot (Jenkins), Nico Huber, Matt DeVillier, Paul Menzel, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39538 to look at the new patch set (#17). Change subject: soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports ...................................................................... soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports Port commit 84b4882b (soc/intel/tigerlake: Configure L1Substates for PCH Root ports), CB:39412) to Skylake. Exposes PcieRpAspm and PcieRpL1Substates to devicetree to allow boards to set these options. get_{aspm,l1_substate}_control() ensure that the right UPD value is set in fsp_params. Change-Id: I36150858485715016158595c832c142b0582ddb8 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h 2 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/39538/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/39538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36150858485715016158595c832c142b0582ddb8 Gerrit-Change-Number: 39538 Gerrit-PatchSet: 17 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports
by Matt DeVillier (Code Review) 09 May '20

09 May '20

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39538 ) Change subject: soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports ...................................................................... Patch Set 16: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/39538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36150858485715016158595c832c142b0582ddb8 Gerrit-Change-Number: 39538 Gerrit-PatchSet: 16 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 09 May 2020 17:12:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86: handle bootblock.c by default in Make
by Arthur Heymans (Code Review) 09 May '20

09 May '20

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41105 ) Change subject: arch/x86: handle bootblock.c by default in Make ...................................................................... Patch Set 7: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/41105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62648bed633b5d9646bc3b943019191b4918f1dc Gerrit-Change-Number: 41105 Gerrit-PatchSet: 7 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 09 May 2020 13:41:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard(s): drop redundant entries from Makefiles
by Benjamin Doron (Code Review) 09 May '20

09 May '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41107 ) Change subject: mainboard(s): drop redundant entries from Makefiles ...................................................................... Patch Set 8: Why is hda_verb being removed? -- To view, visit https://review.coreboot.org/c/coreboot/+/41107 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1961646c5ed4ae6a1308ce0e8e15792970da4e0d Gerrit-Change-Number: 41107 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Comment-Date: Sat, 09 May 2020 06:20:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports
by Benjamin Doron (Code Review) 09 May '20

09 May '20

Hello build bot (Jenkins), Nico Huber, Matt DeVillier, Paul Menzel, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39538 to look at the new patch set (#15). Change subject: soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports ...................................................................... soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports Port commit 84b4882b (soc/intel/tigerlake: Configure L1Substates for PCH Root ports), CB:39412) to Skylake. Exposes PcieRpAspm and PcieRpL1Substates to devicetree to allow boards to set these options. get_{aspm,l1_substate}_control() ensure that the right UPD value is set in fsp_params. Change-Id: I36150858485715016158595c832c142b0582ddb8 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h 2 files changed, 56 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/39538/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/39538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36150858485715016158595c832c142b0582ddb8 Gerrit-Change-Number: 39538 Gerrit-PatchSet: 15 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [WIP] mainboard: Add Acer ES1-572
by Benjamin Doron (Code Review) 09 May '20

09 May '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38978 ) Change subject: [WIP] mainboard: Add Acer ES1-572 ...................................................................... Patch Set 5: (2 comments) https://review.coreboot.org/c/coreboot/+/38978/5/src/mainboard/acer/es1-572… File src/mainboard/acer/es1-572/Makefile.inc: https://review.coreboot.org/c/coreboot/+/38978/5/src/mainboard/acer/es1-572… PS5, Line 16: ramstage-y += ramstage.c > rename ramstage.c to mainboard.c, which is handled in src/arch/x86/Makefile. […] The filename would then be less descriptive. Also, see CB:41106. https://review.coreboot.org/c/coreboot/+/38978/5/src/mainboard/acer/es1-572… PS5, Line 17: ramstage-y += hda_verb.c > handled in src/device/Makefile. […] Only when CONFIG_AZALIA_PLUGIN_SUPPORT=y. According to CB:40746, that shouldn't be an assumed default. -- To view, visit https://review.coreboot.org/c/coreboot/+/38978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id98788a2c5e54f70fd1cacbd70d636f5e63b2619 Gerrit-Change-Number: 38978 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Comment-Date: Sat, 09 May 2020 05:34:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner Gerrit-MessageType: comment

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Change in coreboot[master]: vboot: Clean up pre-RAM use of vboot_recovery_mode_enabled()
by Julius Werner (Code Review) 09 May '20

09 May '20

Hello Furquan Shaikh, Patrick Rudolph, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39221 to review the following change. Change subject: vboot: Clean up pre-RAM use of vboot_recovery_mode_enabled() ...................................................................... vboot: Clean up pre-RAM use of vboot_recovery_mode_enabled() vboot_recovery_mode_enabled() was recently changed to assert() when it is called before vboot logic has run, because we cannot determine whether we're going to be in recovery mode at that point and we wanted to flush out existing uses that pretended that we could. Turns out there are a bunch of uses like that, and there is some code that is shared across configuratiions that can and those that can't. This patch cleans them up to either remove checks that cannot return true, or add explicit Kconfig guards to clarify that the code is shared. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I31bfc7663724fdacab9955224dcaf650d1ec1c3c --- M src/drivers/intel/fsp1_1/Kconfig M src/drivers/intel/fsp1_1/raminit.c M src/drivers/mrc_cache/mrc_cache.c M src/northbridge/intel/haswell/raminit.c M src/northbridge/intel/sandybridge/raminit_mrc.c M src/soc/intel/baytrail/romstage/raminit.c M src/soc/intel/broadwell/romstage/raminit.c M src/southbridge/intel/bd82x6x/me_8.x.c 8 files changed, 13 insertions(+), 57 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/39221/1 diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index 7c69888..304cbae 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -13,6 +13,7 @@ config PLATFORM_USES_FSP1_1 bool + depends on !VBOOT_STARTS_IN_BOOTBLOCK select UEFI_2_4_BINDING select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select MICROCODE_UPDATE_PRE_RAM diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index 208ebb5..9e9ef70 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -22,7 +22,6 @@ #include <lib.h> /* hexdump */ #include <string.h> #include <timestamp.h> -#include <security/vboot/vboot_common.h> void raminit(struct romstage_params *params) { @@ -256,11 +255,10 @@ /* Locate the memory configuration data to speed up the next reboot */ mrc_hob = get_next_guid_hob(&mrc_guid, hob_list_ptr); - if (mrc_hob == NULL) + if (mrc_hob == NULL) { printk(BIOS_DEBUG, "Memory Configuration Data Hob not present\n"); - else if (!vboot_recovery_mode_enabled()) { - /* Do not save MRC data in recovery path */ + } else { params->data_to_save = GET_GUID_HOB_DATA(mrc_hob); params->data_to_save_size = ALIGN_UP( ((u32)GET_HOB_LENGTH(mrc_hob)), 16); diff --git a/src/drivers/mrc_cache/mrc_cache.c b/src/drivers/mrc_cache/mrc_cache.c index d4a4aab..860ba20 100644 --- a/src/drivers/mrc_cache/mrc_cache.c +++ b/src/drivers/mrc_cache/mrc_cache.c @@ -105,7 +105,7 @@ int i; int flags; - if (vboot_recovery_mode_enabled()) + if (CONFIG(VBOOT_STARTS_IN_BOOTBLOCK) && vboot_recovery_mode_enabled()) flags = RECOVERY_FLAG; else flags = NORMAL_FLAG; @@ -519,6 +519,8 @@ const uint32_t invalid = ~MRC_DATA_SIGNATURE; /* Invalidate only on recovery mode with retraining enabled. */ + if (!CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) + return; if (!vboot_recovery_mode_enabled()) return; if (!vboot_recovery_mode_memory_retrain()) diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 8267833..ab47e5e 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -127,7 +127,8 @@ * Do not pass MRC data in for recovery mode boot, * Always pass it in for S3 resume. */ - if (!vboot_recovery_mode_enabled() || pei_data->boot_mode == 2) + if (!(CONFIG(HASWELL_VBOOT_IN_BOOTBLOCK) && vboot_recovery_mode_enabled()) + || pei_data->boot_mode == 2) prepare_mrc_cache(pei_data); /* If MRC data is not found we cannot continue S3 resume. */ diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 8daa9aa..ff1c580 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -207,7 +207,8 @@ * Do not pass MRC data in for recovery mode boot, * Always pass it in for S3 resume. */ - if (!vboot_recovery_mode_enabled() || pei_data->boot_mode == 2) + if (!(CONFIG(SANDYBRIDGE_VBOOT_IN_BOOTBLOCK) && vboot_recovery_mode_enabled()) || + pei_data->boot_mode == 2) prepare_mrc_cache(pei_data); /* If MRC data is not found we cannot continue S3 resume. */ diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index c21a0c4..deaab51 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -125,9 +125,7 @@ if (!mp->io_hole_mb) mp->io_hole_mb = 2048; - if (vboot_recovery_mode_enabled()) { - printk(BIOS_DEBUG, "Recovery mode: not using MRC cache.\n"); - } else if (!mrc_cache_get_current(MRC_TRAINING_DATA, 0, &rdev)) { + if (!mrc_cache_get_current(MRC_TRAINING_DATA, 0, &rdev)) { mp->saved_data_size = region_device_sz(&rdev); mp->saved_data = rdev_mmap_full(&rdev); /* Assume boot device is memory mapped. */ diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index 3759c1f..0683e1c 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -48,7 +48,8 @@ broadwell_fill_pei_data(pei_data); - if (vboot_recovery_mode_enabled()) { + if (CONFIG(BROADWELL_VBOOT_IN_BOOTBLOCK) && + vboot_recovery_mode_enabled()) { /* Recovery mode does not use MRC cache */ printk(BIOS_DEBUG, "Recovery mode: not using MRC cache.\n"); } else if (!mrc_cache_get_current(MRC_TRAINING_DATA, 0, &rdev)) { diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index f13ced9..c7c16b1 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -416,38 +416,6 @@ print_cap("Wireless LAN (WLAN)", cap->wlan); } -#if CONFIG(CHROMEOS) && 0 /* DISABLED */ -/* Tell ME to issue a global reset */ -static int mkhi_global_reset(void) -{ - struct me_global_reset reset = { - .request_origin = GLOBAL_RESET_BIOS_POST, - .reset_type = CBM_RR_GLOBAL_RESET, - }; - struct mkhi_header mkhi = { - .group_id = MKHI_GROUP_ID_CBM, - .command = MKHI_GLOBAL_RESET, - }; - struct mei_header mei = { - .is_complete = 1, - .length = sizeof(mkhi) + sizeof(reset), - .host_address = MEI_HOST_ADDRESS, - .client_address = MEI_ADDRESS_MKHI, - }; - - /* Send request and wait for response */ - printk(BIOS_NOTICE, "ME: %s\n", __FUNCTION__); - if (mei_sendrecv(&mei, &mkhi, &reset, NULL, 0) < 0) { - /* No response means reset will happen shortly... */ - halt(); - } - - /* If the ME responded it rejected the reset request */ - printk(BIOS_ERR, "ME: Global Reset failed\n"); - return -1; -} -#endif - /* Send END OF POST message to the ME */ static int __unused mkhi_end_of_post(void) { @@ -696,20 +664,6 @@ if (intel_me_read_mbp(&mbp_data)) break; -#if CONFIG(CHROMEOS) && 0 /* DISABLED */ - /* - * Unlock ME in recovery mode. - */ - if (vboot_recovery_mode_enabled()) { - /* Unlock ME flash region */ - mkhi_hmrfpo_enable(); - - /* Issue global reset */ - mkhi_global_reset(); - return; - } -#endif - if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) { me_print_fw_version(&mbp_data.fw_version_name); me_print_fwcaps(&mbp_data.fw_caps_sku); -- To view, visit https://review.coreboot.org/c/coreboot/+/39221 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31bfc7663724fdacab9955224dcaf650d1ec1c3c Gerrit-Change-Number: 39221 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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coreboot-gerrit May 2020