coreboot-gerrit May 2020

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Change in coreboot[master]: drivers/ocp/ipmi: Implement set POST start/end command
by Tim Chu (Code Review) 11 May '20

11 May '20

Tim Chu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41229 ) Change subject: drivers/ocp/ipmi: Implement set POST start/end command ...................................................................... drivers/ocp/ipmi: Implement set POST start/end command Implemented to send POST start and POST end command to BMC in ramstage. Tested=Read POST command in OpenBMC, if success message may show as below, root@bmc:~# cat /var/log/messages |grep -i "POST" Aug 10 00:11:24 bmc user.info ipmid: POST Start Event for Payload#1 Aug 10 00:11:28 bmc user.info ipmid: POST End Event for Payload#1 root@bmc:~# Signed-off-by: TimChu <Tim.Chu(a)quantatw.com> Change-Id: I25fe435eeeef06ca9378ca9a0b3654806a3222ad --- A src/drivers/ocp/ipmi/Kconfig A src/drivers/ocp/ipmi/Makefile.inc A src/drivers/ocp/ipmi/ipmi_ocp.c A src/drivers/ocp/ipmi/ipmi_ocp.h M src/mainboard/ocp/tiogapass/Kconfig M src/mainboard/ocp/tiogapass/devicetree.cb 6 files changed, 138 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/41229/1 diff --git a/src/drivers/ocp/ipmi/Kconfig b/src/drivers/ocp/ipmi/Kconfig new file mode 100644 index 0000000..74a886e --- /dev/null +++ b/src/drivers/ocp/ipmi/Kconfig @@ -0,0 +1,3 @@ +config IPMI_OCP + bool + default n \ No newline at end of file diff --git a/src/drivers/ocp/ipmi/Makefile.inc b/src/drivers/ocp/ipmi/Makefile.inc new file mode 100644 index 0000000..f8be839 --- /dev/null +++ b/src/drivers/ocp/ipmi/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_IPMI_OCP) += ipmi_ocp.c \ No newline at end of file diff --git a/src/drivers/ocp/ipmi/ipmi_ocp.c b/src/drivers/ocp/ipmi/ipmi_ocp.c new file mode 100644 index 0000000..08bca43 --- /dev/null +++ b/src/drivers/ocp/ipmi/ipmi_ocp.c @@ -0,0 +1,120 @@ +/* This file is part of the coreboot project. */ +/* + * Place in devicetree.cb: + * + * chip drivers/ocp/ipmi # OCP specific IPMI porting + device pnp ca2.1 on end + * end + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pnp.h> +#include "chip.h" +#include "drivers/ipmi/ipmi_kcs.h" +#include "ipmi_ocp.h" + +static int ipmi_set_post_start(struct device *dev, struct ipmi_rsp *rsp) +{ + int ret; + + ret = ipmi_kcs_message(dev->path.pnp.port, IPMI_NETFN_OEM, 0, + IPMI_BMC_SET_POST_START, NULL, 0, (u8 *)rsp, + sizeof(*rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp->completion_code) { + printk(BIOS_ERR, "IPMI: %s command failed (ret=%d rsp=0x%x)\n", + __func__, ret, rsp->completion_code); + return 1; + } + if (ret != sizeof(*rsp)) { + printk(BIOS_ERR, "IPMI: %s response truncated\n", __func__); + return 1; + } + return 0; +} + +static int ipmi_set_post_end(struct device *dev, struct ipmi_rsp *rsp) +{ + int ret; + + ret = ipmi_kcs_message(dev->path.pnp.port, IPMI_NETFN_OEM, 0, + IPMI_BMC_SET_POST_END, NULL, 0, (u8 *)rsp, + sizeof(*rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp->completion_code) { + printk(BIOS_ERR, "IPMI: %s command failed (ret=%d rsp=0x%x)\n", + __func__, ret, rsp->completion_code); + return 1; + } + if (ret != sizeof(*rsp)) { + printk(BIOS_ERR, "IPMI: %s response truncated\n", __func__); + return 1; + } + return 0; +} + +static void ipmi_ocp_init(struct device *dev) +{ + struct ipmi_rsp postrsp; + + /* Send POST start to BMC. */ + if(!ipmi_set_post_start(dev, &postrsp)){ + printk(BIOS_DEBUG, "IPMI BMC POST is started\n"); + } +} + +static void ipmi_ocp_final(struct device *dev) +{ + struct ipmi_rsp postrsp; + + /* Send POST end to BMC. */ + if(!ipmi_set_post_end(dev, &postrsp)){ + printk(BIOS_DEBUG, "IPMI BMC POST is ended\n"); + } +} + +static void ipmi_set_resources(struct device *dev) +{ + struct resource *res; + + for (res = dev->resource_list; res; res = res->next) { + if (!(res->flags & IORESOURCE_ASSIGNED)) + continue; + + res->flags |= IORESOURCE_STORED; + report_resource_stored(dev, res, ""); + } +} + +static void ipmi_read_resources(struct device *dev) +{ + struct resource *res = new_resource(dev, 0); + res->base = dev->path.pnp.port; + res->size = 2; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static struct device_operations ops = { + .read_resources = ipmi_read_resources, + .set_resources = ipmi_set_resources, + .init = ipmi_ocp_init, + .final = ipmi_ocp_final, +}; + +static void enable_dev(struct device *dev) +{ + if (dev->path.type != DEVICE_PATH_PNP) + printk(BIOS_ERR, "%s: Unsupported device type\n", + dev_path(dev)); + else if (dev->path.pnp.port & 1) + printk(BIOS_ERR, "%s: Base address needs to be aligned to 2\n", + dev_path(dev)); + else + dev->ops = &ops; +} + +struct chip_operations drivers_ocp_ipmi_ops = { + CHIP_NAME("IPMI OCP") + .enable_dev = enable_dev, +}; \ No newline at end of file diff --git a/src/drivers/ocp/ipmi/ipmi_ocp.h b/src/drivers/ocp/ipmi/ipmi_ocp.h new file mode 100644 index 0000000..6747e0a --- /dev/null +++ b/src/drivers/ocp/ipmi/ipmi_ocp.h @@ -0,0 +1,10 @@ +/* This file is part of the coreboot project. */ + +#ifndef __IPMI_OCP_H +#define __IPMI_OCP_H + +#define IPMI_NETFN_OEM 0x30 +#define IPMI_BMC_SET_POST_START 0x73 +#define IPMI_BMC_SET_POST_END 0x74 + +#endif \ No newline at end of file diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig index f9b5e7f..73eeca1 100644 --- a/src/mainboard/ocp/tiogapass/Kconfig +++ b/src/mainboard/ocp/tiogapass/Kconfig @@ -21,6 +21,7 @@ select HAVE_ACPI_TABLES select MAINBOARD_USES_FSP2_0 select IPMI_KCS + select IPMI_OCP select SOC_INTEL_SKYLAKE_SP select SUPERIO_ASPEED_AST2400 diff --git a/src/mainboard/ocp/tiogapass/devicetree.cb b/src/mainboard/ocp/tiogapass/devicetree.cb index 51e6a62..8b0caab 100644 --- a/src/mainboard/ocp/tiogapass/devicetree.cb +++ b/src/mainboard/ocp/tiogapass/devicetree.cb @@ -89,6 +89,9 @@ register "bmc_i2c_address" = "0x20" register "bmc_boot_timeout" = "60" end + chip drivers/ocp/ipmi # OCP specific IPMI porting + device pnp ca2.1 on end + end end # Intel Corporation C621 Series Chipset LPC/eSPI Controller device pci 1f.2 on end # Intel Corporation C620 Series Chipset Family Power Management Controller device pci 1f.4 on end # Intel Corporation C620 Series Chipset Family SMBus -- To view, visit https://review.coreboot.org/c/coreboot/+/41229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25fe435eeeef06ca9378ca9a0b3654806a3222ad Gerrit-Change-Number: 41229 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/kukui: add dsi flag MIPI_DSI_MODE_EOT_PACKET for anx7625
by Paul Ma (Code Review) 11 May '20

11 May '20

Paul Ma has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41161 ) Change subject: mb/google/kukui: add dsi flag MIPI_DSI_MODE_EOT_PACKET for anx7625 ...................................................................... mb/google/kukui: add dsi flag MIPI_DSI_MODE_EOT_PACKET for anx7625 MIPI_DSI_MODE_EOT_PACKET is required for anx7625 to work correctly. BUG=b:144824303 TEST=boot damu board, edp panel with anx7625 as bridge boot up normally. Signed-off-by: Paul Ma <magf(a)bitland.corp-partner.google.com> Change-Id: Iad651202bde2a40024af8c12153143ada2ce2439 --- M src/mainboard/google/kukui/mainboard.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/41161/1 diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index bb36d90..efcd49e 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -154,6 +154,8 @@ u32 mipi_dsi_flags = (MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | MIPI_DSI_MODE_LPM); + if (CONFIG(DRIVER_ANALOGIX_ANX7625)) + mipi_dsi_flags |= MIPI_DSI_MODE_EOT_PACKET; if (mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4, edid, panel->s->init) < 0) { printk(BIOS_ERR, "%s: Failed in DSI init.\n", __func__); -- To view, visit https://review.coreboot.org/c/coreboot/+/41161 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad651202bde2a40024af8c12153143ada2ce2439 Gerrit-Change-Number: 41161 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Ma <magf(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/kukui: Fix backlight flash white before show logo
by jitao shi (Code Review) 11 May '20

11 May '20

jitao shi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41146 ) Change subject: mb/google/kukui: Fix backlight flash white before show logo ...................................................................... mb/google/kukui: Fix backlight flash white before show logo Move the panel power on after backlight off. BUG=b:155107047 TEST=make # board = kukui Signed-off-by: Jitao Shi <jitao.shi(a)mediatek.com> Change-Id: I0f31923bd7c1dfa26d4b1bbd0a230ae400b08ca3 --- M src/mainboard/google/kukui/mainboard.c 1 file changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/41146/1 diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index bb36d90..d5a1bf4 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -139,13 +139,16 @@ static bool configure_display(void) { - struct panel_description *panel = get_active_panel(); - if (!panel) - return false; + struct panel_description *panel; mtcmos_display_power_on(); mtcmos_protect_display_bus(); configure_panel_backlight(); + + panel = get_active_panel(); + if (!panel) + return false; + power_on_panel(panel); struct edid *edid = &panel->s->edid; -- To view, visit https://review.coreboot.org/c/coreboot/+/41146 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f31923bd7c1dfa26d4b1bbd0a230ae400b08ca3 Gerrit-Change-Number: 41146 Gerrit-PatchSet: 1 Gerrit-Owner: jitao shi <jitao.shi(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: MAINTAINERS: update for mb/ocp/tiogapass
by Jonathan Zhang (Code Review) 11 May '20

11 May '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40966 ) Change subject: MAINTAINERS: update for mb/ocp/tiogapass ...................................................................... MAINTAINERS: update for mb/ocp/tiogapass Change-Id: Ia48f20ca8c21d3c645c5566c189dddf2f8bc0308 --- M MAINTAINERS 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/40966/1 diff --git a/MAINTAINERS b/MAINTAINERS index bc1e1fc..3531292 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -362,6 +362,16 @@ S: Maintained F: src/mainboard/facebook/monolith/ +OCP TIOGAPASS MAINBOARD +M: Jonathan Zhang <jonzhang(a)fb.com> +M: Reddy Chagam <anjaneya.chagam(a)intel.com> +M: Johnny Lin <Johnny_Lin(a)wiwynn.com> +M: Morgan Jang <Morgan_Jang(a)wiwynn.com> +M: Ryback Hung <<Ryback.Hung(a)quantatw.com> +M: Bryant Ou <Bryant.Ou(a)quantatw.com> +S: Maintained +F: src/mainboard/ocp/tiogapass + PORTWELL PQ-M107 MAINBOARD M: Frans Hendriks <fhendriks(a)eltan.com> M: Wim Vervoorn <wvervoorn(a)eltan.com> -- To view, visit https://review.coreboot.org/c/coreboot/+/40966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia48f20ca8c21d3c645c5566c189dddf2f8bc0308 Gerrit-Change-Number: 40966 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp: make CPX ramstage.h common for CPX, SKX
by Patrick Georgi (Code Review) 11 May '20

11 May '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41116 ) Change subject: soc/intel/xeon_sp: make CPX ramstage.h common for CPX, SKX ...................................................................... soc/intel/xeon_sp: make CPX ramstage.h common for CPX, SKX CB:41106 revealed that mb/intel/cedarisland already sets FSP-S UPD (see CB:40735) while the required includes are still missing in CPX. Buildbot did not fail because `ramstage.c` never was (implicitly) included. Fix this problem by making SKX/CPX share a common ramstage header for now by moving the one from SKX. Test: Build cedarisland_crb Change-Id: I9cd25edd167ec71ee98c7ffa4fa6f95ca73a75e9 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41116 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- D src/soc/intel/xeon_sp/cpx/include/soc/ramstage.h R src/soc/intel/xeon_sp/include/soc/ramstage.h 2 files changed, 0 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Maxim Polyakov: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/ramstage.h b/src/soc/intel/xeon_sp/cpx/include/soc/ramstage.h deleted file mode 100644 index 28e8d1a..0000000 --- a/src/soc/intel/xeon_sp/cpx/include/soc/ramstage.h +++ /dev/null @@ -1,6 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include <device/device.h> - -extern struct pci_operations soc_pci_ops; diff --git a/src/soc/intel/xeon_sp/skx/include/soc/ramstage.h b/src/soc/intel/xeon_sp/include/soc/ramstage.h similarity index 100% rename from src/soc/intel/xeon_sp/skx/include/soc/ramstage.h rename to src/soc/intel/xeon_sp/include/soc/ramstage.h -- To view, visit https://review.coreboot.org/c/coreboot/+/41116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cd25edd167ec71ee98c7ffa4fa6f95ca73a75e9 Gerrit-Change-Number: 41116 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/octopus: Fix default FMD
by Matt DeVillier (Code Review) 11 May '20

11 May '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41016 ) Change subject: mb/google/octopus: Fix default FMD ...................................................................... mb/google/octopus: Fix default FMD On Apollo Lake/Gemini Lake platforms, FSP requires more than a simple RW_MRC_CACHE; without the RECOVERY and VAR cache regions, FSP-m will fail on s3 resume and trigger a full reset instead. This fixes the default.fmd for octopus to match that used for reef. Test: build/boot google/ampton, verify sleep/resume works under Linux with 5.x kernel. Change-Id: I8565aa93256df7d6e0b359d70e9305f34e5ccb60 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M 3rdparty/libgfxinit M src/mainboard/google/octopus/default.fmd 2 files changed, 6 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/41016/1 diff --git a/3rdparty/libgfxinit b/3rdparty/libgfxinit index cdbfce2..12d71aa 160000 --- a/3rdparty/libgfxinit +++ b/3rdparty/libgfxinit @@ -1 +1 @@ -Subproject commit cdbfce275777f2fd142e3a3c73469807a4c40207 +Subproject commit 12d71aa3a542da31a26591ab6a09ed8602d3d34f diff --git a/src/mainboard/google/octopus/default.fmd b/src/mainboard/google/octopus/default.fmd index 6e6b64f..bf51a1c 100644 --- a/src/mainboard/google/octopus/default.fmd +++ b/src/mainboard/google/octopus/default.fmd @@ -4,7 +4,11 @@ IFWI@0x0 0x1ff000 # SMMSTORE requires 64k alignment SMMSTORE@0xa5e000 0x40000 - RW_MRC_CACHE 0x10000 + UNIFIED_MRC_CACHE 0x21000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + RW_VAR_MRC_CACHE 0x1000 + } FMAP 0x300 COREBOOT(CBFS) BIOS_UNUSABLE 0x4f000 -- To view, visit https://review.coreboot.org/c/coreboot/+/41016 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8565aa93256df7d6e0b359d70e9305f34e5ccb60 Gerrit-Change-Number: 41016 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/basecode: Implement CSE update flow
by Sridhar Siricilla (Code Review) 11 May '20

11 May '20

Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Sridhar Siricilla, Rizwan Qureshi, Subrata Banik, Balaji Manigandan, Aamir Bohra, Patrick Rudolph, V Sowmya, Andrey Petrov, Jamie Ryu, Martin Roth, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35403 to look at the new patch set (#82). Change subject: soc/intel/common/basecode: Implement CSE update flow ...................................................................... soc/intel/common/basecode: Implement CSE update flow The following changes have been done in this patch: Get the CSE partition info containing version of CSE RW using GET_BOOT_PARTITION_INFO HECI command Get the me_rw.version from the currently selected RW slot. If the version from the above 2 locations don't match start the update - If CSE's current boot partition is not RO, then * Set the CSE's next boot partition to RO using SET_BOOT_PARTITION HECI command. * Send global reset command to reset the system. - Enable HMRFPO (Host ME Region Flash Protection Override) operation mode using HMRFPO_ENABLE HECI command - Erase and Copy the CBFS CSE RW to CSE RW partition - Set the CSE's next boot partition to RW using SET_BOOT_PARTITION HECI command - Trigger global reset The system should boot with the Updated CSE RW partition. TEST=Verified basic update flows on hatch and helios. BUG=b:111330995 Change-Id: I12f6bba3324069d65edabaccd234006b0840e700 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- A Documentation/soc/intel/cse_fw_update/Layout_after.svg A Documentation/soc/intel/cse_fw_update/Layout_before.svg A Documentation/soc/intel/cse_fw_update/cse_fw_update.md M Documentation/soc/intel/index.md M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/custom_bp.c 6 files changed, 703 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/35403/82 -- To view, visit https://review.coreboot.org/c/coreboot/+/35403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12f6bba3324069d65edabaccd234006b0840e700 Gerrit-Change-Number: 35403 Gerrit-PatchSet: 82 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/jasperlake: Add function to display ME firmware status info...
by V Sowmya (Code Review) 11 May '20

11 May '20

V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40570 ) Change subject: soc/intel/jasperlake: Add function to display ME firmware status information ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/40570 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6b1c9410db8f06ac24fd997772b2ede04264bee Gerrit-Change-Number: 40570 Gerrit-PatchSet: 2 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Comment-Date: Mon, 11 May 2020 06:14:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Add function to display ME firmware status info...
by Rizwan Qureshi (Code Review) 11 May '20

11 May '20

Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40570 ) Change subject: soc/intel/jasperlake: Add function to display ME firmware status information ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/40570 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6b1c9410db8f06ac24fd997772b2ede04264bee Gerrit-Change-Number: 40570 Gerrit-PatchSet: 2 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Comment-Date: Mon, 11 May 2020 06:10:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: device/: Add basic dualgraphics support
by Patrick Rudolph (Code Review) 11 May '20

11 May '20

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41190 ) Change subject: device/: Add basic dualgraphics support ...................................................................... Patch Set 3: (3 comments) Thanks for working on this. Please state what you try to achieve. I made an attempt a while ago here: CB:12897 It's not that easy to fix. In general you want only one GPU to decode I/O, which is likely required for graphics init on legacy devices. Besides that all GPUs could decode memory as long as they only the primary decodes the A-seg. Running graphics init on every GPU is possible by switching the "primary" between those runs, but that's not supported by coreboot (yet). https://review.coreboot.org/c/coreboot/+/41190/3/src/device/device.c File src/device/device.c: https://review.coreboot.org/c/coreboot/+/41190/3/src/device/device.c@769 PS3, Line 769: PCI_COMMAND_IO only the primary gpu should decode IO https://review.coreboot.org/c/coreboot/+/41190/3/src/device/device.c@782 PS3, Line 782: (vga != vga_onboard) && vga_onboard && tab https://review.coreboot.org/c/coreboot/+/41190/3/src/device/device.c@791 PS3, Line 791: if (!CONFIG(ENABLE_ALL_GPUS)) { That's just wrong. -- To view, visit https://review.coreboot.org/c/coreboot/+/41190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28f896c2b7964728975d38dba4b3ebccf887e0b7 Gerrit-Change-Number: 41190 Gerrit-PatchSet: 3 Gerrit-Owner: UIS Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 11 May 2020 06:00:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit May 2020